/*

 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2014, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 */

#include <stdio.h>

#include <sys/types.h>

#include "precompiled.hpp"

#include "asm/assembler.hpp"

#include "asm/assembler.inline.hpp"

#include "interpreter/interpreter.hpp"

#ifndef PRODUCT

const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;

#endif

#include "compiler/disassembler.hpp"

#include "memory/resourceArea.hpp"

#include "runtime/interfaceSupport.inline.hpp"

#include "runtime/sharedRuntime.hpp"

#include "immediate_aarch64.hpp"

extern "C" void entry(CodeBuffer *cb);

#define __ _masm.

#ifdef PRODUCT

#define BLOCK_COMMENT(str) /* nothing */

#else

#define BLOCK_COMMENT(str) block_comment(str)

#endif

#define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")

static float unpack(unsigned value);

short Assembler::SIMD_Size_in_bytes[] = {

  // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q

       8,   16,   8,  16,   8,  16,   8,  16,  16

};

#ifdef ASSERT

static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {

    bool ok = true;

    for (unsigned int i = 0; i < len; i++) {

      if (insns[i] != insns1[i]) {

        ok = false;

        printf("Ours:\n");

        Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);

        printf("Theirs:\n");

        Disassembler::decode((address)&insns[i], (address)&insns[i+1]);

        printf("\n");

      }

    }

    assert(ok, "Assembler smoke test failed");

  }

#endif // ASSERT

void entry(CodeBuffer *cb) {

  // {

  //   for (int i = 0; i < 256; i+=16)

  //     {

  //    printf("\"%20.20g\", ", unpack(i));

  //    printf("\"%20.20g\", ", unpack(i+1));

  //     }

  //   printf("\n");

  // }

  Assembler _masm(cb);

  address entry = __ pc();

  // Smoke test for assembler

#ifdef ASSERT

// BEGIN  Generated code -- do not edit

// Generated by aarch64-asmtest.py

    Label back, forth;

    __ bind(back);

// ArithOp

    __ add(r15, r12, r16, Assembler::LSR, 30);         //        add        x15, x12, x16, LSR #30

    __ sub(r1, r15, r3, Assembler::LSR, 32);           //        sub        x1, x15, x3, LSR #32

    __ adds(r13, r25, r5, Assembler::LSL, 13);         //        adds        x13, x25, x5, LSL #13

    __ subs(r22, r28, r6, Assembler::ASR, 17);         //        subs        x22, x28, x6, ASR #17

    __ addw(r0, r9, r22, Assembler::ASR, 6);           //        add        w0, w9, w22, ASR #6

    __ subw(r19, r3, r25, Assembler::LSL, 21);         //        sub        w19, w3, w25, LSL #21

    __ addsw(r4, r19, r11, Assembler::LSL, 20);        //        adds        w4, w19, w11, LSL #20

    __ subsw(r24, r7, r19, Assembler::ASR, 0);         //        subs        w24, w7, w19, ASR #0

    __ andr(r30, r7, r11, Assembler::LSL, 48);         //        and        x30, x7, x11, LSL #48

    __ orr(r24, r8, r15, Assembler::LSL, 12);          //        orr        x24, x8, x15, LSL #12

    __ eor(r17, r9, r23, Assembler::LSL, 1);           //        eor        x17, x9, x23, LSL #1

    __ ands(r14, r11, r4, Assembler::LSR, 55);         //        ands        x14, x11, x4, LSR #55

    __ andw(r19, r7, r12, Assembler::LSR, 17);         //        and        w19, w7, w12, LSR #17

    __ orrw(r19, r27, r11, Assembler::ASR, 28);        //        orr        w19, w27, w11, ASR #28

    __ eorw(r30, r3, r22, Assembler::LSR, 31);         //        eor        w30, w3, w22, LSR #31

    __ andsw(r19, r26, r28, Assembler::ASR, 0);        //        ands        w19, w26, w28, ASR #0

    __ bic(r29, r6, r26, Assembler::LSL, 51);          //        bic        x29, x6, x26, LSL #51

    __ orn(r26, r27, r17, Assembler::LSL, 35);         //        orn        x26, x27, x17, LSL #35

    __ eon(r21, r4, r14, Assembler::LSL, 5);           //        eon        x21, x4, x14, LSL #5

    __ bics(r2, r15, r0, Assembler::ASR, 5);           //        bics        x2, x15, x0, ASR #5

    __ bicw(r2, r7, r2, Assembler::LSL, 29);           //        bic        w2, w7, w2, LSL #29

    __ ornw(r24, r12, r21, Assembler::LSR, 5);         //        orn        w24, w12, w21, LSR #5

    __ eonw(r30, r15, r19, Assembler::LSL, 2);         //        eon        w30, w15, w19, LSL #2

    __ bicsw(r30, r23, r17, Assembler::ASR, 28);       //        bics        w30, w23, w17, ASR #28

// AddSubImmOp

    __ addw(r4, r20, 660u);                            //        add        w4, w20, #660

    __ addsw(r2, r10, 710u);                           //        adds        w2, w10, #710

    __ subw(r19, r26, 244u);                           //        sub        w19, w26, #244

    __ subsw(r28, r13, 73u);                           //        subs        w28, w13, #73

    __ add(r2, r30, 862u);                             //        add        x2, x30, #862

    __ adds(r27, r16, 574u);                           //        adds        x27, x16, #574

    __ sub(r22, r9, 589u);                             //        sub        x22, x9, #589

    __ subs(r4, r1, 698u);                             //        subs        x4, x1, #698

// LogicalImmOp

    __ andw(r28, r19, 4294709247ul);                   //        and        w28, w19, #0xfffc0fff

    __ orrw(r27, r5, 536870910ul);                     //        orr        w27, w5, #0x1ffffffe

    __ eorw(r30, r20, 4294840319ul);                   //        eor        w30, w20, #0xfffe0fff

    __ andsw(r22, r26, 4294959615ul);                  //        ands        w22, w26, #0xffffe1ff

    __ andr(r5, r7, 4194300ul);                        //        and        x5, x7, #0x3ffffc

    __ orr(r13, r7, 18014398509481728ul);              //        orr        x13, x7, #0x3fffffffffff00

    __ eor(r7, r9, 18442240474082197503ul);            //        eor        x7, x9, #0xfff0000000003fff

    __ ands(r3, r0, 18374686479671656447ul);           //        ands        x3, x0, #0xff00000000007fff

// AbsOp

    __ b(__ pc());                                     //        b        .

    __ b(back);                                        //        b        back

    __ b(forth);                                       //        b        forth

    __ bl(__ pc());                                    //        bl        .

    __ bl(back);                                       //        bl        back

    __ bl(forth);                                      //        bl        forth

// RegAndAbsOp

    __ cbzw(r16, __ pc());                             //        cbz        w16, .

    __ cbzw(r16, back);                                //        cbz        w16, back

    __ cbzw(r16, forth);                               //        cbz        w16, forth

    __ cbnzw(r19, __ pc());                            //        cbnz        w19, .

    __ cbnzw(r19, back);                               //        cbnz        w19, back

    __ cbnzw(r19, forth);                              //        cbnz        w19, forth

    __ cbz(r5, __ pc());                               //        cbz        x5, .

    __ cbz(r5, back);                                  //        cbz        x5, back

    __ cbz(r5, forth);                                 //        cbz        x5, forth

    __ cbnz(r4, __ pc());                              //        cbnz        x4, .

    __ cbnz(r4, back);                                 //        cbnz        x4, back

    __ cbnz(r4, forth);                                //        cbnz        x4, forth

    __ adr(r27, __ pc());                              //        adr        x27, .

    __ adr(r27, back);                                 //        adr        x27, back

    __ adr(r27, forth);                                //        adr        x27, forth

    __ _adrp(r16, __ pc());                            //        adrp        x16, .

// RegImmAbsOp

    __ tbz(r28, 8, __ pc());                           //        tbz        x28, #8, .

    __ tbz(r28, 8, back);                              //        tbz        x28, #8, back

    __ tbz(r28, 8, forth);                             //        tbz        x28, #8, forth

    __ tbnz(r1, 1, __ pc());                           //        tbnz        x1, #1, .

    __ tbnz(r1, 1, back);                              //        tbnz        x1, #1, back

    __ tbnz(r1, 1, forth);                             //        tbnz        x1, #1, forth

// MoveWideImmOp

    __ movnw(r20, 8639, 16);                           //        movn        w20, #8639, lsl 16

    __ movzw(r7, 25835, 0);                            //        movz        w7, #25835, lsl 0

    __ movkw(r17, 7261, 0);                            //        movk        w17, #7261, lsl 0

    __ movn(r14, 2097, 32);                            //        movn        x14, #2097, lsl 32

    __ movz(r9, 16082, 0);                             //        movz        x9, #16082, lsl 0

    __ movk(r19, 13962, 16);                           //        movk        x19, #13962, lsl 16

// BitfieldOp

    __ sbfm(r9, r22, 6, 22);                           //        sbfm        x9, x22, #6, #22

    __ bfmw(r19, r0, 11, 0);                           //        bfm        w19, w0, #11, #0

    __ ubfmw(r10, r19, 11, 19);                        //        ubfm        w10, w19, #11, #19

    __ sbfm(r4, r15, 5, 17);                           //        sbfm        x4, x15, #5, #17

    __ bfm(r3, r5, 19, 28);                            //        bfm        x3, x5, #19, #28

    __ ubfm(r12, r28, 17, 2);                          //        ubfm        x12, x28, #17, #2

// ExtractOp

    __ extrw(r15, r0, r22, 3);                         //        extr        w15, w0, w22, #3

    __ extr(r6, r14, r14, 55);                         //        extr        x6, x14, x14, #55

// CondBranchOp

    __ br(Assembler::EQ, __ pc());                     //        b.EQ        .

    __ br(Assembler::EQ, back);                        //        b.EQ        back

    __ br(Assembler::EQ, forth);                       //        b.EQ        forth

    __ br(Assembler::NE, __ pc());                     //        b.NE        .

    __ br(Assembler::NE, back);                        //        b.NE        back

    __ br(Assembler::NE, forth);                       //        b.NE        forth

    __ br(Assembler::HS, __ pc());                     //        b.HS        .

    __ br(Assembler::HS, back);                        //        b.HS        back

    __ br(Assembler::HS, forth);                       //        b.HS        forth

    __ br(Assembler::CS, __ pc());                     //        b.CS        .

    __ br(Assembler::CS, back);                        //        b.CS        back

    __ br(Assembler::CS, forth);                       //        b.CS        forth

    __ br(Assembler::LO, __ pc());                     //        b.LO        .

    __ br(Assembler::LO, back);                        //        b.LO        back

    __ br(Assembler::LO, forth);                       //        b.LO        forth

    __ br(Assembler::CC, __ pc());                     //        b.CC        .

    __ br(Assembler::CC, back);                        //        b.CC        back

    __ br(Assembler::CC, forth);                       //        b.CC        forth

    __ br(Assembler::MI, __ pc());                     //        b.MI        .

    __ br(Assembler::MI, back);                        //        b.MI        back

    __ br(Assembler::MI, forth);                       //        b.MI        forth

    __ br(Assembler::PL, __ pc());                     //        b.PL        .

    __ br(Assembler::PL, back);                        //        b.PL        back

    __ br(Assembler::PL, forth);                       //        b.PL        forth

    __ br(Assembler::VS, __ pc());                     //        b.VS        .

    __ br(Assembler::VS, back);                        //        b.VS        back

    __ br(Assembler::VS, forth);                       //        b.VS        forth

    __ br(Assembler::VC, __ pc());                     //        b.VC        .

    __ br(Assembler::VC, back);                        //        b.VC        back

    __ br(Assembler::VC, forth);                       //        b.VC        forth

    __ br(Assembler::HI, __ pc());                     //        b.HI        .

    __ br(Assembler::HI, back);                        //        b.HI        back

    __ br(Assembler::HI, forth);                       //        b.HI        forth

    __ br(Assembler::LS, __ pc());                     //        b.LS        .

    __ br(Assembler::LS, back);                        //        b.LS        back

    __ br(Assembler::LS, forth);                       //        b.LS        forth

    __ br(Assembler::GE, __ pc());                     //        b.GE        .

    __ br(Assembler::GE, back);                        //        b.GE        back

    __ br(Assembler::GE, forth);                       //        b.GE        forth

    __ br(Assembler::LT, __ pc());                     //        b.LT        .

    __ br(Assembler::LT, back);                        //        b.LT        back

    __ br(Assembler::LT, forth);                       //        b.LT        forth

    __ br(Assembler::GT, __ pc());                     //        b.GT        .

    __ br(Assembler::GT, back);                        //        b.GT        back

    __ br(Assembler::GT, forth);                       //        b.GT        forth

    __ br(Assembler::LE, __ pc());                     //        b.LE        .

    __ br(Assembler::LE, back);                        //        b.LE        back

    __ br(Assembler::LE, forth);                       //        b.LE        forth

    __ br(Assembler::AL, __ pc());                     //        b.AL        .

    __ br(Assembler::AL, back);                        //        b.AL        back

    __ br(Assembler::AL, forth);                       //        b.AL        forth

    __ br(Assembler::NV, __ pc());                     //        b.NV        .

    __ br(Assembler::NV, back);                        //        b.NV        back

    __ br(Assembler::NV, forth);                       //        b.NV        forth

// ImmOp

    __ svc(22064);                                     //        svc        #22064

    __ hvc(533);                                       //        hvc        #533

    __ smc(9942);                                      //        smc        #9942

    __ brk(4714);                                      //        brk        #4714

    __ hlt(4302);                                      //        hlt        #4302

// Op

    __ nop();                                          //        nop

    __ eret();                                         //        eret

    __ drps();                                         //        drps

    __ isb();                                          //        isb

// SystemOp

    __ dsb(Assembler::OSH);                            //        dsb        OSH

    __ dmb(Assembler::NSHLD);                          //        dmb        NSHLD

// OneRegOp

    __ br(r20);                                        //        br        x20

    __ blr(r2);                                        //        blr        x2

// LoadStoreExclusiveOp

    __ stxr(r18, r23, r0);                             //        stxr        w18, x23, [x0]

    __ stlxr(r30, r5, r22);                            //        stlxr        w30, x5, [x22]

    __ ldxr(r5, r8);                                   //        ldxr        x5, [x8]

    __ ldaxr(r20, r16);                                //        ldaxr        x20, [x16]

    __ stlr(r6, r11);                                  //        stlr        x6, [x11]

    __ ldar(r6, r27);                                  //        ldar        x6, [x27]

// LoadStoreExclusiveOp

    __ stxrw(r10, r17, r5);                            //        stxr        w10, w17, [x5]

    __ stlxrw(r22, r9, r12);                           //        stlxr        w22, w9, [x12]

    __ ldxrw(r27, r8);                                 //        ldxr        w27, [x8]

    __ ldaxrw(r23, r2);                                //        ldaxr        w23, [x2]

    __ stlrw(r26, r29);                                //        stlr        w26, [x29]

    __ ldarw(r13, r10);                                //        ldar        w13, [x10]

// LoadStoreExclusiveOp

    __ stxrh(r25, r28, r27);                           //        stxrh        w25, w28, [x27]

    __ stlxrh(r29, r22, r12);                          //        stlxrh        w29, w22, [x12]

    __ ldxrh(r22, r28);                                //        ldxrh        w22, [x28]

    __ ldaxrh(r3, r30);                                //        ldaxrh        w3, [x30]

    __ stlrh(r24, r15);                                //        stlrh        w24, [x15]

    __ ldarh(r27, r26);                                //        ldarh        w27, [x26]

// LoadStoreExclusiveOp

    __ stxrb(r11, r10, r19);                           //        stxrb        w11, w10, [x19]

    __ stlxrb(r23, r27, r22);                          //        stlxrb        w23, w27, [x22]

    __ ldxrb(r24, r16);                                //        ldxrb        w24, [x16]

    __ ldaxrb(r24, r1);                                //        ldaxrb        w24, [x1]

    __ stlrb(r5, r29);                                 //        stlrb        w5, [x29]

    __ ldarb(r24, r16);                                //        ldarb        w24, [x16]

// LoadStoreExclusiveOp

    __ ldxp(r25, r24, r17);                            //        ldxp        x25, x24, [x17]

    __ ldaxp(r22, r12, r19);                           //        ldaxp        x22, x12, [x19]

    __ stxp(r0, r26, r21, r25);                        //        stxp        w0, x26, x21, [x25]

    __ stlxp(r1, r6, r11, r5);                         //        stlxp        w1, x6, x11, [x5]

// LoadStoreExclusiveOp

    __ ldxpw(r13, r14, r4);                            //        ldxp        w13, w14, [x4]

    __ ldaxpw(r17, r2, r6);                            //        ldaxp        w17, w2, [x6]

    __ stxpw(r15, r3, r9, r18);                        //        stxp        w15, w3, w9, [x18]

    __ stlxpw(r18, r17, r4, r9);                       //        stlxp        w18, w17, w4, [x9]

// base_plus_unscaled_offset

// LoadStoreOp

    __ str(r23, Address(r21, -49));                    //        str        x23, [x21, -49]

    __ strw(r21, Address(r2, 63));                     //        str        w21, [x2, 63]

    __ strb(r27, Address(r28, 11));                    //        strb        w27, [x28, 11]

    __ strh(r29, Address(r15, -13));                   //        strh        w29, [x15, -13]

    __ ldr(r14, Address(r30, -45));                    //        ldr        x14, [x30, -45]

    __ ldrw(r29, Address(r28, 53));                    //        ldr        w29, [x28, 53]

    __ ldrb(r20, Address(r26, 7));                     //        ldrb        w20, [x26, 7]

    __ ldrh(r25, Address(r2, -50));                    //        ldrh        w25, [x2, -50]

    __ ldrsb(r3, Address(r10, -15));                   //        ldrsb        x3, [x10, -15]

    __ ldrsh(r14, Address(r15, 19));                   //        ldrsh        x14, [x15, 19]

    __ ldrshw(r29, Address(r11, -5));                  //        ldrsh        w29, [x11, -5]

    __ ldrsw(r15, Address(r5, -71));                   //        ldrsw        x15, [x5, -71]

    __ ldrd(v19, Address(r12, 3));                     //        ldr        d19, [x12, 3]

    __ ldrs(v12, Address(r27, 42));                    //        ldr        s12, [x27, 42]

    __ strd(v22, Address(r28, 125));                   //        str        d22, [x28, 125]

    __ strs(v24, Address(r15, -20));                   //        str        s24, [x15, -20]

// pre

// LoadStoreOp

    __ str(r8, Address(__ pre(r28, -24)));             //        str        x8, [x28, -24]!

    __ strw(r6, Address(__ pre(r15, 37)));             //        str        w6, [x15, 37]!

    __ strb(r7, Address(__ pre(r1, 7)));               //        strb        w7, [x1, 7]!

    __ strh(r0, Address(__ pre(r17, 30)));             //        strh        w0, [x17, 30]!

    __ ldr(r25, Address(__ pre(r29, 84)));             //        ldr        x25, [x29, 84]!

    __ ldrw(r26, Address(__ pre(r20, -52)));           //        ldr        w26, [x20, -52]!

    __ ldrb(r26, Address(__ pre(r29, -25)));           //        ldrb        w26, [x29, -25]!

    __ ldrh(r4, Address(__ pre(r25, 26)));             //        ldrh        w4, [x25, 26]!

    __ ldrsb(r28, Address(__ pre(r8, -21)));           //        ldrsb        x28, [x8, -21]!

    __ ldrsh(r17, Address(__ pre(r14, -6)));           //        ldrsh        x17, [x14, -6]!

    __ ldrshw(r28, Address(__ pre(r23, 10)));          //        ldrsh        w28, [x23, 10]!

    __ ldrsw(r30, Address(__ pre(r27, -64)));          //        ldrsw        x30, [x27, -64]!

    __ ldrd(v20, Address(__ pre(r30, -242)));          //        ldr        d20, [x30, -242]!

    __ ldrs(v17, Address(__ pre(r27, 20)));            //        ldr        s17, [x27, 20]!

    __ strd(v7, Address(__ pre(r3, 17)));              //        str        d7, [x3, 17]!

    __ strs(v13, Address(__ pre(r11, -16)));           //        str        s13, [x11, -16]!

// post

// LoadStoreOp

    __ str(r6, Address(__ post(r9, -61)));             //        str        x6, [x9], -61

    __ strw(r16, Address(__ post(r5, -29)));           //        str        w16, [x5], -29

    __ strb(r29, Address(__ post(r29, 15)));           //        strb        w29, [x29], 15

    __ strh(r4, Address(__ post(r20, 18)));            //        strh        w4, [x20], 18

    __ ldr(r19, Address(__ post(r18, 46)));            //        ldr        x19, [x18], 46

    __ ldrw(r22, Address(__ post(r2, 23)));            //        ldr        w22, [x2], 23

    __ ldrb(r7, Address(__ post(r3, -30)));            //        ldrb        w7, [x3], -30

    __ ldrh(r11, Address(__ post(r12, -29)));          //        ldrh        w11, [x12], -29

    __ ldrsb(r8, Address(__ post(r6, -29)));           //        ldrsb        x8, [x6], -29

    __ ldrsh(r24, Address(__ post(r23, 4)));           //        ldrsh        x24, [x23], 4

    __ ldrshw(r17, Address(__ post(r16, 0)));          //        ldrsh        w17, [x16], 0

    __ ldrsw(r0, Address(__ post(r20, -8)));           //        ldrsw        x0, [x20], -8

    __ ldrd(v20, Address(__ post(r2, -126)));          //        ldr        d20, [x2], -126

    __ ldrs(v19, Address(__ post(r30, -104)));         //        ldr        s19, [x30], -104

    __ strd(v4, Address(__ post(r17, 118)));           //        str        d4, [x17], 118

    __ strs(v21, Address(__ post(r19, -112)));         //        str        s21, [x19], -112

// base_plus_reg

// LoadStoreOp

    __ str(r26, Address(r2, r19, Address::lsl(3)));    //        str        x26, [x2, x19, lsl #3]

    __ strw(r9, Address(r0, r15, Address::sxtw(2)));   //        str        w9, [x0, w15, sxtw #2]

    __ strb(r26, Address(r12, r1, Address::lsl(0)));   //        strb        w26, [x12, x1, lsl #0]

    __ strh(r21, Address(r11, r10, Address::lsl(1)));  //        strh        w21, [x11, x10, lsl #1]

    __ ldr(r16, Address(r23, r16, Address::sxtx(0)));  //        ldr        x16, [x23, x16, sxtx #0]

    __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); //        ldr        w10, [x11, w17, sxtw #2]

    __ ldrb(r13, Address(r23, r11, Address::lsl(0)));  //        ldrb        w13, [x23, x11, lsl #0]

    __ ldrh(r27, Address(r4, r21, Address::lsl(0)));   //        ldrh        w27, [x4, x21, lsl #0]

    __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); //        ldrsb        x26, [x8, w15, sxtw #0]

    __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); //        ldrsh        x21, [x10, w2, sxtw #0]

    __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); //        ldrsh        w8, [x30, x14, lsl #0]

    __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); //        ldrsw        x29, [x14, x20, sxtx #2]

    __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); //        ldr        d30, [x27, x22, sxtx #0]

    __ ldrs(v13, Address(r9, r22, Address::lsl(0)));   //        ldr        s13, [x9, x22, lsl #0]

    __ strd(v8, Address(r25, r17, Address::sxtw(3)));  //        str        d8, [x25, w17, sxtw #3]

    __ strs(v1, Address(r24, r5, Address::uxtw(2)));   //        str        s1, [x24, w5, uxtw #2]

// base_plus_scaled_offset

// LoadStoreOp

    __ str(r10, Address(r21, 14496));                  //        str        x10, [x21, 14496]

    __ strw(r18, Address(r29, 7228));                  //        str        w18, [x29, 7228]

    __ strb(r23, Address(r3, 2018));                   //        strb        w23, [x3, 2018]

    __ strh(r28, Address(r11, 3428));                  //        strh        w28, [x11, 3428]

    __ ldr(r24, Address(r26, 14376));                  //        ldr        x24, [x26, 14376]

    __ ldrw(r21, Address(r2, 6972));                   //        ldr        w21, [x2, 6972]

    __ ldrb(r4, Address(r5, 1848));                    //        ldrb        w4, [x5, 1848]

    __ ldrh(r14, Address(r14, 3112));                  //        ldrh        w14, [x14, 3112]

    __ ldrsb(r4, Address(r27, 1959));                  //        ldrsb        x4, [x27, 1959]

    __ ldrsh(r4, Address(r27, 3226));                  //        ldrsh        x4, [x27, 3226]

    __ ldrshw(r10, Address(r28, 3286));                //        ldrsh        w10, [x28, 3286]

    __ ldrsw(r10, Address(r17, 7912));                 //        ldrsw        x10, [x17, 7912]

    __ ldrd(v13, Address(r28, 13400));                 //        ldr        d13, [x28, 13400]

    __ ldrs(v24, Address(r3, 7596));                   //        ldr        s24, [x3, 7596]

    __ strd(v2, Address(r12, 15360));                  //        str        d2, [x12, 15360]

    __ strs(v17, Address(r1, 6492));                   //        str        s17, [x1, 6492]

// pcrel

// LoadStoreOp

    __ ldr(r16, __ pc());                              //        ldr        x16, .

    __ ldrw(r13, __ pc());                             //        ldr        w13, .

// LoadStoreOp

    __ prfm(Address(r18, -127));                       //        prfm        PLDL1KEEP, [x18, -127]

// LoadStoreOp

    __ prfm(back);                                     //        prfm        PLDL1KEEP, back

// LoadStoreOp

    __ prfm(Address(r20, r2, Address::lsl(3)));        //        prfm        PLDL1KEEP, [x20, x2, lsl #3]

// LoadStoreOp

    __ prfm(Address(r9, 13808));                       //        prfm        PLDL1KEEP, [x9, 13808]

// AddSubCarryOp

    __ adcw(r8, r23, r2);                              //        adc        w8, w23, w2

    __ adcsw(r24, r3, r19);                            //        adcs        w24, w3, w19

    __ sbcw(r22, r24, r29);                            //        sbc        w22, w24, w29

    __ sbcsw(r12, r27, r3);                            //        sbcs        w12, w27, w3

    __ adc(r11, r23, r1);                              //        adc        x11, x23, x1

    __ adcs(r29, r5, r23);                             //        adcs        x29, x5, x23

    __ sbc(r9, r25, r12);                              //        sbc        x9, x25, x12

    __ sbcs(r12, r0, r22);                             //        sbcs        x12, x0, x22

// AddSubExtendedOp

    __ addw(r26, r12, r3, ext::uxtw, 1);               //        add        w26, w12, w3, uxtw #1

    __ addsw(r20, r16, r18, ext::sxtb, 2);             //        adds        w20, w16, w18, sxtb #2

    __ sub(r30, r30, r7, ext::uxtw, 2);                //        sub        x30, x30, x7, uxtw #2

    __ subsw(r11, r21, r2, ext::uxth, 3);              //        subs        w11, w21, w2, uxth #3

    __ add(r2, r26, r1, ext::uxtw, 2);                 //        add        x2, x26, x1, uxtw #2

    __ adds(r18, r29, r20, ext::sxth, 1);              //        adds        x18, x29, x20, sxth #1

    __ sub(r14, r16, r4, ext::uxtw, 4);                //        sub        x14, x16, x4, uxtw #4

    __ subs(r0, r17, r23, ext::sxtb, 3);               //        subs        x0, x17, x23, sxtb #3

// ConditionalCompareOp

    __ ccmnw(r20, r22, 3u, Assembler::PL);             //        ccmn        w20, w22, #3, PL

    __ ccmpw(r25, r2, 1u, Assembler::EQ);              //        ccmp        w25, w2, #1, EQ

    __ ccmn(r18, r24, 7u, Assembler::GT);              //        ccmn        x18, x24, #7, GT

    __ ccmp(r8, r13, 6u, Assembler::PL);               //        ccmp        x8, x13, #6, PL

// ConditionalCompareImmedOp

    __ ccmnw(r9, 2, 4, Assembler::VS);                 //        ccmn        w9, #2, #4, VS

    __ ccmpw(r2, 27, 7, Assembler::EQ);                //        ccmp        w2, #27, #7, EQ

    __ ccmn(r16, 1, 2, Assembler::CC);                 //        ccmn        x16, #1, #2, CC

    __ ccmp(r17, 31, 3, Assembler::LT);                //        ccmp        x17, #31, #3, LT

// ConditionalSelectOp

    __ cselw(r23, r27, r23, Assembler::LS);            //        csel        w23, w27, w23, LS

    __ csincw(r10, r0, r6, Assembler::VS);             //        csinc        w10, w0, w6, VS

    __ csinvw(r11, r0, r9, Assembler::CC);             //        csinv        w11, w0, w9, CC

    __ csnegw(r17, r27, r18, Assembler::LO);           //        csneg        w17, w27, w18, LO

    __ csel(r12, r16, r11, Assembler::VC);             //        csel        x12, x16, x11, VC

    __ csinc(r6, r28, r6, Assembler::HI);              //        csinc        x6, x28, x6, HI

    __ csinv(r13, r27, r26, Assembler::VC);            //        csinv        x13, x27, x26, VC

    __ csneg(r29, r22, r18, Assembler::PL);            //        csneg        x29, x22, x18, PL

// TwoRegOp

    __ rbitw(r12, r19);                                //        rbit        w12, w19

    __ rev16w(r23, r18);                               //        rev16        w23, w18

    __ revw(r9, r28);                                  //        rev        w9, w28

    __ clzw(r2, r19);                                  //        clz        w2, w19

    __ clsw(r25, r29);                                 //        cls        w25, w29

    __ rbit(r4, r23);                                  //        rbit        x4, x23

    __ rev16(r29, r18);                                //        rev16        x29, x18

    __ rev32(r7, r8);                                  //        rev32        x7, x8

    __ rev(r13, r17);                                  //        rev        x13, x17

    __ clz(r17, r0);                                   //        clz        x17, x0

    __ cls(r18, r26);                                  //        cls        x18, x26

// ThreeRegOp

    __ udivw(r11, r12, r16);                           //        udiv        w11, w12, w16

    __ sdivw(r4, r9, r7);                              //        sdiv        w4, w9, w7

    __ lslvw(r12, r7, r16);                            //        lslv        w12, w7, w16

    __ lsrvw(r19, r16, r23);                           //        lsrv        w19, w16, w23

    __ asrvw(r7, r4, r6);                              //        asrv        w7, w4, w6

    __ rorvw(r21, r20, r23);                           //        rorv        w21, w20, w23

    __ udiv(r16, r12, r28);                            //        udiv        x16, x12, x28

    __ sdiv(r4, r12, r13);                             //        sdiv        x4, x12, x13

    __ lslv(r9, r13, r7);                              //        lslv        x9, x13, x7

    __ lsrv(r28, r27, r15);                            //        lsrv        x28, x27, x15

    __ asrv(r20, r30, r14);                            //        asrv        x20, x30, x14

    __ rorv(r14, r18, r30);                            //        rorv        x14, x18, x30