hotspot/src/share/vm/runtime/orderAccess.hpp
author kvn
Thu, 10 Jun 2010 13:04:20 -0700
changeset 5883 8dc4bdc132d5
parent 5547 f4b087cbb361
child 6253 228a0240f71e
permissions -rw-r--r--
6730276: JDI_REGRESSION tests fail with "Error: count must be non-zero" error on x86 Summary: Modify assembler code to check for 0 count for all copy routines. Reviewed-by: never, ysr, jcoomes
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
     1
/*
5547
f4b087cbb361 6941466: Oracle rebranding changes for Hotspot repositories
trims
parents: 3261
diff changeset
     2
 * Copyright (c) 2003, 2009, Oracle and/or its affiliates. All rights reserved.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
     3
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
489c9b5090e2 Initial load
duke
parents:
diff changeset
     4
 *
489c9b5090e2 Initial load
duke
parents:
diff changeset
     5
 * This code is free software; you can redistribute it and/or modify it
489c9b5090e2 Initial load
duke
parents:
diff changeset
     6
 * under the terms of the GNU General Public License version 2 only, as
489c9b5090e2 Initial load
duke
parents:
diff changeset
     7
 * published by the Free Software Foundation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
     8
 *
489c9b5090e2 Initial load
duke
parents:
diff changeset
     9
 * This code is distributed in the hope that it will be useful, but WITHOUT
489c9b5090e2 Initial load
duke
parents:
diff changeset
    10
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
489c9b5090e2 Initial load
duke
parents:
diff changeset
    11
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
489c9b5090e2 Initial load
duke
parents:
diff changeset
    12
 * version 2 for more details (a copy is included in the LICENSE file that
489c9b5090e2 Initial load
duke
parents:
diff changeset
    13
 * accompanied this code).
489c9b5090e2 Initial load
duke
parents:
diff changeset
    14
 *
489c9b5090e2 Initial load
duke
parents:
diff changeset
    15
 * You should have received a copy of the GNU General Public License version
489c9b5090e2 Initial load
duke
parents:
diff changeset
    16
 * 2 along with this work; if not, write to the Free Software Foundation,
489c9b5090e2 Initial load
duke
parents:
diff changeset
    17
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    18
 *
5547
f4b087cbb361 6941466: Oracle rebranding changes for Hotspot repositories
trims
parents: 3261
diff changeset
    19
 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
f4b087cbb361 6941466: Oracle rebranding changes for Hotspot repositories
trims
parents: 3261
diff changeset
    20
 * or visit www.oracle.com if you need additional information or have any
f4b087cbb361 6941466: Oracle rebranding changes for Hotspot repositories
trims
parents: 3261
diff changeset
    21
 * questions.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
    22
 *
489c9b5090e2 Initial load
duke
parents:
diff changeset
    23
 */
489c9b5090e2 Initial load
duke
parents:
diff changeset
    24
489c9b5090e2 Initial load
duke
parents:
diff changeset
    25
//                Memory Access Ordering Model
489c9b5090e2 Initial load
duke
parents:
diff changeset
    26
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    27
// This interface is based on the JSR-133 Cookbook for Compiler Writers
489c9b5090e2 Initial load
duke
parents:
diff changeset
    28
// and on the IA64 memory model.  It is the dynamic equivalent of the
489c9b5090e2 Initial load
duke
parents:
diff changeset
    29
// C/C++ volatile specifier.  I.e., volatility restricts compile-time
489c9b5090e2 Initial load
duke
parents:
diff changeset
    30
// memory access reordering in a way similar to what we want to occur
489c9b5090e2 Initial load
duke
parents:
diff changeset
    31
// at runtime.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    32
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    33
// In the following, the terms 'previous', 'subsequent', 'before',
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 1
diff changeset
    34
// 'after', 'preceding' and 'succeeding' refer to program order.  The
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
    35
// terms 'down' and 'below' refer to forward load or store motion
489c9b5090e2 Initial load
duke
parents:
diff changeset
    36
// relative to program order, while 'up' and 'above' refer to backward
489c9b5090e2 Initial load
duke
parents:
diff changeset
    37
// motion.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    38
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    39
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    40
// We define four primitive memory barrier operations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    41
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    42
// LoadLoad:   Load1(s); LoadLoad; Load2
489c9b5090e2 Initial load
duke
parents:
diff changeset
    43
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    44
// Ensures that Load1 completes (obtains the value it loads from memory)
489c9b5090e2 Initial load
duke
parents:
diff changeset
    45
// before Load2 and any subsequent load operations.  Loads before Load1
489c9b5090e2 Initial load
duke
parents:
diff changeset
    46
// may *not* float below Load2 and any subsequent load operations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    47
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    48
// StoreStore: Store1(s); StoreStore; Store2
489c9b5090e2 Initial load
duke
parents:
diff changeset
    49
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    50
// Ensures that Store1 completes (the effect on memory of Store1 is made
489c9b5090e2 Initial load
duke
parents:
diff changeset
    51
// visible to other processors) before Store2 and any subsequent store
489c9b5090e2 Initial load
duke
parents:
diff changeset
    52
// operations.  Stores before Store1 may *not* float below Store2 and any
489c9b5090e2 Initial load
duke
parents:
diff changeset
    53
// subsequent store operations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    54
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    55
// LoadStore:  Load1(s); LoadStore; Store2
489c9b5090e2 Initial load
duke
parents:
diff changeset
    56
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    57
// Ensures that Load1 completes before Store2 and any subsequent store
489c9b5090e2 Initial load
duke
parents:
diff changeset
    58
// operations.  Loads before Load1 may *not* float below Store2 and any
489c9b5090e2 Initial load
duke
parents:
diff changeset
    59
// subseqeuent store operations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    60
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    61
// StoreLoad:  Store1(s); StoreLoad; Load2
489c9b5090e2 Initial load
duke
parents:
diff changeset
    62
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    63
// Ensures that Store1 completes before Load2 and any subsequent load
489c9b5090e2 Initial load
duke
parents:
diff changeset
    64
// operations.  Stores before Store1 may *not* float below Load2 and any
489c9b5090e2 Initial load
duke
parents:
diff changeset
    65
// subseqeuent load operations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    66
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    67
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    68
// We define two further operations, 'release' and 'acquire'.  They are
489c9b5090e2 Initial load
duke
parents:
diff changeset
    69
// mirror images of each other.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    70
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    71
// Execution by a processor of release makes the effect of all memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
    72
// accesses issued by it previous to the release visible to all
489c9b5090e2 Initial load
duke
parents:
diff changeset
    73
// processors *before* the release completes.  The effect of subsequent
489c9b5090e2 Initial load
duke
parents:
diff changeset
    74
// memory accesses issued by it *may* be made visible *before* the
489c9b5090e2 Initial load
duke
parents:
diff changeset
    75
// release.  I.e., subsequent memory accesses may float above the
489c9b5090e2 Initial load
duke
parents:
diff changeset
    76
// release, but prior ones may not float below it.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    77
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    78
// Execution by a processor of acquire makes the effect of all memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
    79
// accesses issued by it subsequent to the acquire visible to all
489c9b5090e2 Initial load
duke
parents:
diff changeset
    80
// processors *after* the acquire completes.  The effect of prior memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
    81
// accesses issued by it *may* be made visible *after* the acquire.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    82
// I.e., prior memory accesses may float below the acquire, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
    83
// subsequent ones may not float above it.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    84
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    85
// Finally, we define a 'fence' operation, which conceptually is a
489c9b5090e2 Initial load
duke
parents:
diff changeset
    86
// release combined with an acquire.  In the real world these operations
489c9b5090e2 Initial load
duke
parents:
diff changeset
    87
// require one or more machine instructions which can float above and
489c9b5090e2 Initial load
duke
parents:
diff changeset
    88
// below the release or acquire, so we usually can't just issue the
489c9b5090e2 Initial load
duke
parents:
diff changeset
    89
// release-acquire back-to-back.  All machines we know of implement some
489c9b5090e2 Initial load
duke
parents:
diff changeset
    90
// sort of memory fence instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    91
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    92
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    93
// The standalone implementations of release and acquire need an associated
489c9b5090e2 Initial load
duke
parents:
diff changeset
    94
// dummy volatile store or load respectively.  To avoid redundant operations,
489c9b5090e2 Initial load
duke
parents:
diff changeset
    95
// we can define the composite operators: 'release_store', 'store_fence' and
489c9b5090e2 Initial load
duke
parents:
diff changeset
    96
// 'load_acquire'.  Here's a summary of the machine instructions corresponding
489c9b5090e2 Initial load
duke
parents:
diff changeset
    97
// to each operation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
    98
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
    99
//               sparc RMO             ia64             x86
489c9b5090e2 Initial load
duke
parents:
diff changeset
   100
// ---------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   101
// fence         membar #LoadStore |   mf               lock addl 0,(sp)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   102
//                      #StoreStore |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   103
//                      #LoadLoad |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   104
//                      #StoreLoad
489c9b5090e2 Initial load
duke
parents:
diff changeset
   105
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   106
// release       membar #LoadStore |   st.rel [sp]=r0   movl $0,<dummy>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   107
//                      #StoreStore
489c9b5090e2 Initial load
duke
parents:
diff changeset
   108
//               st %g0,[]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   109
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   110
// acquire       ld [%sp],%g0          ld.acq <r>=[sp]  movl (sp),<r>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   111
//               membar #LoadLoad |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   112
//                      #LoadStore
489c9b5090e2 Initial load
duke
parents:
diff changeset
   113
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   114
// release_store membar #LoadStore |   st.rel           <store>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   115
//                      #StoreStore
489c9b5090e2 Initial load
duke
parents:
diff changeset
   116
//               st
489c9b5090e2 Initial load
duke
parents:
diff changeset
   117
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   118
// store_fence   st                    st               lock xchg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   119
//               fence                 mf
489c9b5090e2 Initial load
duke
parents:
diff changeset
   120
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   121
// load_acquire  ld                    ld.acq           <load>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   122
//               membar #LoadLoad |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   123
//                      #LoadStore
489c9b5090e2 Initial load
duke
parents:
diff changeset
   124
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   125
// Using only release_store and load_acquire, we can implement the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   126
// following ordered sequences.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   127
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   128
// 1. load, load   == load_acquire,  load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   129
//                 or load_acquire,  load_acquire
489c9b5090e2 Initial load
duke
parents:
diff changeset
   130
// 2. load, store  == load,          release_store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   131
//                 or load_acquire,  store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   132
//                 or load_acquire,  release_store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   133
// 3. store, store == store,         release_store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   134
//                 or release_store, release_store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   135
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   136
// These require no membar instructions for sparc-TSO and no extra
489c9b5090e2 Initial load
duke
parents:
diff changeset
   137
// instructions for ia64.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   138
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   139
// Ordering a load relative to preceding stores requires a store_fence,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   140
// which implies a membar #StoreLoad between the store and load under
489c9b5090e2 Initial load
duke
parents:
diff changeset
   141
// sparc-TSO.  A fence is required by ia64.  On x86, we use locked xchg.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   142
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   143
// 4. store, load  == store_fence, load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   144
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   145
// Use store_fence to make sure all stores done in an 'interesting'
489c9b5090e2 Initial load
duke
parents:
diff changeset
   146
// region are made visible prior to both subsequent loads and stores.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   147
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   148
// Conventional usage is to issue a load_acquire for ordered loads.  Use
489c9b5090e2 Initial load
duke
parents:
diff changeset
   149
// release_store for ordered stores when you care only that prior stores
489c9b5090e2 Initial load
duke
parents:
diff changeset
   150
// are visible before the release_store, but don't care exactly when the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   151
// store associated with the release_store becomes visible.  Use
489c9b5090e2 Initial load
duke
parents:
diff changeset
   152
// release_store_fence to update values like the thread state, where we
489c9b5090e2 Initial load
duke
parents:
diff changeset
   153
// don't want the current thread to continue until all our prior memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
   154
// accesses (including the new thread state) are visible to other threads.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   155
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   156
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   157
//                C++ Volatility
489c9b5090e2 Initial load
duke
parents:
diff changeset
   158
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   159
// C++ guarantees ordering at operations termed 'sequence points' (defined
489c9b5090e2 Initial load
duke
parents:
diff changeset
   160
// to be volatile accesses and calls to library I/O functions).  'Side
489c9b5090e2 Initial load
duke
parents:
diff changeset
   161
// effects' (defined as volatile accesses, calls to library I/O functions
489c9b5090e2 Initial load
duke
parents:
diff changeset
   162
// and object modification) previous to a sequence point must be visible
489c9b5090e2 Initial load
duke
parents:
diff changeset
   163
// at that sequence point.  See the C++ standard, section 1.9, titled
489c9b5090e2 Initial load
duke
parents:
diff changeset
   164
// "Program Execution".  This means that all barrier implementations,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   165
// including standalone loadload, storestore, loadstore, storeload, acquire
489c9b5090e2 Initial load
duke
parents:
diff changeset
   166
// and release must include a sequence point, usually via a volatile memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
   167
// access.  Other ways to guarantee a sequence point are, e.g., use of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   168
// indirect calls and linux's __asm__ volatile.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   169
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   170
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   171
//                os::is_MP Considered Redundant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   172
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   173
// Callers of this interface do not need to test os::is_MP() before
489c9b5090e2 Initial load
duke
parents:
diff changeset
   174
// issuing an operation. The test is taken care of by the implementation
489c9b5090e2 Initial load
duke
parents:
diff changeset
   175
// of the interface (depending on the vm version and platform, the test
489c9b5090e2 Initial load
duke
parents:
diff changeset
   176
// may or may not be actually done by the implementation).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   177
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   178
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   179
//                A Note on Memory Ordering and Cache Coherency
489c9b5090e2 Initial load
duke
parents:
diff changeset
   180
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   181
// Cache coherency and memory ordering are orthogonal concepts, though they
489c9b5090e2 Initial load
duke
parents:
diff changeset
   182
// interact.  E.g., all existing itanium machines are cache-coherent, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
   183
// the hardware can freely reorder loads wrt other loads unless it sees a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   184
// load-acquire instruction.  All existing sparc machines are cache-coherent
489c9b5090e2 Initial load
duke
parents:
diff changeset
   185
// and, unlike itanium, TSO guarantees that the hardware orders loads wrt
489c9b5090e2 Initial load
duke
parents:
diff changeset
   186
// loads and stores, and stores wrt to each other.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   187
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   188
// Consider the implementation of loadload.  *If* your platform *isn't*
489c9b5090e2 Initial load
duke
parents:
diff changeset
   189
// cache-coherent, then loadload must not only prevent hardware load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   190
// instruction reordering, but it must *also* ensure that subsequent
489c9b5090e2 Initial load
duke
parents:
diff changeset
   191
// loads from addresses that could be written by other processors (i.e.,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   192
// that are broadcast by other processors) go all the way to the first
489c9b5090e2 Initial load
duke
parents:
diff changeset
   193
// level of memory shared by those processors and the one issuing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   194
// the loadload.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   195
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   196
// So if we have a MP that has, say, a per-processor D$ that doesn't see
489c9b5090e2 Initial load
duke
parents:
diff changeset
   197
// writes by other processors, and has a shared E$ that does, the loadload
489c9b5090e2 Initial load
duke
parents:
diff changeset
   198
// barrier would have to make sure that either
489c9b5090e2 Initial load
duke
parents:
diff changeset
   199
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   200
// 1. cache lines in the issuing processor's D$ that contained data from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   201
// addresses that could be written by other processors are invalidated, so
489c9b5090e2 Initial load
duke
parents:
diff changeset
   202
// subsequent loads from those addresses go to the E$, (it could do this
489c9b5090e2 Initial load
duke
parents:
diff changeset
   203
// by tagging such cache lines as 'shared', though how to tell the hardware
489c9b5090e2 Initial load
duke
parents:
diff changeset
   204
// to do the tagging is an interesting problem), or
489c9b5090e2 Initial load
duke
parents:
diff changeset
   205
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   206
// 2. there never are such cache lines in the issuing processor's D$, which
489c9b5090e2 Initial load
duke
parents:
diff changeset
   207
// means all references to shared data (however identified: see above)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   208
// bypass the D$ (i.e., are satisfied from the E$).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   209
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   210
// If your machine doesn't have an E$, substitute 'main memory' for 'E$'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   211
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   212
// Either of these alternatives is a pain, so no current machine we know of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   213
// has incoherent caches.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   214
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   215
// If loadload didn't have these properties, the store-release sequence for
489c9b5090e2 Initial load
duke
parents:
diff changeset
   216
// publishing a shared data structure wouldn't work, because a processor
489c9b5090e2 Initial load
duke
parents:
diff changeset
   217
// trying to read data newly published by another processor might go to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   218
// its own incoherent caches to satisfy the read instead of to the newly
489c9b5090e2 Initial load
duke
parents:
diff changeset
   219
// written shared memory.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   220
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   221
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   222
//                NOTE WELL!!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   223
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   224
//                A Note on MutexLocker and Friends
489c9b5090e2 Initial load
duke
parents:
diff changeset
   225
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   226
// See mutexLocker.hpp.  We assume throughout the VM that MutexLocker's
489c9b5090e2 Initial load
duke
parents:
diff changeset
   227
// and friends' constructors do a fence, a lock and an acquire *in that
489c9b5090e2 Initial load
duke
parents:
diff changeset
   228
// order*.  And that their destructors do a release and unlock, in *that*
489c9b5090e2 Initial load
duke
parents:
diff changeset
   229
// order.  If their implementations change such that these assumptions
489c9b5090e2 Initial load
duke
parents:
diff changeset
   230
// are violated, a whole lot of code will break.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   231
489c9b5090e2 Initial load
duke
parents:
diff changeset
   232
class OrderAccess : AllStatic {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   233
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   234
  static void     loadload();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   235
  static void     storestore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   236
  static void     loadstore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   237
  static void     storeload();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   238
489c9b5090e2 Initial load
duke
parents:
diff changeset
   239
  static void     acquire();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   240
  static void     release();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   241
  static void     fence();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   242
489c9b5090e2 Initial load
duke
parents:
diff changeset
   243
  static jbyte    load_acquire(volatile jbyte*   p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   244
  static jshort   load_acquire(volatile jshort*  p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   245
  static jint     load_acquire(volatile jint*    p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   246
  static jlong    load_acquire(volatile jlong*   p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   247
  static jubyte   load_acquire(volatile jubyte*  p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   248
  static jushort  load_acquire(volatile jushort* p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   249
  static juint    load_acquire(volatile juint*   p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   250
  static julong   load_acquire(volatile julong*  p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   251
  static jfloat   load_acquire(volatile jfloat*  p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   252
  static jdouble  load_acquire(volatile jdouble* p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   253
489c9b5090e2 Initial load
duke
parents:
diff changeset
   254
  static intptr_t load_ptr_acquire(volatile intptr_t*   p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   255
  static void*    load_ptr_acquire(volatile void*       p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   256
  static void*    load_ptr_acquire(const volatile void* p);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   257
489c9b5090e2 Initial load
duke
parents:
diff changeset
   258
  static void     release_store(volatile jbyte*   p, jbyte   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   259
  static void     release_store(volatile jshort*  p, jshort  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   260
  static void     release_store(volatile jint*    p, jint    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   261
  static void     release_store(volatile jlong*   p, jlong   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   262
  static void     release_store(volatile jubyte*  p, jubyte  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   263
  static void     release_store(volatile jushort* p, jushort v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   264
  static void     release_store(volatile juint*   p, juint   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   265
  static void     release_store(volatile julong*  p, julong  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   266
  static void     release_store(volatile jfloat*  p, jfloat  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   267
  static void     release_store(volatile jdouble* p, jdouble v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   268
489c9b5090e2 Initial load
duke
parents:
diff changeset
   269
  static void     release_store_ptr(volatile intptr_t* p, intptr_t v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   270
  static void     release_store_ptr(volatile void*     p, void*    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   271
489c9b5090e2 Initial load
duke
parents:
diff changeset
   272
  static void     store_fence(jbyte*   p, jbyte   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   273
  static void     store_fence(jshort*  p, jshort  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   274
  static void     store_fence(jint*    p, jint    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   275
  static void     store_fence(jlong*   p, jlong   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   276
  static void     store_fence(jubyte*  p, jubyte  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   277
  static void     store_fence(jushort* p, jushort v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   278
  static void     store_fence(juint*   p, juint   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   279
  static void     store_fence(julong*  p, julong  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   280
  static void     store_fence(jfloat*  p, jfloat  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   281
  static void     store_fence(jdouble* p, jdouble v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   282
489c9b5090e2 Initial load
duke
parents:
diff changeset
   283
  static void     store_ptr_fence(intptr_t* p, intptr_t v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   284
  static void     store_ptr_fence(void**    p, void*    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   285
489c9b5090e2 Initial load
duke
parents:
diff changeset
   286
  static void     release_store_fence(volatile jbyte*   p, jbyte   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   287
  static void     release_store_fence(volatile jshort*  p, jshort  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   288
  static void     release_store_fence(volatile jint*    p, jint    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   289
  static void     release_store_fence(volatile jlong*   p, jlong   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   290
  static void     release_store_fence(volatile jubyte*  p, jubyte  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   291
  static void     release_store_fence(volatile jushort* p, jushort v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   292
  static void     release_store_fence(volatile juint*   p, juint   v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   293
  static void     release_store_fence(volatile julong*  p, julong  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   294
  static void     release_store_fence(volatile jfloat*  p, jfloat  v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   295
  static void     release_store_fence(volatile jdouble* p, jdouble v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   296
489c9b5090e2 Initial load
duke
parents:
diff changeset
   297
  static void     release_store_ptr_fence(volatile intptr_t* p, intptr_t v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   298
  static void     release_store_ptr_fence(volatile void*     p, void*    v);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   299
489c9b5090e2 Initial load
duke
parents:
diff changeset
   300
  // In order to force a memory access, implementations may
489c9b5090e2 Initial load
duke
parents:
diff changeset
   301
  // need a volatile externally visible dummy variable.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   302
  static volatile intptr_t dummy;
2338
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   303
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   304
 private:
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   305
  // This is a helper that invokes the StubRoutines::fence_entry()
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   306
  // routine if it exists, It should only be used by platforms that
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   307
  // don't another way to do the inline eassembly.
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2131
diff changeset
   308
  static void StubRoutines_fence();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   309
};