author | mdoerr |
Tue, 05 Nov 2019 11:53:46 +0100 | |
changeset 58932 | 8623f75be895 |
parent 53244 | 9807daeb47c4 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2014, 2108, Red Hat Inc. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_AARCH64_NATIVEINST_AARCH64_HPP |
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#define CPU_AARCH64_NATIVEINST_AARCH64_HPP |
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#include "asm/assembler.hpp" |
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#include "runtime/icache.hpp" |
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#include "runtime/os.hpp" |
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||
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// We have interfaces for the following instructions: |
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// - NativeInstruction |
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// - - NativeCall |
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// - - NativeMovConstReg |
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// - - NativeMovConstRegPatching |
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// - - NativeMovRegMem |
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// - - NativeMovRegMemPatching |
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// - - NativeJump |
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// - - NativeIllegalOpCode |
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// - - NativeGeneralJump |
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// - - NativeReturn |
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// - - NativeReturnX (return with argument) |
|
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// - - NativePushConst |
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// - - NativeTstRegMem |
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||
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// The base class for different kinds of native instruction abstractions. |
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// Provides the primitive operations to manipulate code relative to this. |
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class NativeCall; |
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class NativeInstruction { |
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friend class Relocation; |
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friend bool is_NativeCallTrampolineStub_at(address); |
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public: |
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enum { |
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instruction_size = 4 |
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}; |
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||
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juint encoding() const { |
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return uint_at(0); |
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} |
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||
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bool is_blr() const { return (encoding() & 0xff9ffc1f) == 0xd61f0000; } // blr(register) or br(register) |
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bool is_adr_aligned() const { return (encoding() & 0xff000000) == 0x10000000; } // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction). |
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inline bool is_nop(); |
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inline bool is_illegal(); |
|
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inline bool is_return(); |
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bool is_jump(); |
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bool is_general_jump(); |
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inline bool is_jump_or_nop(); |
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inline bool is_cond_jump(); |
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bool is_safepoint_poll(); |
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bool is_movz(); |
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bool is_movk(); |
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bool is_sigill_zombie_not_entrant(); |
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protected: |
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address addr_at(int offset) const { return address(this) + offset; } |
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||
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s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } |
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u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } |
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jint int_at(int offset) const { return *(jint*) addr_at(offset); } |
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juint uint_at(int offset) const { return *(juint*) addr_at(offset); } |
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address ptr_at(int offset) const { return *(address*) addr_at(offset); } |
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||
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oop oop_at (int offset) const { return *(oop*) addr_at(offset); } |
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void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; } |
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void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; } |
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void set_uint_at(int offset, jint i) { *(juint*)addr_at(offset) = i; } |
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void set_ptr_at (int offset, address ptr) { *(address*) addr_at(offset) = ptr; } |
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void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; } |
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void wrote(int offset); |
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||
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public: |
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// unit test stuff |
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static void test() {} // override for testing |
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inline friend NativeInstruction* nativeInstruction_at(address address); |
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static bool is_adrp_at(address instr); |
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static bool is_ldr_literal_at(address instr); |
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bool is_ldr_literal() { |
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return is_ldr_literal_at(addr_at(0)); |
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} |
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||
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static bool is_ldrw_to_zr(address instr); |
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static bool is_call_at(address instr) { |
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const uint32_t insn = (*(uint32_t*)instr); |
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return (insn >> 26) == 0b100101; |
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} |
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bool is_call() { |
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return is_call_at(addr_at(0)); |
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} |
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||
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static bool maybe_cpool_ref(address instr) { |
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return is_adrp_at(instr) || is_ldr_literal_at(instr); |
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} |
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bool is_Membar() { |
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unsigned int insn = uint_at(0); |
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return Instruction_aarch64::extract(insn, 31, 12) == 0b11010101000000110011 && |
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Instruction_aarch64::extract(insn, 7, 0) == 0b10111111; |
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} |
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bool is_Imm_LdSt() { |
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unsigned int insn = uint_at(0); |
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return Instruction_aarch64::extract(insn, 29, 27) == 0b111 && |
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Instruction_aarch64::extract(insn, 23, 23) == 0b0 && |
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Instruction_aarch64::extract(insn, 26, 25) == 0b00; |
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} |
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}; |
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inline NativeInstruction* nativeInstruction_at(address address) { |
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return (NativeInstruction*)address; |
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} |
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// The natural type of an AArch64 instruction is uint32_t |
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inline NativeInstruction* nativeInstruction_at(uint32_t *address) { |
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return (NativeInstruction*)address; |
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} |
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class NativePltCall: public NativeInstruction { |
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public: |
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enum Arm_specific_constants { |
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instruction_size = 4, |
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instruction_offset = 0, |
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displacement_offset = 1, |
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return_address_offset = 4 |
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}; |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(return_address_offset); } |
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address displacement_address() const { return addr_at(displacement_offset); } |
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int displacement() const { return (jint) int_at(displacement_offset); } |
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address return_address() const { return addr_at(return_address_offset); } |
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address destination() const; |
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address plt_entry() const; |
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address plt_jump() const; |
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address plt_load_got() const; |
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address plt_resolve_call() const; |
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address plt_c2i_stub() const; |
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void set_stub_to_clean(); |
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void reset_to_plt_resolve_call(); |
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void set_destination_mt_safe(address dest); |
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void verify() const; |
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}; |
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inline NativePltCall* nativePltCall_at(address address) { |
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NativePltCall* call = (NativePltCall*) address; |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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inline NativePltCall* nativePltCall_before(address addr) { |
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address at = addr - NativePltCall::instruction_size; |
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return nativePltCall_at(at); |
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} |
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||
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inline NativeCall* nativeCall_at(address address); |
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// The NativeCall is an abstraction for accessing/manipulating native |
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// call instructions (used to manipulate inline caches, primitive & |
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// DSO calls, etc.). |
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class NativeCall: public NativeInstruction { |
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public: |
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enum Aarch64_specific_constants { |
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instruction_size = 4, |
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instruction_offset = 0, |
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displacement_offset = 0, |
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return_address_offset = 4 |
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}; |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(return_address_offset); } |
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int displacement() const { return (int_at(displacement_offset) << 6) >> 4; } |
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address displacement_address() const { return addr_at(displacement_offset); } |
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address return_address() const { return addr_at(return_address_offset); } |
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address destination() const; |
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void set_destination(address dest) { |
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int offset = dest - instruction_address(); |
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unsigned int insn = 0b100101 << 26; |
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assert((offset & 3) == 0, "should be"); |
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offset >>= 2; |
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offset &= (1 << 26) - 1; // mask off insn part |
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insn |= offset; |
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set_int_at(displacement_offset, insn); |
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} |
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void verify_alignment() { ; } |
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void verify(); |
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void print(); |
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// Creation |
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inline friend NativeCall* nativeCall_at(address address); |
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inline friend NativeCall* nativeCall_before(address return_address); |
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static bool is_call_before(address return_address) { |
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return is_call_at(return_address - NativeCall::return_address_offset); |
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} |
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||
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#if INCLUDE_AOT |
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// Return true iff a call from instr to target is out of range. |
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// Used for calls from JIT- to AOT-compiled code. |
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static bool is_far_call(address instr, address target) { |
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// On AArch64 we use trampolines which can reach anywhere in the |
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// address space, so calls are never out of range. |
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return false; |
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} |
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#endif |
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// MT-safe patching of a call instruction. |
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static void insert(address code_pos, address entry); |
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static void replace_mt_safe(address instr_addr, address code_buffer); |
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// Similar to replace_mt_safe, but just changes the destination. The |
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// important thing is that free-running threads are able to execute |
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// this call instruction at all times. If the call is an immediate BL |
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// instruction we can simply rely on atomicity of 32-bit writes to |
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// make sure other threads will see no intermediate states. |
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// We cannot rely on locks here, since the free-running threads must run at |
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// full speed. |
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// |
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// Used in the runtime linkage of calls; see class CompiledIC. |
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// (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.) |
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// The parameter assert_lock disables the assertion during code generation. |
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void set_destination_mt_safe(address dest, bool assert_lock = true); |
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address get_trampoline(); |
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address trampoline_jump(CodeBuffer &cbuf, address dest); |
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}; |
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inline NativeCall* nativeCall_at(address address) { |
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NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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inline NativeCall* nativeCall_before(address return_address) { |
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NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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// An interface for accessing/manipulating native mov reg, imm instructions. |
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// (used to manipulate inlined 64-bit data calls, etc.) |
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class NativeMovConstReg: public NativeInstruction { |
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public: |
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enum Aarch64_specific_constants { |
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instruction_size = 3 * 4, // movz, movk, movk. See movptr(). |
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instruction_offset = 0, |
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displacement_offset = 0, |
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}; |
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297 |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { |
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if (nativeInstruction_at(instruction_address())->is_movz()) |
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// Assume movz, movk, movk |
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return addr_at(instruction_size); |
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else if (is_adrp_at(instruction_address())) |
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return addr_at(2*4); |
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else if (is_ldr_literal_at(instruction_address())) |
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return(addr_at(4)); |
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assert(false, "Unknown instruction in NativeMovConstReg"); |
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return NULL; |
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} |
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310 |
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intptr_t data() const; |
|
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void set_data(intptr_t x); |
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||
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void flush() { |
|
315 |
if (! maybe_cpool_ref(instruction_address())) { |
|
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ICache::invalidate_range(instruction_address(), instruction_size); |
|
317 |
} |
|
318 |
} |
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319 |
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320 |
void verify(); |
|
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void print(); |
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322 |
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323 |
// unit test stuff |
|
324 |
static void test() {} |
|
325 |
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326 |
// Creation |
|
327 |
inline friend NativeMovConstReg* nativeMovConstReg_at(address address); |
|
328 |
inline friend NativeMovConstReg* nativeMovConstReg_before(address address); |
|
329 |
}; |
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330 |
||
331 |
inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
|
332 |
NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); |
|
333 |
#ifdef ASSERT |
|
334 |
test->verify(); |
|
335 |
#endif |
|
336 |
return test; |
|
337 |
} |
|
338 |
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339 |
inline NativeMovConstReg* nativeMovConstReg_before(address address) { |
|
340 |
NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); |
|
341 |
#ifdef ASSERT |
|
342 |
test->verify(); |
|
343 |
#endif |
|
344 |
return test; |
|
345 |
} |
|
346 |
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347 |
class NativeMovConstRegPatching: public NativeMovConstReg { |
|
348 |
private: |
|
349 |
friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
|
350 |
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); |
|
351 |
#ifdef ASSERT |
|
352 |
test->verify(); |
|
353 |
#endif |
|
354 |
return test; |
|
355 |
} |
|
356 |
}; |
|
357 |
||
358 |
// An interface for accessing/manipulating native moves of the form: |
|
359 |
// mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) |
|
360 |
// mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg |
|
361 |
// mov[s/z]x[w/b/q] [reg + offset], reg |
|
362 |
// fld_s [reg+offset] |
|
363 |
// fld_d [reg+offset] |
|
364 |
// fstp_s [reg + offset] |
|
365 |
// fstp_d [reg + offset] |
|
366 |
// mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) |
|
367 |
// |
|
368 |
// Warning: These routines must be able to handle any instruction sequences |
|
369 |
// that are generated as a result of the load/store byte,word,long |
|
370 |
// macros. For example: The load_unsigned_byte instruction generates |
|
371 |
// an xor reg,reg inst prior to generating the movb instruction. This |
|
372 |
// class must skip the xor instruction. |
|
373 |
||
374 |
class NativeMovRegMem: public NativeInstruction { |
|
375 |
enum AArch64_specific_constants { |
|
376 |
instruction_size = 4, |
|
377 |
instruction_offset = 0, |
|
378 |
data_offset = 0, |
|
379 |
next_instruction_offset = 4 |
|
380 |
}; |
|
381 |
||
382 |
public: |
|
383 |
// helper |
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384 |
int instruction_start() const { return instruction_offset; } |
29183 | 385 |
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386 |
address instruction_address() const { return addr_at(instruction_offset); } |
29183 | 387 |
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diff
changeset
|
388 |
int num_bytes_to_end_of_patch() const { return instruction_offset + instruction_size; } |
29183 | 389 |
|
390 |
int offset() const; |
|
391 |
||
392 |
void set_offset(int x); |
|
393 |
||
394 |
void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } |
|
395 |
||
396 |
void verify(); |
|
397 |
void print (); |
|
398 |
||
399 |
// unit test stuff |
|
400 |
static void test() {} |
|
401 |
||
402 |
private: |
|
403 |
inline friend NativeMovRegMem* nativeMovRegMem_at (address address); |
|
404 |
}; |
|
405 |
||
406 |
inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
|
407 |
NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); |
|
408 |
#ifdef ASSERT |
|
409 |
test->verify(); |
|
410 |
#endif |
|
411 |
return test; |
|
412 |
} |
|
413 |
||
414 |
class NativeMovRegMemPatching: public NativeMovRegMem { |
|
415 |
private: |
|
416 |
friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0; } |
|
417 |
}; |
|
418 |
||
419 |
// An interface for accessing/manipulating native leal instruction of form: |
|
420 |
// leal reg, [reg + offset] |
|
421 |
||
36060 | 422 |
class NativeLoadAddress: public NativeInstruction { |
423 |
enum AArch64_specific_constants { |
|
424 |
instruction_size = 4, |
|
425 |
instruction_offset = 0, |
|
426 |
data_offset = 0, |
|
427 |
next_instruction_offset = 4 |
|
428 |
}; |
|
429 |
||
29183 | 430 |
public: |
431 |
void verify(); |
|
432 |
void print (); |
|
433 |
||
434 |
// unit test stuff |
|
435 |
static void test() {} |
|
436 |
}; |
|
437 |
||
50104 | 438 |
// adrp x16, #page |
439 |
// add x16, x16, #offset |
|
440 |
// ldr x16, [x16] |
|
441 |
class NativeLoadGot: public NativeInstruction { |
|
442 |
public: |
|
443 |
enum AArch64_specific_constants { |
|
444 |
instruction_length = 4 * NativeInstruction::instruction_size, |
|
445 |
offset_offset = 0, |
|
446 |
}; |
|
447 |
||
448 |
address instruction_address() const { return addr_at(0); } |
|
449 |
address return_address() const { return addr_at(instruction_length); } |
|
450 |
address got_address() const; |
|
451 |
address next_instruction_address() const { return return_address(); } |
|
452 |
intptr_t data() const; |
|
453 |
void set_data(intptr_t data) { |
|
454 |
intptr_t *addr = (intptr_t *) got_address(); |
|
455 |
*addr = data; |
|
456 |
} |
|
457 |
||
458 |
void verify() const; |
|
459 |
private: |
|
460 |
void report_and_fail() const; |
|
461 |
}; |
|
462 |
||
463 |
inline NativeLoadGot* nativeLoadGot_at(address addr) { |
|
464 |
NativeLoadGot* load = (NativeLoadGot*) addr; |
|
465 |
#ifdef ASSERT |
|
466 |
load->verify(); |
|
467 |
#endif |
|
468 |
return load; |
|
469 |
} |
|
470 |
||
29183 | 471 |
class NativeJump: public NativeInstruction { |
472 |
public: |
|
473 |
enum AArch64_specific_constants { |
|
474 |
instruction_size = 4, |
|
475 |
instruction_offset = 0, |
|
476 |
data_offset = 0, |
|
477 |
next_instruction_offset = 4 |
|
478 |
}; |
|
479 |
||
480 |
address instruction_address() const { return addr_at(instruction_offset); } |
|
481 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
482 |
address jump_destination() const; |
|
483 |
void set_jump_destination(address dest); |
|
484 |
||
485 |
// Creation |
|
486 |
inline friend NativeJump* nativeJump_at(address address); |
|
487 |
||
488 |
void verify(); |
|
489 |
||
490 |
// Unit testing stuff |
|
491 |
static void test() {} |
|
492 |
||
493 |
// Insertion of native jump instruction |
|
494 |
static void insert(address code_pos, address entry); |
|
495 |
// MT-safe insertion of native jump at verified method entry |
|
496 |
static void check_verified_entry_alignment(address entry, address verified_entry); |
|
497 |
static void patch_verified_entry(address entry, address verified_entry, address dest); |
|
498 |
}; |
|
499 |
||
500 |
inline NativeJump* nativeJump_at(address address) { |
|
501 |
NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); |
|
502 |
#ifdef ASSERT |
|
503 |
jump->verify(); |
|
504 |
#endif |
|
505 |
return jump; |
|
506 |
} |
|
507 |
||
508 |
class NativeGeneralJump: public NativeJump { |
|
509 |
public: |
|
510 |
enum AArch64_specific_constants { |
|
511 |
instruction_size = 4 * 4, |
|
512 |
instruction_offset = 0, |
|
513 |
data_offset = 0, |
|
514 |
next_instruction_offset = 4 * 4 |
|
515 |
}; |
|
36060 | 516 |
|
517 |
address jump_destination() const; |
|
518 |
void set_jump_destination(address dest); |
|
519 |
||
29183 | 520 |
static void insert_unconditional(address code_pos, address entry); |
521 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
522 |
static void verify(); |
|
523 |
}; |
|
524 |
||
525 |
inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
|
526 |
NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
|
527 |
debug_only(jump->verify();) |
|
528 |
return jump; |
|
529 |
} |
|
530 |
||
50104 | 531 |
class NativeGotJump: public NativeInstruction { |
532 |
public: |
|
533 |
enum AArch64_specific_constants { |
|
534 |
instruction_size = 4 * NativeInstruction::instruction_size, |
|
535 |
}; |
|
536 |
||
537 |
void verify() const; |
|
538 |
address instruction_address() const { return addr_at(0); } |
|
539 |
address destination() const; |
|
540 |
address return_address() const { return addr_at(instruction_size); } |
|
541 |
address got_address() const; |
|
542 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
543 |
bool is_GotJump() const; |
|
544 |
||
545 |
void set_jump_destination(address dest) { |
|
546 |
address* got = (address *)got_address(); |
|
547 |
*got = dest; |
|
548 |
} |
|
549 |
}; |
|
550 |
||
551 |
inline NativeGotJump* nativeGotJump_at(address addr) { |
|
552 |
NativeGotJump* jump = (NativeGotJump*)(addr); |
|
553 |
return jump; |
|
554 |
} |
|
555 |
||
29183 | 556 |
class NativePopReg : public NativeInstruction { |
557 |
public: |
|
558 |
// Insert a pop instruction |
|
559 |
static void insert(address code_pos, Register reg); |
|
560 |
}; |
|
561 |
||
562 |
||
563 |
class NativeIllegalInstruction: public NativeInstruction { |
|
564 |
public: |
|
565 |
// Insert illegal opcode as specific address |
|
566 |
static void insert(address code_pos); |
|
567 |
}; |
|
568 |
||
569 |
// return instruction that does not pop values of the stack |
|
570 |
class NativeReturn: public NativeInstruction { |
|
571 |
public: |
|
572 |
}; |
|
573 |
||
574 |
// return instruction that does pop values of the stack |
|
575 |
class NativeReturnX: public NativeInstruction { |
|
576 |
public: |
|
577 |
}; |
|
578 |
||
579 |
// Simple test vs memory |
|
580 |
class NativeTstRegMem: public NativeInstruction { |
|
581 |
public: |
|
582 |
}; |
|
583 |
||
584 |
inline bool NativeInstruction::is_nop() { |
|
585 |
uint32_t insn = *(uint32_t*)addr_at(0); |
|
586 |
return insn == 0xd503201f; |
|
587 |
} |
|
588 |
||
589 |
inline bool NativeInstruction::is_jump() { |
|
590 |
uint32_t insn = *(uint32_t*)addr_at(0); |
|
591 |
||
592 |
if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { |
|
593 |
// Unconditional branch (immediate) |
|
594 |
return true; |
|
595 |
} else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { |
|
596 |
// Conditional branch (immediate) |
|
597 |
return true; |
|
598 |
} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { |
|
599 |
// Compare & branch (immediate) |
|
600 |
return true; |
|
601 |
} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { |
|
602 |
// Test & branch (immediate) |
|
603 |
return true; |
|
604 |
} else |
|
605 |
return false; |
|
606 |
} |
|
607 |
||
608 |
inline bool NativeInstruction::is_jump_or_nop() { |
|
609 |
return is_nop() || is_jump(); |
|
610 |
} |
|
611 |
||
612 |
// Call trampoline stubs. |
|
613 |
class NativeCallTrampolineStub : public NativeInstruction { |
|
614 |
public: |
|
615 |
||
616 |
enum AArch64_specific_constants { |
|
617 |
instruction_size = 4 * 4, |
|
618 |
instruction_offset = 0, |
|
619 |
data_offset = 2 * 4, |
|
620 |
next_instruction_offset = 4 * 4 |
|
621 |
}; |
|
622 |
||
623 |
address destination(nmethod *nm = NULL) const; |
|
624 |
void set_destination(address new_destination); |
|
625 |
ptrdiff_t destination_offset() const; |
|
626 |
}; |
|
627 |
||
628 |
inline bool is_NativeCallTrampolineStub_at(address addr) { |
|
629 |
// Ensure that the stub is exactly |
|
630 |
// ldr xscratch1, L |
|
631 |
// br xscratch1 |
|
632 |
// L: |
|
633 |
uint32_t *i = (uint32_t *)addr; |
|
634 |
return i[0] == 0x58000048 && i[1] == 0xd61f0100; |
|
635 |
} |
|
636 |
||
637 |
inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) { |
|
638 |
assert(is_NativeCallTrampolineStub_at(addr), "no call trampoline found"); |
|
639 |
return (NativeCallTrampolineStub*)addr; |
|
640 |
} |
|
641 |
||
33193 | 642 |
class NativeMembar : public NativeInstruction { |
643 |
public: |
|
644 |
unsigned int get_kind() { return Instruction_aarch64::extract(uint_at(0), 11, 8); } |
|
645 |
void set_kind(int order_kind) { Instruction_aarch64::patch(addr_at(0), 11, 8, order_kind); } |
|
646 |
}; |
|
647 |
||
648 |
inline NativeMembar *NativeMembar_at(address addr) { |
|
649 |
assert(nativeInstruction_at(addr)->is_Membar(), "no membar found"); |
|
650 |
return (NativeMembar*)addr; |
|
651 |
} |
|
652 |
||
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
653 |
class NativeLdSt : public NativeInstruction { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
654 |
private: |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
655 |
int32_t size() { return Instruction_aarch64::extract(uint_at(0), 31, 30); } |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
656 |
// Check whether instruction is with unscaled offset. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
657 |
bool is_ldst_ur() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
658 |
return (Instruction_aarch64::extract(uint_at(0), 29, 21) == 0b111000010 || |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
659 |
Instruction_aarch64::extract(uint_at(0), 29, 21) == 0b111000000) && |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
660 |
Instruction_aarch64::extract(uint_at(0), 11, 10) == 0b00; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
661 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
662 |
bool is_ldst_unsigned_offset() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
663 |
return Instruction_aarch64::extract(uint_at(0), 29, 22) == 0b11100101 || |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
664 |
Instruction_aarch64::extract(uint_at(0), 29, 22) == 0b11100100; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
665 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
666 |
public: |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
667 |
Register target() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
668 |
uint32_t r = Instruction_aarch64::extract(uint_at(0), 4, 0); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
669 |
return r == 0x1f ? zr : as_Register(r); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
670 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
671 |
Register base() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
672 |
uint32_t b = Instruction_aarch64::extract(uint_at(0), 9, 5); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
673 |
return b == 0x1f ? sp : as_Register(b); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
674 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
675 |
int64_t offset() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
676 |
if (is_ldst_ur()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
677 |
return Instruction_aarch64::sextract(uint_at(0), 20, 12); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
678 |
} else if (is_ldst_unsigned_offset()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
679 |
return Instruction_aarch64::extract(uint_at(0), 21, 10) << size(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
680 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
681 |
// others like: pre-index or post-index. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
682 |
ShouldNotReachHere(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
683 |
return 0; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
684 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
685 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
686 |
size_t size_in_bytes() { return 1 << size(); } |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
687 |
bool is_not_pre_post_index() { return (is_ldst_ur() || is_ldst_unsigned_offset()); } |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
688 |
bool is_load() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
689 |
assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 || |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
690 |
Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str"); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
691 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
692 |
return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
693 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
694 |
bool is_store() { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
695 |
assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 || |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
696 |
Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str"); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
697 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
48487
diff
changeset
|
698 |
return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00; |
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} |
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}; |
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|
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inline NativeLdSt *NativeLdSt_at(address addr) { |
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assert(nativeInstruction_at(addr)->is_Imm_LdSt(), "no immediate load/store found"); |
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return (NativeLdSt*)addr; |
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} |
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#endif // CPU_AARCH64_NATIVEINST_AARCH64_HPP |