hotspot/src/cpu/aarch64/vm/nativeInst_aarch64.cpp
author adinn
Mon, 02 Mar 2015 10:31:52 -0800
changeset 29195 7d6208ea1775
parent 29183 0cc8699f7372
child 36060 de5c192c2eac
permissions -rw-r--r--
8074119: [AARCH64] stage repo misses fixes from several Hotspot changes Summary: add shared code changes from 8059606, 8069230, 8068976, 8068977, 8072911 and 8071805 Reviewed-by: aph, kvn
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/*
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 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "memory/resourceArea.hpp"
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#include "nativeInst_aarch64.hpp"
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#include "oops/oop.inline.hpp"
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#include "runtime/handles.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "utilities/ostream.hpp"
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#ifdef COMPILER1
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#include "c1/c1_Runtime1.hpp"
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#endif
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void NativeCall::verify() { ; }
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address NativeCall::destination() const {
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  address addr = (address)this;
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  address destination = instruction_address() + displacement();
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  // Do we use a trampoline stub for this call?
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  CodeBlob* cb = CodeCache::find_blob_unsafe(addr);   // Else we get assertion if nmethod is zombie.
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  assert(cb && cb->is_nmethod(), "sanity");
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  nmethod *nm = (nmethod *)cb;
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  if (nm->stub_contains(destination) && is_NativeCallTrampolineStub_at(destination)) {
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    // Yes we do, so get the destination from the trampoline stub.
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    const address trampoline_stub_addr = destination;
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    destination = nativeCallTrampolineStub_at(trampoline_stub_addr)->destination();
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  }
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  return destination;
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}
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// Similar to replace_mt_safe, but just changes the destination. The
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// important thing is that free-running threads are able to execute this
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// call instruction at all times.
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//
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// Used in the runtime linkage of calls; see class CompiledIC.
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//
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// Add parameter assert_lock to switch off assertion
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// during code generation, where no patching lock is needed.
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void NativeCall::set_destination_mt_safe(address dest, bool assert_lock) {
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  assert(!assert_lock ||
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         (Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()),
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         "concurrent code patching");
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  ResourceMark rm;
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  int code_size = NativeInstruction::instruction_size;
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  address addr_call = addr_at(0);
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  assert(NativeCall::is_call_at(addr_call), "unexpected code at call site");
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  // Patch the constant in the call's trampoline stub.
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  address trampoline_stub_addr = get_trampoline();
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  if (trampoline_stub_addr != NULL) {
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    assert (! is_NativeCallTrampolineStub_at(dest), "chained trampolines");
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    nativeCallTrampolineStub_at(trampoline_stub_addr)->set_destination(dest);
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  }
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  // Patch the call.
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  if (Assembler::reachable_from_branch_at(addr_call, dest)) {
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    set_destination(dest);
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  } else {
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    assert (trampoline_stub_addr != NULL, "we need a trampoline");
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    set_destination(trampoline_stub_addr);
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  }
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  ICache::invalidate_range(addr_call, instruction_size);
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}
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address NativeCall::get_trampoline() {
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  address call_addr = addr_at(0);
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  CodeBlob *code = CodeCache::find_blob(call_addr);
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  assert(code != NULL, "Could not find the containing code blob");
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  address bl_destination
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    = MacroAssembler::pd_call_destination(call_addr);
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  if (code->content_contains(bl_destination) &&
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      is_NativeCallTrampolineStub_at(bl_destination))
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    return bl_destination;
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  // If the codeBlob is not a nmethod, this is because we get here from the
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  // CodeBlob constructor, which is called within the nmethod constructor.
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  return trampoline_stub_Relocation::get_trampoline_for(call_addr, (nmethod*)code);
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}
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// Inserts a native call instruction at a given pc
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void NativeCall::insert(address code_pos, address entry) { Unimplemented(); }
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//-------------------------------------------------------------------
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void NativeMovConstReg::verify() {
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  // make sure code pattern is actually mov reg64, imm64 instructions
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}
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intptr_t NativeMovConstReg::data() const {
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  // das(uint64_t(instruction_address()),2);
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  address addr = MacroAssembler::target_addr_for_insn(instruction_address());
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  if (maybe_cpool_ref(instruction_address())) {
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    return *(intptr_t*)addr;
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  } else {
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    return (intptr_t)addr;
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  }
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}
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void NativeMovConstReg::set_data(intptr_t x) {
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  if (maybe_cpool_ref(instruction_address())) {
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    address addr = MacroAssembler::target_addr_for_insn(instruction_address());
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    *(intptr_t*)addr = x;
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  } else {
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    MacroAssembler::pd_patch_instruction(instruction_address(), (address)x);
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    ICache::invalidate_range(instruction_address(), instruction_size);
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  }
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};
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void NativeMovConstReg::print() {
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  tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
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                p2i(instruction_address()), data());
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}
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//-------------------------------------------------------------------
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address NativeMovRegMem::instruction_address() const      { return addr_at(instruction_offset); }
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int NativeMovRegMem::offset() const  {
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  address pc = instruction_address();
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  unsigned insn = *(unsigned*)pc;
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  if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
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    address addr = MacroAssembler::target_addr_for_insn(pc);
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    return *addr;
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  } else {
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    return (int)(intptr_t)MacroAssembler::target_addr_for_insn(instruction_address());
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  }
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}
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void NativeMovRegMem::set_offset(int x) {
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  address pc = instruction_address();
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  unsigned insn = *(unsigned*)pc;
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  if (maybe_cpool_ref(pc)) {
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    address addr = MacroAssembler::target_addr_for_insn(pc);
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    *(long*)addr = x;
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  } else {
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    MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x));
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    ICache::invalidate_range(instruction_address(), instruction_size);
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  }
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}
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void NativeMovRegMem::verify() {
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#ifdef ASSERT
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  address dest = MacroAssembler::target_addr_for_insn(instruction_address());
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#endif
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}
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//--------------------------------------------------------------------------------
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void NativeJump::verify() { ; }
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void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
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}
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address NativeJump::jump_destination() const          {
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  address dest = MacroAssembler::target_addr_for_insn(instruction_address());
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  // We use jump to self as the unresolved address which the inline
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  // cache code (and relocs) know about
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  // return -1 if jump to self
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  dest = (dest == (address) this) ? (address) -1 : dest;
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  return dest;
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}
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void NativeJump::set_jump_destination(address dest) {
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  // We use jump to self as the unresolved address which the inline
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  // cache code (and relocs) know about
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  if (dest == (address) -1)
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    dest = instruction_address();
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  MacroAssembler::pd_patch_instruction(instruction_address(), dest);
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  ICache::invalidate_range(instruction_address(), instruction_size);
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};
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//-------------------------------------------------------------------
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bool NativeInstruction::is_safepoint_poll() {
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  // a safepoint_poll is implemented in two steps as either
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  //
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  // adrp(reg, polling_page);
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  // ldr(zr, [reg, #offset]);
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  //
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  // or
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  //
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  // mov(reg, polling_page);
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  // ldr(zr, [reg, #offset]);
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  //
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  // however, we cannot rely on the polling page address load always
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  // directly preceding the read from the page. C1 does that but C2
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  // has to do the load and read as two independent instruction
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  // generation steps. that's because with a single macro sequence the
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  // generic C2 code can only add the oop map before the mov/adrp and
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  // the trap handler expects an oop map to be associated with the
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  // load. with the load scheuled as a prior step the oop map goes
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  // where it is needed.
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  //
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  // so all we can do here is check that marked instruction is a load
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  // word to zr
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  return is_ldrw_to_zr(address(this));
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}
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bool NativeInstruction::is_adrp_at(address instr) {
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  unsigned insn = *(unsigned*)instr;
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  return (Instruction_aarch64::extract(insn, 31, 24) & 0b10011111) == 0b10010000;
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}
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bool NativeInstruction::is_ldr_literal_at(address instr) {
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  unsigned insn = *(unsigned*)instr;
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  return (Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000;
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}
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bool NativeInstruction::is_ldrw_to_zr(address instr) {
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  unsigned insn = *(unsigned*)instr;
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  return (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
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          Instruction_aarch64::extract(insn, 4, 0) == 0b11111);
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}
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bool NativeInstruction::is_movz() {
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  return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b10100101;
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}
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bool NativeInstruction::is_movk() {
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  return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b11100101;
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}
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bool NativeInstruction::is_sigill_zombie_not_entrant() {
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  return uint_at(0) == 0xd4bbd5a1; // dcps1 #0xdead
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}
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void NativeIllegalInstruction::insert(address code_pos) {
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  *(juint*)code_pos = 0xd4bbd5a1; // dcps1 #0xdead
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}
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//-------------------------------------------------------------------
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// MT-safe inserting of a jump over a jump or a nop (used by
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// nmethod::make_not_entrant_or_zombie)
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void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
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  assert(dest == SharedRuntime::get_handle_wrong_method_stub(), "expected fixed destination of patch");
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  assert(nativeInstruction_at(verified_entry)->is_jump_or_nop()
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         || nativeInstruction_at(verified_entry)->is_sigill_zombie_not_entrant(),
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         "Aarch64 cannot replace non-jump with jump");
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  // Patch this nmethod atomically.
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  if (Assembler::reachable_from_branch_at(verified_entry, dest)) {
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    ptrdiff_t disp = dest - verified_entry;
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    guarantee(disp < 1 << 27 && disp > - (1 << 27), "branch overflow");
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    unsigned int insn = (0b000101 << 26) | ((disp >> 2) & 0x3ffffff);
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    *(unsigned int*)verified_entry = insn;
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  } else {
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    // We use an illegal instruction for marking a method as
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    // not_entrant or zombie.
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    NativeIllegalInstruction::insert(verified_entry);
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  }
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  ICache::invalidate_range(verified_entry, instruction_size);
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}
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void NativeGeneralJump::verify() {  }
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void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
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  NativeGeneralJump* n_jump = (NativeGeneralJump*)code_pos;
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  CodeBuffer cb(code_pos, instruction_size);
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  MacroAssembler a(&cb);
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  a.mov(rscratch1, entry);
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  a.br(rscratch1);
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  ICache::invalidate_range(code_pos, instruction_size);
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}
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// MT-safe patching of a long jump instruction.
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void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
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  ShouldNotCallThis();
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}
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address NativeCallTrampolineStub::destination(nmethod *nm) const {
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  return ptr_at(data_offset);
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}
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void NativeCallTrampolineStub::set_destination(address new_destination) {
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  set_ptr_at(data_offset, new_destination);
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  OrderAccess::release();
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}