/*

 * Copyright 1999-2009 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

#include "incls/_precompiled.incl"

#include "incls/_c1_Runtime1_x86.cpp.incl"

// Implementation of StubAssembler

int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, int args_size) {

  // setup registers

  const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)

  assert(!(oop_result1->is_valid() || oop_result2->is_valid()) || oop_result1 != oop_result2, "registers must be different");

  assert(oop_result1 != thread && oop_result2 != thread, "registers must be different");

  assert(args_size >= 0, "illegal args_size");

#ifdef _LP64

  mov(c_rarg0, thread);

  set_num_rt_args(0); // Nothing on stack

#else

  set_num_rt_args(1 + args_size);

  // push java thread (becomes first argument of C function)

  get_thread(thread);

  push(thread);

#endif // _LP64

  set_last_Java_frame(thread, noreg, rbp, NULL);

  // do the call

  call(RuntimeAddress(entry));

  int call_offset = offset();

  // verify callee-saved register

#ifdef ASSERT

  guarantee(thread != rax, "change this code");

  push(rax);

  { Label L;

    get_thread(rax);

    cmpptr(thread, rax);

    jcc(Assembler::equal, L);

    int3();

    stop("StubAssembler::call_RT: rdi not callee saved?");

    bind(L);

  }

  pop(rax);

#endif

  reset_last_Java_frame(thread, true, false);

  // discard thread and arguments

  NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));

  // check for pending exceptions

  { Label L;

    cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);

    jcc(Assembler::equal, L);

    // exception pending => remove activation and forward to exception handler

    movptr(rax, Address(thread, Thread::pending_exception_offset()));

    // make sure that the vm_results are cleared

    if (oop_result1->is_valid()) {

      movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);

    }

    if (oop_result2->is_valid()) {

      movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);

    }

    if (frame_size() == no_frame_size) {

      leave();

      jump(RuntimeAddress(StubRoutines::forward_exception_entry()));

    } else if (_stub_id == Runtime1::forward_exception_id) {

      should_not_reach_here();

    } else {

      jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));

    }

    bind(L);

  }

  // get oop results if there are any and reset the values in the thread

  if (oop_result1->is_valid()) {

    movptr(oop_result1, Address(thread, JavaThread::vm_result_offset()));

    movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);

    verify_oop(oop_result1);

  }

  if (oop_result2->is_valid()) {

    movptr(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));

    movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);

    verify_oop(oop_result2);

  }

  return call_offset;

}

int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {

#ifdef _LP64

  mov(c_rarg1, arg1);

#else

  push(arg1);

#endif // _LP64

  return call_RT(oop_result1, oop_result2, entry, 1);

}

int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {

#ifdef _LP64

  if (c_rarg1 == arg2) {

    if (c_rarg2 == arg1) {

      xchgq(arg1, arg2);

    } else {

      mov(c_rarg2, arg2);

      mov(c_rarg1, arg1);

    }

  } else {

    mov(c_rarg1, arg1);

    mov(c_rarg2, arg2);

  }

#else

  push(arg2);

  push(arg1);

#endif // _LP64

  return call_RT(oop_result1, oop_result2, entry, 2);

}

int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {

#ifdef _LP64

  // if there is any conflict use the stack

  if (arg1 == c_rarg2 || arg1 == c_rarg3 ||

      arg2 == c_rarg1 || arg1 == c_rarg3 ||

      arg3 == c_rarg1 || arg1 == c_rarg2) {

    push(arg3);

    push(arg2);

    push(arg1);

    pop(c_rarg1);

    pop(c_rarg2);

    pop(c_rarg3);

  } else {

    mov(c_rarg1, arg1);

    mov(c_rarg2, arg2);

    mov(c_rarg3, arg3);

  }

#else

  push(arg3);

  push(arg2);

  push(arg1);

#endif // _LP64

  return call_RT(oop_result1, oop_result2, entry, 3);

}

// Implementation of StubFrame

class StubFrame: public StackObj {

 private:

  StubAssembler* _sasm;

 public:

  StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);

  void load_argument(int offset_in_words, Register reg);

  ~StubFrame();

};

#define __ _sasm->

StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {

  _sasm = sasm;

  __ set_info(name, must_gc_arguments);

  __ enter();

}

// load parameters that were stored with LIR_Assembler::store_parameter

// Note: offsets for store_parameter and load_argument must match

void StubFrame::load_argument(int offset_in_words, Register reg) {

  // rbp, + 0: link

  //     + 1: return address

  //     + 2: argument with offset 0

  //     + 3: argument with offset 1

  //     + 4: ...

  __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));

}

StubFrame::~StubFrame() {

  __ leave();

  __ ret(0);

}

#undef __

// Implementation of Runtime1

#define __ sasm->

const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;

const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;

// Stack layout for saving/restoring  all the registers needed during a runtime

// call (this includes deoptimization)

// Note: note that users of this frame may well have arguments to some runtime

// while these values are on the stack. These positions neglect those arguments

// but the code in save_live_registers will take the argument count into

// account.

//

#ifdef _LP64

  #define SLOT2(x) x,

  #define SLOT_PER_WORD 2

#else

  #define SLOT2(x)

  #define SLOT_PER_WORD 1

#endif // _LP64

enum reg_save_layout {

  // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that

  // happen and will assert if the stack size we create is misaligned

#ifdef _LP64

  align_dummy_0, align_dummy_1,

#endif // _LP64

  dummy1, SLOT2(dummy1H)                                                                    // 0, 4

  dummy2, SLOT2(dummy2H)                                                                    // 8, 12

  // Two temps to be used as needed by users of save/restore callee registers

  temp_2_off, SLOT2(temp_2H_off)                                                            // 16, 20

  temp_1_off, SLOT2(temp_1H_off)                                                            // 24, 28

  xmm_regs_as_doubles_off,                                                                  // 32

  float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots,  // 160

  fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots,          // 224

  // fpu_state_end_off is exclusive

  fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD),                // 352

  marker = fpu_state_end_off, SLOT2(markerH)                                                // 352, 356

  extra_space_offset,                                                                       // 360

#ifdef _LP64

  r15_off = extra_space_offset, r15H_off,                                                   // 360, 364

  r14_off, r14H_off,                                                                        // 368, 372

  r13_off, r13H_off,                                                                        // 376, 380

  r12_off, r12H_off,                                                                        // 384, 388

  r11_off, r11H_off,                                                                        // 392, 396

  r10_off, r10H_off,                                                                        // 400, 404

  r9_off, r9H_off,                                                                          // 408, 412

  r8_off, r8H_off,                                                                          // 416, 420

  rdi_off, rdiH_off,                                                                        // 424, 428

#else

  rdi_off = extra_space_offset,

#endif // _LP64

  rsi_off, SLOT2(rsiH_off)                                                                  // 432, 436

  rbp_off, SLOT2(rbpH_off)                                                                  // 440, 444

  rsp_off, SLOT2(rspH_off)                                                                  // 448, 452

  rbx_off, SLOT2(rbxH_off)                                                                  // 456, 460

  rdx_off, SLOT2(rdxH_off)                                                                  // 464, 468

  rcx_off, SLOT2(rcxH_off)                                                                  // 472, 476

  rax_off, SLOT2(raxH_off)                                                                  // 480, 484

  saved_rbp_off, SLOT2(saved_rbpH_off)                                                      // 488, 492

  return_off, SLOT2(returnH_off)                                                            // 496, 500

  reg_save_frame_size,  // As noted: neglects any parameters to runtime                     // 504

#ifdef _WIN64

  c_rarg0_off = rcx_off,

#else

  c_rarg0_off = rdi_off,

#endif // WIN64

  // equates

  // illegal instruction handler

  continue_dest_off = temp_1_off,

  // deoptimization equates

  fp0_off = float_regs_as_doubles_off, // slot for java float/double return value

  xmm0_off = xmm_regs_as_doubles_off,  // slot for java float/double return value

  deopt_type = temp_2_off,             // slot for type of deopt in progress

  ret_type = temp_1_off                // slot for return type

};

// Save off registers which might be killed by calls into the runtime.

// Tries to smart of about FP registers.  In particular we separate

// saving and describing the FPU registers for deoptimization since we

// have to save the FPU registers twice if we describe them and on P4

// saving FPU registers which don't contain anything appears

// expensive.  The deopt blob is the only thing which needs to

// describe FPU registers.  In all other cases it should be sufficient

// to simply save their current value.

static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,

                                bool save_fpu_registers = true) {

  // In 64bit all the args are in regs so there are no additional stack slots

  LP64_ONLY(num_rt_args = 0);

  LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)

  int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread

  sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );

  // record saved value locations in an OopMap

  // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread

  OopMap* map = new OopMap(frame_size_in_slots, 0);

  map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());

#ifdef _LP64

  map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args),  r8->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args),  r9->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());

  // This is stupid but needed.

  map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args),  r8->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args),  r9->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());

  map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());

#endif // _LP64

  if (save_fpu_registers) {

    if (UseSSE < 2) {

      int fpu_off = float_regs_as_doubles_off;

      for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {

        VMReg fpu_name_0 = FrameMap::fpu_regname(n);

        map->set_callee_saved(VMRegImpl::stack2reg(fpu_off +     num_rt_args), fpu_name_0);

        // %%% This is really a waste but we'll keep things as they were for now

        if (true) {

          map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());

        }

        fpu_off += 2;

      }

      assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");

    }

    if (UseSSE >= 2) {

      int xmm_off = xmm_regs_as_doubles_off;

      for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {

        VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();

        map->set_callee_saved(VMRegImpl::stack2reg(xmm_off +     num_rt_args), xmm_name_0);

        // %%% This is really a waste but we'll keep things as they were for now

        if (true) {

          map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());

        }

        xmm_off += 2;

      }

      assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");

    } else if (UseSSE == 1) {

      int xmm_off = xmm_regs_as_doubles_off;

      for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {

        VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();

        map->set_callee_saved(VMRegImpl::stack2reg(xmm_off +     num_rt_args), xmm_name_0);

        xmm_off += 2;

      }

      assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");

    }

  }

  return map;

}

static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,

                                   bool save_fpu_registers = true) {

  __ block_comment("save_live_registers");

  // 64bit passes the args in regs to the c++ runtime

  int frame_size_in_slots = reg_save_frame_size NOT_LP64(+ num_rt_args); // args + thread

  // frame_size = round_to(frame_size, 4);

  sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );

  __ pusha();         // integer registers

  // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");

  // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");

  __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);

#ifdef ASSERT

  __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);

#endif

  if (save_fpu_registers) {

    if (UseSSE < 2) {

      // save FPU stack

      __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));

      __ fwait();

#ifdef ASSERT

      Label ok;

      __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());

      __ jccb(Assembler::equal, ok);

      __ stop("corrupted control word detected");

      __ bind(ok);

#endif

      // Reset the control word to guard against exceptions being unmasked

      // since fstp_d can cause FPU stack underflow exceptions.  Write it

      // into the on stack copy and then reload that to make sure that the

      // current and future values are correct.

      __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());

      __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));

      // Save the FPU registers in de-opt-able form

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));

      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));

    }

    if (UseSSE >= 2) {

      // save XMM registers

      // XMM registers can contain float or double values, but this is not known here,

      // so always save them as doubles.

      // note that float values are _not_ converted automatically, so for float values

      // the second word contains only garbage data.

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0), xmm0);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8), xmm1);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);

#ifdef _LP64

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);

      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);

#endif // _LP64

    } else if (UseSSE == 1) {

      // save XMM registers as float because double not supported without SSE2

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0), xmm0);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8), xmm1);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);

      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);

    }

  }

  // FPU stack must be empty now

  __ verify_FPU(0, "save_live_registers");

  return generate_oop_map(sasm, num_rt_args, save_fpu_registers);

}

static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {

  if (restore_fpu_registers) {

    if (UseSSE >= 2) {

      // restore XMM registers

      __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0));

      __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8));

      __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));

      __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));

      __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));

      __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));

      __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));

      __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));

#ifdef _LP64

      __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));

      __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));

      __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));

      __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));

      __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));

      __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));

      __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));

      __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));

#endif // _LP64