src/hotspot/share/opto/coalesce.cpp
author erikj
Tue, 12 Sep 2017 19:03:39 +0200
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parent 46378 hotspot/src/share/vm/opto/coalesce.cpp@4ccca1fdf627
child 51521 76a51e26d0ac
permissions -rw-r--r--
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/*
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 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "memory/allocation.inline.hpp"
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#include "opto/block.hpp"
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#include "opto/cfgnode.hpp"
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#include "opto/chaitin.hpp"
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#include "opto/coalesce.hpp"
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#include "opto/connode.hpp"
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#include "opto/indexSet.hpp"
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#include "opto/machnode.hpp"
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#include "opto/matcher.hpp"
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#include "opto/regmask.hpp"
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#ifndef PRODUCT
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void PhaseCoalesce::dump(Node *n) const {
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  // Being a const function means I cannot use 'Find'
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  uint r = _phc._lrg_map.find(n);
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  tty->print("L%d/N%d ",r,n->_idx);
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}
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void PhaseCoalesce::dump() const {
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  // I know I have a block layout now, so I can print blocks in a loop
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  for( uint i=0; i<_phc._cfg.number_of_blocks(); i++ ) {
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    uint j;
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    Block* b = _phc._cfg.get_block(i);
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    // Print a nice block header
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    tty->print("B%d: ",b->_pre_order);
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    for( j=1; j<b->num_preds(); j++ )
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      tty->print("B%d ", _phc._cfg.get_block_for_node(b->pred(j))->_pre_order);
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    tty->print("-> ");
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    for( j=0; j<b->_num_succs; j++ )
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      tty->print("B%d ",b->_succs[j]->_pre_order);
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    tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
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    uint cnt = b->number_of_nodes();
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    for( j=0; j<cnt; j++ ) {
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      Node *n = b->get_node(j);
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      dump( n );
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      tty->print("\t%s\t",n->Name());
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      // Dump the inputs
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      uint k;                   // Exit value of loop
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      for( k=0; k<n->req(); k++ ) // For all required inputs
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        if( n->in(k) ) dump( n->in(k) );
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        else tty->print("_ ");
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      int any_prec = 0;
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      for( ; k<n->len(); k++ )          // For all precedence inputs
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        if( n->in(k) ) {
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          if( !any_prec++ ) tty->print(" |");
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          dump( n->in(k) );
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        }
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      // Dump node-specific info
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      n->dump_spec(tty);
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      tty->print("\n");
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    }
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    tty->print("\n");
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  }
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}
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#endif
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// Combine the live ranges def'd by these 2 Nodes.  N2 is an input to N1.
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void PhaseCoalesce::combine_these_two(Node *n1, Node *n2) {
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  uint lr1 = _phc._lrg_map.find(n1);
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  uint lr2 = _phc._lrg_map.find(n2);
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  if( lr1 != lr2 &&             // Different live ranges already AND
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      !_phc._ifg->test_edge_sq( lr1, lr2 ) ) {  // Do not interfere
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    LRG *lrg1 = &_phc.lrgs(lr1);
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    LRG *lrg2 = &_phc.lrgs(lr2);
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    // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
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    // Now, why is int->oop OK?  We end up declaring a raw-pointer as an oop
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    // and in general that's a bad thing.  However, int->oop conversions only
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    // happen at GC points, so the lifetime of the misclassified raw-pointer
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    // is from the CheckCastPP (that converts it to an oop) backwards up
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    // through a merge point and into the slow-path call, and around the
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    // diamond up to the heap-top check and back down into the slow-path call.
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    // The misclassified raw pointer is NOT live across the slow-path call,
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    // and so does not appear in any GC info, so the fact that it is
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    // misclassified is OK.
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    if( (lrg1->_is_oop || !lrg2->_is_oop) && // not an oop->int cast AND
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        // Compatible final mask
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        lrg1->mask().overlap( lrg2->mask() ) ) {
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      // Merge larger into smaller.
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      if( lr1 > lr2 ) {
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        uint  tmp =  lr1;  lr1 =  lr2;  lr2 =  tmp;
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        Node   *n =   n1;   n1 =   n2;   n2 =    n;
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        LRG *ltmp = lrg1; lrg1 = lrg2; lrg2 = ltmp;
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      }
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      // Union lr2 into lr1
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      _phc.Union( n1, n2 );
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      if (lrg1->_maxfreq < lrg2->_maxfreq)
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        lrg1->_maxfreq = lrg2->_maxfreq;
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      // Merge in the IFG
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      _phc._ifg->Union( lr1, lr2 );
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      // Combine register restrictions
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      lrg1->AND(lrg2->mask());
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    }
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  }
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}
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// Copy coalescing
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void PhaseCoalesce::coalesce_driver() {
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  verify();
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  // Coalesce from high frequency to low
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  for (uint i = 0; i < _phc._cfg.number_of_blocks(); i++) {
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    coalesce(_phc._blks[i]);
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  }
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}
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// I am inserting copies to come out of SSA form.  In the general case, I am
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// doing a parallel renaming.  I'm in the Named world now, so I can't do a
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// general parallel renaming.  All the copies now use  "names" (live-ranges)
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// to carry values instead of the explicit use-def chains.  Suppose I need to
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// insert 2 copies into the same block.  They copy L161->L128 and L128->L132.
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// If I insert them in the wrong order then L128 will get clobbered before it
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// can get used by the second copy.  This cannot happen in the SSA model;
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// direct use-def chains get me the right value.  It DOES happen in the named
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// model so I have to handle the reordering of copies.
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//
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// In general, I need to topo-sort the placed copies to avoid conflicts.
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// Its possible to have a closed cycle of copies (e.g., recirculating the same
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// values around a loop).  In this case I need a temp to break the cycle.
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void PhaseAggressiveCoalesce::insert_copy_with_overlap( Block *b, Node *copy, uint dst_name, uint src_name ) {
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  // Scan backwards for the locations of the last use of the dst_name.
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  // I am about to clobber the dst_name, so the copy must be inserted
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  // after the last use.  Last use is really first-use on a backwards scan.
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  uint i = b->end_idx()-1;
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  while(1) {
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    Node *n = b->get_node(i);
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    // Check for end of virtual copies; this is also the end of the
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    // parallel renaming effort.
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    if (n->_idx < _unique) {
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      break;
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    }
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    uint idx = n->is_Copy();
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    assert( idx || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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    if (idx && _phc._lrg_map.find(n->in(idx)) == dst_name) {
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      break;
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    }
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    i--;
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  }
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  uint last_use_idx = i;
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  // Also search for any kill of src_name that exits the block.
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  // Since the copy uses src_name, I have to come before any kill.
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  uint kill_src_idx = b->end_idx();
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   173
  // There can be only 1 kill that exits any block and that is
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   174
  // the last kill.  Thus it is the first kill on a backwards scan.
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  i = b->end_idx()-1;
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   176
  while (1) {
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    Node *n = b->get_node(i);
1
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   178
    // Check for end of virtual copies; this is also the end of the
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   179
    // parallel renaming effort.
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   180
    if (n->_idx < _unique) {
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   181
      break;
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   182
    }
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   183
    assert( n->is_Copy() || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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   184
    if (_phc._lrg_map.find(n) == src_name) {
1
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   185
      kill_src_idx = i;
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   186
      break;
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   187
    }
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    i--;
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   189
  }
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  // Need a temp?  Last use of dst comes after the kill of src?
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   191
  if (last_use_idx >= kill_src_idx) {
1
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   192
    // Need to break a cycle with a temp
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   193
    uint idx = copy->is_Copy();
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   194
    Node *tmp = copy->clone();
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   195
    uint max_lrg_id = _phc._lrg_map.max_lrg_id();
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   196
    _phc.new_lrg(tmp, max_lrg_id);
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   197
    _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
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diff changeset
   198
1
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   199
    // Insert new temp between copy and source
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   200
    tmp ->set_req(idx,copy->in(idx));
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   201
    copy->set_req(idx,tmp);
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   202
    // Save source in temp early, before source is killed
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   203
    b->insert_node(tmp, kill_src_idx);
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   204
    _phc._cfg.map_node_to_block(tmp, b);
1
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   205
    last_use_idx++;
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   206
  }
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   207
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   208
  // Insert just after last use
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   209
  b->insert_node(copy, last_use_idx + 1);
1
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   210
}
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   211
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   212
void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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   213
  // We do LRGs compressing and fix a liveout data only here since the other
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   214
  // place in Split() is guarded by the assert which we never hit.
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   215
  _phc._lrg_map.compress_uf_map_for_nodes();
1
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   216
  // Fix block's liveout data for compressed live ranges.
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   217
  for (uint lrg = 1; lrg < _phc._lrg_map.max_lrg_id(); lrg++) {
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   218
    uint compressed_lrg = _phc._lrg_map.find(lrg);
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   219
    if (lrg != compressed_lrg) {
19330
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adlertz
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diff changeset
   220
      for (uint bidx = 0; bidx < _phc._cfg.number_of_blocks(); bidx++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
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parents: 19279
diff changeset
   221
        IndexSet *liveout = _phc._live->live(_phc._cfg.get_block(bidx));
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diff changeset
   222
        if (liveout->member(lrg)) {
1
489c9b5090e2 Initial load
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diff changeset
   223
          liveout->remove(lrg);
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parents:
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   224
          liveout->insert(compressed_lrg);
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diff changeset
   225
        }
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diff changeset
   226
      }
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diff changeset
   227
    }
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diff changeset
   228
  }
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parents:
diff changeset
   229
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   230
  // All new nodes added are actual copies to replace virtual copies.
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   231
  // Nodes with index less than '_unique' are original, non-virtual Nodes.
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   232
  _unique = C->unique();
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   233
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diff changeset
   234
  for (uint i = 0; i < _phc._cfg.number_of_blocks(); i++) {
18099
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17013
diff changeset
   235
    C->check_node_count(NodeLimitFudgeFactor, "out of nodes in coalesce");
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17013
diff changeset
   236
    if (C->failing()) return;
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adlertz
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diff changeset
   237
    Block *b = _phc._cfg.get_block(i);
1
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diff changeset
   238
    uint cnt = b->num_preds();  // Number of inputs to the Phi
489c9b5090e2 Initial load
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parents:
diff changeset
   239
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
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parents: 19334
diff changeset
   240
    for( uint l = 1; l<b->number_of_nodes(); l++ ) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   241
      Node *n = b->get_node(l);
1
489c9b5090e2 Initial load
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parents:
diff changeset
   242
489c9b5090e2 Initial load
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parents:
diff changeset
   243
      // Do not use removed-copies, use copied value instead
489c9b5090e2 Initial load
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diff changeset
   244
      uint ncnt = n->req();
489c9b5090e2 Initial load
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diff changeset
   245
      for( uint k = 1; k<ncnt; k++ ) {
489c9b5090e2 Initial load
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parents:
diff changeset
   246
        Node *copy = n->in(k);
489c9b5090e2 Initial load
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parents:
diff changeset
   247
        uint cidx = copy->is_Copy();
489c9b5090e2 Initial load
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parents:
diff changeset
   248
        if( cidx ) {
489c9b5090e2 Initial load
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parents:
diff changeset
   249
          Node *def = copy->in(cidx);
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22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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parents: 10255
diff changeset
   250
          if (_phc._lrg_map.find(copy) == _phc._lrg_map.find(def)) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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parents: 10255
diff changeset
   251
            n->set_req(k, def);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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diff changeset
   252
          }
1
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diff changeset
   253
        }
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parents:
diff changeset
   254
      }
489c9b5090e2 Initial load
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parents:
diff changeset
   255
489c9b5090e2 Initial load
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parents:
diff changeset
   256
      // Remove any explicit copies that get coalesced.
489c9b5090e2 Initial load
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parents:
diff changeset
   257
      uint cidx = n->is_Copy();
489c9b5090e2 Initial load
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parents:
diff changeset
   258
      if( cidx ) {
489c9b5090e2 Initial load
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parents:
diff changeset
   259
        Node *def = n->in(cidx);
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22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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parents: 10255
diff changeset
   260
        if (_phc._lrg_map.find(n) == _phc._lrg_map.find(def)) {
1
489c9b5090e2 Initial load
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parents:
diff changeset
   261
          n->replace_by(def);
489c9b5090e2 Initial load
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parents:
diff changeset
   262
          n->set_req(cidx,NULL);
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   263
          b->remove_node(l);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   264
          l--;
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parents:
diff changeset
   265
          continue;
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duke
parents:
diff changeset
   266
        }
489c9b5090e2 Initial load
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parents:
diff changeset
   267
      }
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parents:
diff changeset
   268
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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parents: 10255
diff changeset
   269
      if (n->is_Phi()) {
1
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parents:
diff changeset
   270
        // Get the chosen name for the Phi
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
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parents: 10255
diff changeset
   271
        uint phi_name = _phc._lrg_map.find(n);
1
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parents:
diff changeset
   272
        // Ignore the pre-allocated specials
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   273
        if (!phi_name) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   274
          continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   275
        }
1
489c9b5090e2 Initial load
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parents:
diff changeset
   276
        // Check for mismatch inputs to Phi
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   277
        for (uint j = 1; j < cnt; j++) {
1
489c9b5090e2 Initial load
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parents:
diff changeset
   278
          Node *m = n->in(j);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   279
          uint src_name = _phc._lrg_map.find(m);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   280
          if (src_name != phi_name) {
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   281
            Block *pred = _phc._cfg.get_block_for_node(b->pred(j));
1
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   282
            Node *copy;
489c9b5090e2 Initial load
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   283
            assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
27416
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   284
            // Rematerialize constants instead of copying them.
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   285
            // We do this only for immediate constants, we avoid constant table loads
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   286
            // because that will unsafely extend the live range of the constant table base.
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   287
            if (m->is_Mach() && m->as_Mach()->is_Con() && !m->as_Mach()->is_MachConstant() &&
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   288
                m->as_Mach()->rematerialize()) {
1
489c9b5090e2 Initial load
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parents:
diff changeset
   289
              copy = m->clone();
489c9b5090e2 Initial load
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parents:
diff changeset
   290
              // Insert the copy in the predecessor basic block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   291
              pred->add_inst(copy);
489c9b5090e2 Initial load
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parents:
diff changeset
   292
              // Copy any flags as well
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22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   293
              _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
1
489c9b5090e2 Initial load
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parents:
diff changeset
   294
            } else {
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   295
              uint ireg = m->ideal_reg();
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   296
              if (ireg == 0 || ireg == Op_RegFlags) {
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   297
                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   298
                       m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::PhiInput));
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   299
                C->record_method_not_compilable("attempted to spill a non-spillable item");
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   300
                return;
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   301
              }
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   302
              const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
   303
              copy = new MachSpillCopyNode(MachSpillCopyNode::PhiInput, m, *rm, *rm);
1
489c9b5090e2 Initial load
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parents:
diff changeset
   304
              // Find a good place to insert.  Kinda tricky, use a subroutine
489c9b5090e2 Initial load
duke
parents:
diff changeset
   305
              insert_copy_with_overlap(pred,copy,phi_name,src_name);
489c9b5090e2 Initial load
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parents:
diff changeset
   306
            }
489c9b5090e2 Initial load
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parents:
diff changeset
   307
            // Insert the copy in the use-def chain
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   308
            n->set_req(j, copy);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   309
            _phc._cfg.map_node_to_block(copy, pred);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   310
            // Extend ("register allocate") the names array for the copy.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   311
            _phc._lrg_map.extend(copy->_idx, phi_name);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   312
          } // End of if Phi names do not match
489c9b5090e2 Initial load
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parents:
diff changeset
   313
        } // End of for all inputs to Phi
489c9b5090e2 Initial load
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parents:
diff changeset
   314
      } else { // End of if Phi
489c9b5090e2 Initial load
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parents:
diff changeset
   315
489c9b5090e2 Initial load
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parents:
diff changeset
   316
        // Now check for 2-address instructions
489c9b5090e2 Initial load
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parents:
diff changeset
   317
        uint idx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   318
        if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   319
          // Get the chosen name for the Node
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   320
          uint name = _phc._lrg_map.find(n);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   321
          assert (name, "no 2-address specials");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   322
          // Check for name mis-match on the 2-address input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   323
          Node *m = n->in(idx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   324
          if (_phc._lrg_map.find(m) != name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   325
            Node *copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   326
            assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   327
            // At this point it is unsafe to extend live ranges (6550579).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   328
            // Rematerialize only constants as we do for Phi above.
27416
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   329
            if (m->is_Mach() && m->as_Mach()->is_Con() && !m->as_Mach()->is_MachConstant() &&
862162c5a8e0 8047383: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 24923
diff changeset
   330
                m->as_Mach()->rematerialize()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   331
              copy = m->clone();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   332
              // Insert the copy in the basic block, just before us
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   333
              b->insert_node(copy, l++);
19334
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   334
              l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   335
            } else {
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   336
              uint ireg = m->ideal_reg();
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   337
              if (ireg == 0 || ireg == Op_RegFlags) {
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   338
                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   339
                       m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::TwoAddress));
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   340
                C->record_method_not_compilable("attempted to spill a non-spillable item");
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   341
                return;
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   342
              }
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   343
              const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
   344
              copy = new MachSpillCopyNode(MachSpillCopyNode::TwoAddress, m, *rm, *rm);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   345
              // Insert the copy in the basic block, just before us
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   346
              b->insert_node(copy, l++);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   347
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   348
            // Insert the copy in the use-def chain
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   349
            n->set_req(idx, copy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   350
            // Extend ("register allocate") the names array for the copy.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   351
            _phc._lrg_map.extend(copy->_idx, name);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   352
            _phc._cfg.map_node_to_block(copy, b);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   353
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   354
489c9b5090e2 Initial load
duke
parents:
diff changeset
   355
        } // End of is two-adr
489c9b5090e2 Initial load
duke
parents:
diff changeset
   356
489c9b5090e2 Initial load
duke
parents:
diff changeset
   357
        // Insert a copy at a debug use for a lrg which has high frequency
19721
8ecbb2cdc965 8023988: Move local scheduling of nodes to the CFG creation and code motion phase (PhaseCFG)
adlertz
parents: 19717
diff changeset
   358
        if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || _phc._cfg.is_uncommon(b)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   359
          // Walk the debug inputs to the node and check for lrg freq
489c9b5090e2 Initial load
duke
parents:
diff changeset
   360
          JVMState* jvms = n->jvms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   361
          uint debug_start = jvms ? jvms->debug_start() : 999999;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
          uint debug_end   = jvms ? jvms->debug_end()   : 999999;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   363
          for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
            // Do not split monitors; they are only needed for debug table
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
            // entries and need no code.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   366
            if (jvms->is_monitor_use(inpidx)) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   367
              continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   368
            }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
            Node *inp = n->in(inpidx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   370
            uint nidx = _phc._lrg_map.live_range_id(inp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
            LRG &lrg = lrgs(nidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
            // If this lrg has a high frequency use/def
2340
cb47f8209cd8 6810845: Performance regression in mpegaudio on x64
kvn
parents: 2131
diff changeset
   374
            if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
              // If the live range is also live out of this block (like it
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
              // would be for a fast/slow idiom), the normal spill mechanism
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
              // does an excellent job.  If it is not live out of this block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
              // (like it would be for debug info to uncommon trap) splitting
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
              // the live range now allows a better allocation in the high
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
              // frequency blocks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   381
              //   Build_IFG_virtual has converted the live sets to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
              // live-IN info, not live-OUT info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
              uint k;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
              for( k=0; k < b->_num_succs; k++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   385
                if( _phc._live->live(b->_succs[k])->member( nidx ) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
                  break;      // Live in to some successor block?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
              if( k < b->_num_succs )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
                continue;     // Live out; do not pre-split
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
              // Split the lrg at this use
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   390
              uint ireg = inp->ideal_reg();
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   391
              if (ireg == 0 || ireg == Op_RegFlags) {
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 43482
diff changeset
   392
                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
43482
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   393
                       inp->_idx, inp->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::DebugUse));
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   394
                C->record_method_not_compilable("attempted to spill a non-spillable item");
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   395
                return;
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   396
              }
7417485c50f9 8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
thartmann
parents: 27416
diff changeset
   397
              const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
   398
              Node* copy = new MachSpillCopyNode(MachSpillCopyNode::DebugUse, inp, *rm, *rm);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
              // Insert the copy in the use-def chain
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
              n->set_req(inpidx, copy );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
              // Insert the copy in the basic block, just before us
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   402
              b->insert_node(copy,  l++);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
              // Extend ("register allocate") the names array for the copy.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   404
              uint max_lrg_id = _phc._lrg_map.max_lrg_id();
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   405
              _phc.new_lrg(copy, max_lrg_id);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   406
              _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   407
              _phc._cfg.map_node_to_block(copy, b);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
              //tty->print_cr("Split a debug use in Aggressive Coalesce");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
            }  // End of if high frequency use/def
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
          }  // End of for all debug inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
        }  // End of if low frequency safepoint
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
      } // End of if Phi
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
    } // End of for all instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
  } // End of for all blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   419
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
// Aggressive (but pessimistic) copy coalescing of a single block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
// The following coalesce pass represents a single round of aggressive
489c9b5090e2 Initial load
duke
parents:
diff changeset
   423
// pessimistic coalesce.  "Aggressive" means no attempt to preserve
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
// colorability when coalescing.  This occasionally means more spills, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
// it also means fewer rounds of coalescing for better code - and that means
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
// faster compiles.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
// "Pessimistic" means we do not hit the fixed point in one pass (and we are
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
// reaching for the least fixed point to boot).  This is typically solved
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
// with a few more rounds of coalescing, but the compiler must run fast.  We
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
// could optimistically coalescing everything touching PhiNodes together
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
// into one big live range, then check for self-interference.  Everywhere
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
// the live range interferes with self it would have to be split.  Finding
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
// the right split points can be done with some heuristics (based on
489c9b5090e2 Initial load
duke
parents:
diff changeset
   435
// expected frequency of edges in the live range).  In short, it's a real
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
// research problem and the timeline is too short to allow such research.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
// Further thoughts: (1) build the LR in a pass, (2) find self-interference
489c9b5090e2 Initial load
duke
parents:
diff changeset
   438
// in another pass, (3) per each self-conflict, split, (4) split by finding
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
// the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
// according to the GCM algorithm (or just exec freq on CFG edges).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
void PhaseAggressiveCoalesce::coalesce( Block *b ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
  // Copies are still "virtual" - meaning we have not made them explicitly
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
  // copies.  Instead, Phi functions of successor blocks have mis-matched
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
  // live-ranges.  If I fail to coalesce, I'll have to insert a copy to line
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
  // up the live-ranges.  Check for Phis in successor blocks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
  uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
  for( i=0; i<b->_num_succs; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
    Block *bs = b->_succs[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
    // Find index of 'b' in 'bs' predecessors
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
    uint j=1;
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   452
    while (_phc._cfg.get_block_for_node(bs->pred(j)) != b) {
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   453
      j++;
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   454
    }
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   455
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
    // Visit all the Phis in successor block
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   457
    for( uint k = 1; k<bs->number_of_nodes(); k++ ) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   458
      Node *n = bs->get_node(k);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
      if( !n->is_Phi() ) break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
      combine_these_two( n, n->in(j) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
  } // End of for all successor blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
  // Check _this_ block for 2-address instructions and copies.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
  uint cnt = b->end_idx();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
  for( i = 1; i<cnt; i++ ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   468
    Node *n = b->get_node(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
    uint idx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
    // 2-address instructions have a virtual Copy matching their input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
    // to their output
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   472
    if (n->is_Mach() && (idx = n->as_Mach()->two_adr())) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
      MachNode *mach = n->as_Mach();
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   474
      combine_these_two(mach, mach->in(idx));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
  } // End of for all instructions in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   479
PhaseConservativeCoalesce::PhaseConservativeCoalesce(PhaseChaitin &chaitin) : PhaseCoalesce(chaitin) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   480
  _ulr.initialize(_phc._lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
void PhaseConservativeCoalesce::verify() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
  _phc.set_was_low();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
void PhaseConservativeCoalesce::union_helper( Node *lr1_node, Node *lr2_node, uint lr1, uint lr2, Node *src_def, Node *dst_copy, Node *src_copy, Block *b, uint bindex ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
  // Join live ranges.  Merge larger into smaller.  Union lr2 into lr1 in the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
  // union-find tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
  _phc.Union( lr1_node, lr2_node );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
  // Single-def live range ONLY if both live ranges are single-def.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
  // If both are single def, then src_def powers one live range
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
  // and def_copy powers the other.  After merging, src_def powers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
  // the combined live range.
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   498
  lrgs(lr1)._def = (lrgs(lr1).is_multidef() ||
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   499
                        lrgs(lr2).is_multidef() )
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
    ? NodeSentinel : src_def;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
  lrgs(lr2)._def = NULL;    // No def for lrg 2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
  lrgs(lr2).Clear();        // Force empty mask for LRG 2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
  //lrgs(lr2)._size = 0;      // Live-range 2 goes dead
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
  lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
  lrgs(lr2)._is_oop = 0;    // In particular, not an oop for GC info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
  if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
    lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
  // Copy original value instead.  Intermediate copies go dead, and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
  // the dst_copy becomes useless.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
  int didx = dst_copy->is_Copy();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
  dst_copy->set_req( didx, src_def );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
  // Add copy to free list
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
  // _phc.free_spillcopy(b->_nodes[bindex]);
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   516
  assert( b->get_node(bindex) == dst_copy, "" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
  dst_copy->replace_by( dst_copy->in(didx) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
  dst_copy->set_req( didx, NULL);
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   519
  b->remove_node(bindex);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
  if( bindex < b->_ihrp_index ) b->_ihrp_index--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
  if( bindex < b->_fhrp_index ) b->_fhrp_index--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
  // Stretched lr1; add it to liveness of intermediate blocks
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   524
  Block *b2 = _phc._cfg.get_block_for_node(src_copy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
  while( b != b2 ) {
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   526
    b = _phc._cfg.get_block_for_node(b->pred(1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
    _phc._live->live(b)->insert(lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
// Factored code from copy_copy that computes extra interferences from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
// lengthening a live range by double-coalescing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
  assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
  assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
  Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
  Block *b2 = b;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
  uint bindex2 = bindex;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
  while( 1 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
    // Find previous instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
    bindex2--;                  // Chain backwards 1 instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
    while( bindex2 == 0 ) {     // At block start, find prior block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
      assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   545
      b2 = _phc._cfg.get_block_for_node(b2->pred(1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
      bindex2 = b2->end_idx()-1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
    // Get prior instruction
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   549
    assert(bindex2 < b2->number_of_nodes(), "index out of bounds");
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   550
    Node *x = b2->get_node(bindex2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
    if( x == prev_copy ) {      // Previous copy in copy chain?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
      if( prev_copy == src_copy)// Found end of chain and all interferences
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
        break;                  // So break out of loop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
      // Else work back one in copy chain
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
      prev_copy = prev_copy->in(prev_copy->is_Copy());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
    } else {                    // Else collect interferences
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   557
      uint lidx = _phc._lrg_map.find(x);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
      // Found another def of live-range being stretched?
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   559
      if(lidx == lr1) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   560
        return max_juint;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   561
      }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   562
      if(lidx == lr2) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   563
        return max_juint;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   564
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
      // If we attempt to coalesce across a bound def
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
      if( lrgs(lidx).is_bound() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
        // Do not let the coalesced LRG expect to get the bound color
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
        rm.SUBTRACT( lrgs(lidx).mask() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
        // Recompute rm_size
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
        rm_size = rm.Size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
        //if( rm._flags ) rm_size += 1000000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
        if( reg_degree >= rm_size ) return max_juint;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
      if( rm.overlap(lrgs(lidx).mask()) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
        // Insert lidx into union LRG; returns TRUE if actually inserted
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
        if( _ulr.insert(lidx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
          // Infinite-stack neighbors do not alter colorability, as they
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
          // can always color to some other color.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
          if( !lrgs(lidx).mask().is_AllStack() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
            // If this coalesce will make any new neighbor uncolorable,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
            // do not coalesce.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
            if( lrgs(lidx).just_lo_degree() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
              return max_juint;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
            // Bump our degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
            if( ++reg_degree >= rm_size )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
              return max_juint;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
          } // End of if not infinite-stack neighbor
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
        } // End of if actually inserted
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
      } // End of if live range overlaps
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 1217
diff changeset
   591
    } // End of else collect interferences for 1 node
98f9cef66a34 6810672: Comment typos
twisti
parents: 1217
diff changeset
   592
  } // End of while forever, scan back for interferences
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
  return reg_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
void PhaseConservativeCoalesce::update_ifg(uint lr1, uint lr2, IndexSet *n_lr1, IndexSet *n_lr2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
  // Some original neighbors of lr1 might have gone away
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
  // because the constrained register mask prevented them.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
  // Remove lr1 from such neighbors.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
  IndexSetIterator one(n_lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
  uint neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
  LRG &lrg1 = lrgs(lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
  while ((neighbor = one.next()) != 0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
    if( !_ulr.member(neighbor) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
      if( _phc._ifg->neighbors(neighbor)->remove(lr1) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
        lrgs(neighbor).inc_degree( -lrg1.compute_degree(lrgs(neighbor)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
  // lr2 is now called (coalesced into) lr1.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
  // Remove lr2 from the IFG.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
  IndexSetIterator two(n_lr2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
  LRG &lrg2 = lrgs(lr2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
  while ((neighbor = two.next()) != 0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
    if( _phc._ifg->neighbors(neighbor)->remove(lr2) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
      lrgs(neighbor).inc_degree( -lrg2.compute_degree(lrgs(neighbor)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
  // Some neighbors of intermediate copies now interfere with the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
  // combined live range.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
  IndexSetIterator three(&_ulr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
  while ((neighbor = three.next()) != 0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
    if( _phc._ifg->neighbors(neighbor)->insert(lr1) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
      lrgs(neighbor).inc_degree( lrg1.compute_degree(lrgs(neighbor)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
static void record_bias( const PhaseIFG *ifg, int lr1, int lr2 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
  // Tag copy bias here
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
  if( !ifg->lrgs(lr1)._copy_bias )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
    ifg->lrgs(lr1)._copy_bias = lr2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
  if( !ifg->lrgs(lr2)._copy_bias )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
    ifg->lrgs(lr2)._copy_bias = lr1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
// See if I can coalesce a series of multiple copies together.  I need the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
// final dest copy and the original src copy.  They can be the same Node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
// Compute the compatible register masks.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   636
bool PhaseConservativeCoalesce::copy_copy(Node *dst_copy, Node *src_copy, Block *b, uint bindex) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   638
  if (!dst_copy->is_SpillCopy()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   639
    return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   640
  }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   641
  if (!src_copy->is_SpillCopy()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   642
    return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   643
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
  Node *src_def = src_copy->in(src_copy->is_Copy());
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   645
  uint lr1 = _phc._lrg_map.find(dst_copy);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   646
  uint lr2 = _phc._lrg_map.find(src_def);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
  // Same live ranges already?
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   649
  if (lr1 == lr2) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   650
    return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   651
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  // Interfere?
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   654
  if (_phc._ifg->test_edge_sq(lr1, lr2)) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   655
    return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   656
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
  // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   659
  if (!lrgs(lr1)._is_oop && lrgs(lr2)._is_oop) { // not an oop->int cast
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
    return false;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   661
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
  // Coalescing between an aligned live range and a mis-aligned live range?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
  // No, no!  Alignment changes how we count degree.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   665
  if (lrgs(lr1)._fat_proj != lrgs(lr2)._fat_proj) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
    return false;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   667
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
  // Sort; use smaller live-range number
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
  Node *lr1_node = dst_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
  Node *lr2_node = src_def;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 10255
diff changeset
   672
  if (lr1 > lr2) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
    uint tmp = lr1; lr1 = lr2; lr2 = tmp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
    lr1_node = src_def;  lr2_node = dst_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
  // Check for compatibility of the 2 live ranges by
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
  // intersecting their allowed register sets.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
  RegMask rm = lrgs(lr1).mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
  rm.AND(lrgs(lr2).mask());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
  // Number of bits free
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
  uint rm_size = rm.Size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   684
  if (UseFPUForSpilling && rm.is_AllStack() ) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   685
    // Don't coalesce when frequency difference is large
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   686
    Block *dst_b = _phc._cfg.get_block_for_node(dst_copy);
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   687
    Block *src_def_b = _phc._cfg.get_block_for_node(src_def);
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   688
    if (src_def_b->_freq > 10*dst_b->_freq )
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   689
      return false;
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   690
  }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5547
diff changeset
   691
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
  // If we can use any stack slot, then effective size is infinite
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
  if( rm.is_AllStack() ) rm_size += 1000000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  // Incompatible masks, no way to coalesce
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
  if( rm_size == 0 ) return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
  // Another early bail-out test is when we are double-coalescing and the
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 1217
diff changeset
   698
  // 2 copies are separated by some control flow.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
  if( dst_copy != src_copy ) {
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   700
    Block *src_b = _phc._cfg.get_block_for_node(src_copy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
    Block *b2 = b;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
    while( b2 != src_b ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
      if( b2->num_preds() > 2 ){// Found merge-point
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
        _phc._lost_opp_cflow_coalesce++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
        // extra record_bias commented out because Chris believes it is not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
        // productive.  Since we can record only 1 bias, we want to choose one
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
        // that stands a chance of working and this one probably does not.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
        //record_bias( _phc._lrgs, lr1, lr2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
        return false;           // To hard to find all interferences
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
      }
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   711
      b2 = _phc._cfg.get_block_for_node(b2->pred(1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
  // Union the two interference sets together into '_ulr'
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
  uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
  if( reg_degree >= rm_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
    record_bias( _phc._ifg, lr1, lr2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
    return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
  // Now I need to compute all the interferences between dst_copy and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
  // src_copy.  I'm not willing visit the entire interference graph, so
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
  // I limit my search to things in dst_copy's block or in a straight
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
  // line of previous blocks.  I give up at merge points or when I get
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
  // more interferences than my degree.  I can stop when I find src_copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
  if( dst_copy != src_copy ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
    reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
    if( reg_degree == max_juint ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
      record_bias( _phc._ifg, lr1, lr2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
      return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
  } // End of if dst_copy & src_copy are different
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
  // ---- THE COMBINED LRG IS COLORABLE ----
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
  // YEAH - Now coalesce this copy away
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
  assert( lrgs(lr1).num_regs() == lrgs(lr2).num_regs(),   "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
  IndexSet *n_lr1 = _phc._ifg->neighbors(lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
  IndexSet *n_lr2 = _phc._ifg->neighbors(lr2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
  // Update the interference graph
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
  update_ifg(lr1, lr2, n_lr1, n_lr2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
  _ulr.remove(lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
  // Uncomment the following code to trace Coalescing in great detail.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
  //if (false) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
  //  tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
  //  tty->print_cr("#######################################");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
  //  tty->print_cr("union %d and %d", lr1, lr2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
  //  n_lr1->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
  //  n_lr2->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
  //  tty->print_cr("resulting set is");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
  //  _ulr.dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
  //}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
  // Replace n_lr1 with the new combined live range.  _ulr will use
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
  // n_lr1's old memory on the next iteration.  n_lr2 is cleared to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
  // send its internal memory to the free list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
  _ulr.swap(n_lr1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
  _ulr.clear();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
  n_lr2->clear();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
  lrgs(lr1).set_degree( _phc._ifg->effective_degree(lr1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
  lrgs(lr2).set_degree( 0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
  // Join live ranges.  Merge larger into smaller.  Union lr2 into lr1 in the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
  // union-find tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
  union_helper( lr1_node, lr2_node, lr1, lr2, src_def, dst_copy, src_copy, b, bindex );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
  // Combine register restrictions
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
  lrgs(lr1).set_mask(rm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
  lrgs(lr1).compute_set_mask_size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
  lrgs(lr1)._cost += lrgs(lr2)._cost;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
  lrgs(lr1)._area += lrgs(lr2)._area;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
  // While its uncommon to successfully coalesce live ranges that started out
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
  // being not-lo-degree, it can happen.  In any case the combined coalesced
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
  // live range better Simplify nicely.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
  lrgs(lr1)._was_lo = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
  // kinda expensive to do all the time
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
  //tty->print_cr("warning: slow verify happening");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
  //_phc._ifg->verify( &_phc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
  return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
// Conservative (but pessimistic) copy coalescing of a single block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
void PhaseConservativeCoalesce::coalesce( Block *b ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
  // Bail out on infrequent blocks
19721
8ecbb2cdc965 8023988: Move local scheduling of nodes to the CFG creation and code motion phase (PhaseCFG)
adlertz
parents: 19717
diff changeset
   795
  if (_phc._cfg.is_uncommon(b)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
    return;
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
   797
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
  // Check this block for copies.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
  for( uint i = 1; i<b->end_idx(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
    // Check for actual copies on inputs.  Coalesce a copy into its
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
    // input if use and copy's input are compatible.
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   802
    Node *copy1 = b->get_node(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
    uint idx1 = copy1->is_Copy();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
    if( !idx1 ) continue;       // Not a copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
    if( copy_copy(copy1,copy1,b,i) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
      i--;                      // Retry, same location in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
      PhaseChaitin::_conserv_coalesce++;  // Collect stats on success
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
      continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
}