author | erikj |
Tue, 12 Sep 2017 19:03:39 +0200 | |
changeset 47216 | 71c04702a3d5 |
parent 47091 | hotspot/src/os_cpu/linux_s390/vm/atomic_linux_s390.hpp@4cc46bb5057b |
child 47552 | 8a3599d60996 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2016 SAP SE. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP |
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#define OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP |
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#include "runtime/atomic.hpp" |
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#include "runtime/os.hpp" |
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#include "vm_version_s390.hpp" |
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// Note that the compare-and-swap instructions on System z perform |
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// a serialization function before the storage operand is fetched |
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// and again after the operation is completed. |
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// |
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// Used constraint modifiers: |
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// = write-only access: Value on entry to inline-assembler code irrelevant. |
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// + read/write access: Value on entry is used; on exit value is changed. |
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// read-only access: Value on entry is used and never changed. |
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// & early-clobber access: Might be modified before all read-only operands |
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// have been used. |
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// a address register operand (not GR0). |
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// d general register operand (including GR0) |
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// Q memory operand w/o index register. |
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// 0..9 operand reference (by operand position). |
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// Used for operands that fill multiple roles. One example would be a |
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// write-only operand receiving its initial value from a read-only operand. |
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// Refer to cmpxchg(..) operand #0 and variable cmp_val for a real-life example. |
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// |
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// On System z, all store operations are atomic if the address where the data is stored into |
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// is an integer multiple of the data length. Furthermore, all stores are ordered: |
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// a store which occurs conceptually before another store becomes visible to other CPUs |
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// before the other store becomes visible. |
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inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; } |
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inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; } |
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inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; } |
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inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; } |
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//------------ |
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// Atomic::add |
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//------------ |
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// These methods force the value in memory to be augmented by the passed increment. |
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// Both, memory value and increment, are treated as 32bit signed binary integers. |
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// No overflow exceptions are recognized, and the condition code does not hold |
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// information about the value in memory. |
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// |
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// The value in memory is updated by using a compare-and-swap instruction. The |
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// instruction is retried as often as required. |
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// |
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// The return value of the method is the value that was successfully stored. At the |
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// time the caller receives back control, the value in memory may have changed already. |
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template<size_t byte_size> |
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struct Atomic::PlatformAdd |
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: Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> > |
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{ |
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template<typename I, typename D> |
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D add_and_fetch(I add_value, D volatile* dest) const; |
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}; |
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<4>::add_and_fetch(I inc, D volatile* dest) const { |
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STATIC_ASSERT(4 == sizeof(I)); |
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STATIC_ASSERT(4 == sizeof(D)); |
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D old, upd; |
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if (VM_Version::has_LoadAndALUAtomicV1()) { |
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__asm__ __volatile__ ( |
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" LGFR 0,%[inc] \n\t" // save increment |
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" LA 3,%[mem] \n\t" // force data address into ARG2 |
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// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value |
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// " LAA 2,0,0(3) \n\t" // actually coded instruction |
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" .byte 0xeb \n\t" // LAA main opcode |
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" .byte 0x20 \n\t" // R1,R3 |
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" .byte 0x30 \n\t" // R2,disp1 |
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" .byte 0x00 \n\t" // disp2,disp3 |
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" .byte 0x00 \n\t" // disp4,disp5 |
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" .byte 0xf8 \n\t" // LAA minor opcode |
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" AR 2,0 \n\t" // calc new value in register |
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" LR %[upd],2 \n\t" // move to result register |
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//---< outputs >--- |
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: [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "r0", "r2", "r3", "memory" |
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} else { |
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__asm__ __volatile__ ( |
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" LLGF %[old],%[mem] \n\t" // get old value |
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"0: LA %[upd],0(%[inc],%[old]) \n\t" // calc result |
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" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
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" JNE 0b \n\t" // no success? -> retry |
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//---< outputs >--- |
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: [old] "=&a" (old) // write-only, old counter value |
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, [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "memory" |
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} |
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return upd; |
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} |
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<8>::add_and_fetch(I inc, D volatile* dest) const { |
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STATIC_ASSERT(8 == sizeof(I)); |
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STATIC_ASSERT(8 == sizeof(D)); |
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D old, upd; |
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if (VM_Version::has_LoadAndALUAtomicV1()) { |
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__asm__ __volatile__ ( |
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" LGR 0,%[inc] \n\t" // save increment |
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" LA 3,%[mem] \n\t" // force data address into ARG2 |
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// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value |
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// " LAAG 2,0,0(3) \n\t" // actually coded instruction |
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" .byte 0xeb \n\t" // LAA main opcode |
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" .byte 0x20 \n\t" // R1,R3 |
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" .byte 0x30 \n\t" // R2,disp1 |
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" .byte 0x00 \n\t" // disp2,disp3 |
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" .byte 0x00 \n\t" // disp4,disp5 |
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" .byte 0xe8 \n\t" // LAA minor opcode |
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" AGR 2,0 \n\t" // calc new value in register |
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" LGR %[upd],2 \n\t" // move to result register |
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//---< outputs >--- |
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: [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "r0", "r2", "r3", "memory" |
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); |
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} else { |
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__asm__ __volatile__ ( |
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" LG %[old],%[mem] \n\t" // get old value |
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"0: LA %[upd],0(%[inc],%[old]) \n\t" // calc result |
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" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
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" JNE 0b \n\t" // no success? -> retry |
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//---< outputs >--- |
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: [old] "=&a" (old) // write-only, old counter value |
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, [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "memory" |
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); |
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} |
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return upd; |
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} |
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//------------ |
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// Atomic::inc |
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//------------ |
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// These methods force the value in memory to be incremented (augmented by 1). |
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// Both, memory value and increment, are treated as 32bit signed binary integers. |
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// No overflow exceptions are recognized, and the condition code does not hold |
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// information about the value in memory. |
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// |
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// The value in memory is updated by using a compare-and-swap instruction. The |
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// instruction is retried as often as required. |
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inline void Atomic::inc(volatile jint* dest) { |
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unsigned int old, upd; |
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if (VM_Version::has_LoadAndALUAtomicV1()) { |
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// tty->print_cr("Atomic::inc called... dest @%p", dest); |
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__asm__ __volatile__ ( |
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" LGHI 2,1 \n\t" // load increment |
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" LA 3,%[mem] \n\t" // force data address into ARG2 |
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// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value |
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// " LAA 2,2,0(3) \n\t" // actually coded instruction |
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" .byte 0xeb \n\t" // LAA main opcode |
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" .byte 0x22 \n\t" // R1,R3 |
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" .byte 0x30 \n\t" // R2,disp1 |
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" .byte 0x00 \n\t" // disp2,disp3 |
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" .byte 0x00 \n\t" // disp4,disp5 |
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" .byte 0xf8 \n\t" // LAA minor opcode |
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" AGHI 2,1 \n\t" // calc new value in register |
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" LR %[upd],2 \n\t" // move to result register |
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//---< outputs >--- |
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: [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: |
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// : [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "r2", "r3", "memory" |
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); |
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} else { |
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__asm__ __volatile__ ( |
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" LLGF %[old],%[mem] \n\t" // get old value |
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"0: LA %[upd],1(,%[old]) \n\t" // calc result |
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" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
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" JNE 0b \n\t" // no success? -> retry |
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//---< outputs >--- |
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: [old] "=&a" (old) // write-only, old counter value |
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, [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: |
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//---< clobbered >--- |
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: "cc", "memory" |
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); |
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} |
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} |
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inline void Atomic::inc_ptr(volatile intptr_t* dest) { |
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unsigned long old, upd; |
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if (VM_Version::has_LoadAndALUAtomicV1()) { |
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__asm__ __volatile__ ( |
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256 |
" LGHI 2,1 \n\t" // load increment |
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" LA 3,%[mem] \n\t" // force data address into ARG2 |
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// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value |
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// " LAAG 2,2,0(3) \n\t" // actually coded instruction |
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" .byte 0xeb \n\t" // LAA main opcode |
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" .byte 0x22 \n\t" // R1,R3 |
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" .byte 0x30 \n\t" // R2,disp1 |
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" .byte 0x00 \n\t" // disp2,disp3 |
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" .byte 0x00 \n\t" // disp4,disp5 |
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" .byte 0xe8 \n\t" // LAA minor opcode |
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" AGHI 2,1 \n\t" // calc new value in register |
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" LR %[upd],2 \n\t" // move to result register |
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//---< outputs >--- |
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269 |
: [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: |
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// : [inc] "a" (inc) // read-only. |
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//---< clobbered >--- |
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: "cc", "r2", "r3", "memory" |
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); |
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} else { |
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__asm__ __volatile__ ( |
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" LG %[old],%[mem] \n\t" // get old value |
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"0: LA %[upd],1(,%[old]) \n\t" // calc result |
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" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
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" JNE 0b \n\t" // no success? -> retry |
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//---< outputs >--- |
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: [old] "=&a" (old) // write-only, old counter value |
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, [upd] "=&d" (upd) // write-only, updated counter value |
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
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//---< inputs >--- |
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: |
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//---< clobbered >--- |
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: "cc", "memory" |
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); |
292 |
} |
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} |
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||
295 |
inline void Atomic::inc_ptr(volatile void* dest) { |
|
296 |
inc_ptr((volatile intptr_t*)dest); |
|
297 |
} |
|
298 |
||
299 |
//------------ |
|
300 |
// Atomic::dec |
|
301 |
//------------ |
|
302 |
// These methods force the value in memory to be decremented (augmented by -1). |
|
303 |
// Both, memory value and decrement, are treated as 32bit signed binary integers. |
|
304 |
// No overflow exceptions are recognized, and the condition code does not hold |
|
305 |
// information about the value in memory. |
|
306 |
// |
|
307 |
// The value in memory is updated by using a compare-and-swap instruction. The |
|
308 |
// instruction is retried as often as required. |
|
309 |
||
310 |
inline void Atomic::dec(volatile jint* dest) { |
|
311 |
unsigned int old, upd; |
|
312 |
||
313 |
if (VM_Version::has_LoadAndALUAtomicV1()) { |
|
314 |
__asm__ __volatile__ ( |
|
315 |
" LGHI 2,-1 \n\t" // load increment |
|
316 |
" LA 3,%[mem] \n\t" // force data address into ARG2 |
|
317 |
// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value |
|
318 |
// " LAA 2,2,0(3) \n\t" // actually coded instruction |
|
319 |
" .byte 0xeb \n\t" // LAA main opcode |
|
320 |
" .byte 0x22 \n\t" // R1,R3 |
|
321 |
" .byte 0x30 \n\t" // R2,disp1 |
|
322 |
" .byte 0x00 \n\t" // disp2,disp3 |
|
323 |
" .byte 0x00 \n\t" // disp4,disp5 |
|
324 |
" .byte 0xf8 \n\t" // LAA minor opcode |
|
325 |
" AGHI 2,-1 \n\t" // calc new value in register |
|
326 |
" LR %[upd],2 \n\t" // move to result register |
|
327 |
//---< outputs >--- |
|
328 |
: [upd] "=&d" (upd) // write-only, updated counter value |
|
329 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
330 |
//---< inputs >--- |
|
331 |
: |
|
332 |
// : [inc] "a" (inc) // read-only. |
|
333 |
//---< clobbered >--- |
|
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334 |
: "cc", "r2", "r3", "memory" |
42065 | 335 |
); |
336 |
} else { |
|
337 |
__asm__ __volatile__ ( |
|
338 |
" LLGF %[old],%[mem] \n\t" // get old value |
|
339 |
// LAY not supported by inline assembler |
|
340 |
// "0: LAY %[upd],-1(,%[old]) \n\t" // calc result |
|
341 |
"0: LR %[upd],%[old] \n\t" // calc result |
|
342 |
" AHI %[upd],-1 \n\t" |
|
343 |
" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
|
344 |
" JNE 0b \n\t" // no success? -> retry |
|
345 |
//---< outputs >--- |
|
346 |
: [old] "=&a" (old) // write-only, old counter value |
|
347 |
, [upd] "=&d" (upd) // write-only, updated counter value |
|
348 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
349 |
//---< inputs >--- |
|
350 |
: |
|
351 |
//---< clobbered >--- |
|
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352 |
: "cc", "memory" |
42065 | 353 |
); |
354 |
} |
|
355 |
} |
|
356 |
||
357 |
inline void Atomic::dec_ptr(volatile intptr_t* dest) { |
|
358 |
unsigned long old, upd; |
|
359 |
||
360 |
if (VM_Version::has_LoadAndALUAtomicV1()) { |
|
361 |
__asm__ __volatile__ ( |
|
362 |
" LGHI 2,-1 \n\t" // load increment |
|
363 |
" LA 3,%[mem] \n\t" // force data address into ARG2 |
|
364 |
// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value |
|
365 |
// " LAAG 2,2,0(3) \n\t" // actually coded instruction |
|
366 |
" .byte 0xeb \n\t" // LAA main opcode |
|
367 |
" .byte 0x22 \n\t" // R1,R3 |
|
368 |
" .byte 0x30 \n\t" // R2,disp1 |
|
369 |
" .byte 0x00 \n\t" // disp2,disp3 |
|
370 |
" .byte 0x00 \n\t" // disp4,disp5 |
|
371 |
" .byte 0xe8 \n\t" // LAA minor opcode |
|
372 |
" AGHI 2,-1 \n\t" // calc new value in register |
|
373 |
" LR %[upd],2 \n\t" // move to result register |
|
374 |
//---< outputs >--- |
|
375 |
: [upd] "=&d" (upd) // write-only, updated counter value |
|
376 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
377 |
//---< inputs >--- |
|
378 |
: |
|
379 |
// : [inc] "a" (inc) // read-only. |
|
380 |
//---< clobbered >--- |
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381 |
: "cc", "r2", "r3", "memory" |
42065 | 382 |
); |
383 |
} else { |
|
384 |
__asm__ __volatile__ ( |
|
385 |
" LG %[old],%[mem] \n\t" // get old value |
|
386 |
// LAY not supported by inline assembler |
|
387 |
// "0: LAY %[upd],-1(,%[old]) \n\t" // calc result |
|
388 |
"0: LGR %[upd],%[old] \n\t" // calc result |
|
389 |
" AGHI %[upd],-1 \n\t" |
|
390 |
" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem |
|
391 |
" JNE 0b \n\t" // no success? -> retry |
|
392 |
//---< outputs >--- |
|
393 |
: [old] "=&a" (old) // write-only, old counter value |
|
394 |
, [upd] "=&d" (upd) // write-only, updated counter value |
|
395 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
396 |
//---< inputs >--- |
|
397 |
: |
|
398 |
//---< clobbered >--- |
|
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|
399 |
: "cc", "memory" |
42065 | 400 |
); |
401 |
} |
|
402 |
} |
|
403 |
||
404 |
inline void Atomic::dec_ptr(volatile void* dest) { |
|
405 |
dec_ptr((volatile intptr_t*)dest); |
|
406 |
} |
|
407 |
||
408 |
//------------- |
|
409 |
// Atomic::xchg |
|
410 |
//------------- |
|
411 |
// These methods force the value in memory to be replaced by the new value passed |
|
412 |
// in as argument. |
|
413 |
// |
|
414 |
// The value in memory is replaced by using a compare-and-swap instruction. The |
|
415 |
// instruction is retried as often as required. This makes sure that the new |
|
416 |
// value can be seen, at least for a very short period of time, by other CPUs. |
|
417 |
// |
|
418 |
// If we would use a normal "load(old value) store(new value)" sequence, |
|
419 |
// the new value could be lost unnoticed, due to a store(new value) from |
|
420 |
// another thread. |
|
421 |
// |
|
422 |
// The return value is the (unchanged) value from memory as it was when the |
|
423 |
// replacement succeeded. |
|
424 |
inline jint Atomic::xchg (jint xchg_val, volatile jint* dest) { |
|
425 |
unsigned int old; |
|
426 |
||
427 |
__asm__ __volatile__ ( |
|
428 |
" LLGF %[old],%[mem] \n\t" // get old value |
|
429 |
"0: CS %[old],%[upd],%[mem] \n\t" // try to xchg upd with mem |
|
430 |
" JNE 0b \n\t" // no success? -> retry |
|
431 |
//---< outputs >--- |
|
432 |
: [old] "=&d" (old) // write-only, prev value irrelevant |
|
433 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
434 |
//---< inputs >--- |
|
435 |
: [upd] "d" (xchg_val) // read-only, value to be written to memory |
|
436 |
//---< clobbered >--- |
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|
437 |
: "cc", "memory" |
42065 | 438 |
); |
439 |
||
440 |
return (jint)old; |
|
441 |
} |
|
442 |
||
443 |
inline intptr_t Atomic::xchg_ptr(intptr_t xchg_val, volatile intptr_t* dest) { |
|
444 |
unsigned long old; |
|
445 |
||
446 |
__asm__ __volatile__ ( |
|
447 |
" LG %[old],%[mem] \n\t" // get old value |
|
448 |
"0: CSG %[old],%[upd],%[mem] \n\t" // try to xchg upd with mem |
|
449 |
" JNE 0b \n\t" // no success? -> retry |
|
450 |
//---< outputs >--- |
|
451 |
: [old] "=&d" (old) // write-only, init from memory |
|
452 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically |
|
453 |
//---< inputs >--- |
|
454 |
: [upd] "d" (xchg_val) // read-only, value to be written to memory |
|
455 |
//---< clobbered >--- |
|
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|
456 |
: "cc", "memory" |
42065 | 457 |
); |
458 |
||
459 |
return (intptr_t)old; |
|
460 |
} |
|
461 |
||
462 |
inline void *Atomic::xchg_ptr(void *exchange_value, volatile void *dest) { |
|
463 |
return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest); |
|
464 |
} |
|
465 |
||
466 |
//---------------- |
|
467 |
// Atomic::cmpxchg |
|
468 |
//---------------- |
|
469 |
// These methods compare the value in memory with a given compare value. |
|
470 |
// If both values compare equal, the value in memory is replaced with |
|
471 |
// the exchange value. |
|
472 |
// |
|
473 |
// The value in memory is compared and replaced by using a compare-and-swap |
|
474 |
// instruction. The instruction is NOT retried (one shot only). |
|
475 |
// |
|
476 |
// The return value is the (unchanged) value from memory as it was when the |
|
477 |
// compare-and-swap instruction completed. A successful exchange operation |
|
478 |
// is indicated by (return value == compare_value). If unsuccessful, a new |
|
479 |
// exchange value can be calculated based on the return value which is the |
|
480 |
// latest contents of the memory location. |
|
481 |
// |
|
482 |
// Inspecting the return value is the only way for the caller to determine |
|
483 |
// if the compare-and-swap instruction was successful: |
|
484 |
// - If return value and compare value compare equal, the compare-and-swap |
|
485 |
// instruction was successful and the value in memory was replaced by the |
|
486 |
// exchange value. |
|
487 |
// - If return value and compare value compare unequal, the compare-and-swap |
|
488 |
// instruction was not successful. The value in memory was left unchanged. |
|
489 |
// |
|
490 |
// The s390 processors always fence before and after the csg instructions. |
|
491 |
// Thus we ignore the memory ordering argument. The docu says: "A serialization |
|
492 |
// function is performed before the operand is fetched and again after the |
|
493 |
// operation is completed." |
|
494 |
||
46958
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parents:
46953
diff
changeset
|
495 |
// No direct support for cmpxchg of bytes; emulate using int. |
a13bd8c6b7a2
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|
496 |
template<> |
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8186166: Generalize Atomic::cmpxchg with templates
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diff
changeset
|
497 |
struct Atomic::PlatformCmpxchg<1> : Atomic::CmpxchgByteUsingInt {}; |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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diff
changeset
|
498 |
|
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
eosterlund
parents:
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diff
changeset
|
499 |
template<> |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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changeset
|
500 |
template<typename T> |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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diff
changeset
|
501 |
inline T Atomic::PlatformCmpxchg<4>::operator()(T xchg_val, |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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changeset
|
502 |
T volatile* dest, |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
eosterlund
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46953
diff
changeset
|
503 |
T cmp_val, |
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diff
changeset
|
504 |
cmpxchg_memory_order unused) const { |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
eosterlund
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changeset
|
505 |
STATIC_ASSERT(4 == sizeof(T)); |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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changeset
|
506 |
T old; |
42065 | 507 |
|
508 |
__asm__ __volatile__ ( |
|
509 |
" CS %[old],%[upd],%[mem] \n\t" // Try to xchg upd with mem. |
|
510 |
// outputs |
|
511 |
: [old] "=&d" (old) // Write-only, prev value irrelevant. |
|
512 |
, [mem] "+Q" (*dest) // Read/write, memory to be updated atomically. |
|
513 |
// inputs |
|
514 |
: [upd] "d" (xchg_val) |
|
515 |
, "0" (cmp_val) // Read-only, initial value for [old] (operand #0). |
|
516 |
// clobbered |
|
46953
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|
517 |
: "cc", "memory" |
42065 | 518 |
); |
519 |
||
46958
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changeset
|
520 |
return old; |
42065 | 521 |
} |
522 |
||
46958
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changeset
|
523 |
template<> |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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diff
changeset
|
524 |
template<typename T> |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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changeset
|
525 |
inline T Atomic::PlatformCmpxchg<8>::operator()(T xchg_val, |
a13bd8c6b7a2
8186166: Generalize Atomic::cmpxchg with templates
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changeset
|
526 |
T volatile* dest, |
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46953
diff
changeset
|
527 |
T cmp_val, |
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diff
changeset
|
528 |
cmpxchg_memory_order unused) const { |
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changeset
|
529 |
STATIC_ASSERT(8 == sizeof(T)); |
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changeset
|
530 |
T old; |
42065 | 531 |
|
532 |
__asm__ __volatile__ ( |
|
533 |
" CSG %[old],%[upd],%[mem] \n\t" // Try to xchg upd with mem. |
|
534 |
// outputs |
|
535 |
: [old] "=&d" (old) // Write-only, prev value irrelevant. |
|
536 |
, [mem] "+Q" (*dest) // Read/write, memory to be updated atomically. |
|
537 |
// inputs |
|
538 |
: [upd] "d" (xchg_val) |
|
539 |
, "0" (cmp_val) // Read-only, initial value for [old] (operand #0). |
|
540 |
// clobbered |
|
46953
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changeset
|
541 |
: "cc", "memory" |
42065 | 542 |
); |
543 |
||
46958
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|
544 |
return old; |
42065 | 545 |
} |
546 |
||
46523
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diff
changeset
|
547 |
inline jlong Atomic::load(const volatile jlong* src) { return *src; } |
42065 | 548 |
|
549 |
#endif // OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP |