src/hotspot/cpu/arm/assembler_arm.hpp
author erikj
Tue, 12 Sep 2017 19:03:39 +0200
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parent 42664 hotspot/src/cpu/arm/vm/assembler_arm.hpp@29142a56c193
child 49364 601146c66cad
permissions -rw-r--r--
8187443: Forest Consolidation: Move files to unified layout Reviewed-by: darcy, ihse
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/*
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 * Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_ARM_VM_ASSEMBLER_ARM_HPP
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#define CPU_ARM_VM_ASSEMBLER_ARM_HPP
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#include "utilities/macros.hpp"
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enum AsmCondition {
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  eq, ne, cs, cc, mi, pl, vs, vc,
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  hi, ls, ge, lt, gt, le, al, nv,
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  number_of_conditions,
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  // alternative names
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  hs = cs,
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  lo = cc
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};
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enum AsmShift {
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  lsl, lsr, asr, ror
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};
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#ifdef AARCH64
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enum AsmExtendOp {
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  ex_uxtb, ex_uxth, ex_uxtw, ex_uxtx,
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  ex_sxtb, ex_sxth, ex_sxtw, ex_sxtx,
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  ex_lsl = ex_uxtx
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};
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#endif
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enum AsmOffset {
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#ifdef AARCH64
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  basic_offset = 0b00,
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  pre_indexed  = 0b11,
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  post_indexed = 0b01
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#else
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  basic_offset = 1 << 24,
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  pre_indexed  = 1 << 24 | 1 << 21,
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  post_indexed = 0
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#endif
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};
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#ifndef AARCH64
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enum AsmWriteback {
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  no_writeback,
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  writeback
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};
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enum AsmOffsetOp {
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  sub_offset = 0,
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  add_offset = 1
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};
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#endif
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// ARM Addressing Modes 2 and 3 - Load and store
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class Address VALUE_OBJ_CLASS_SPEC {
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 private:
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  Register  _base;
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  Register  _index;
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  int       _disp;
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  AsmOffset _mode;
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  RelocationHolder   _rspec;
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  int       _shift_imm;
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  AsmExtendOp _extend;
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#else
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  AsmShift  _shift;
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  AsmOffsetOp _offset_op;
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  static inline int abs(int x) { return x < 0 ? -x : x; }
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  static inline int up (int x) { return x < 0 ?  0 : 1; }
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#endif
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#ifdef AARCH64
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  static const AsmExtendOp LSL = ex_lsl;
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#else
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  static const AsmShift LSL = lsl;
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#endif
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 public:
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  Address() : _base(noreg) {}
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  Address(Register rn, int offset = 0, AsmOffset mode = basic_offset) {
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    _base = rn;
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    _index = noreg;
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    _disp = offset;
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    _mode = mode;
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    _shift_imm = 0;
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#ifdef AARCH64
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    _extend = ex_lsl;
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#else
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    _shift = lsl;
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    _offset_op = add_offset;
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#endif
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  }
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#ifdef ASSERT
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  Address(Register rn, ByteSize offset, AsmOffset mode = basic_offset) {
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    _base = rn;
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    _index = noreg;
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    _disp = in_bytes(offset);
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    _mode = mode;
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    _shift_imm = 0;
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#ifdef AARCH64
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    _extend = ex_lsl;
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#else
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    _shift = lsl;
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    _offset_op = add_offset;
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#endif
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  }
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#endif
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#ifdef AARCH64
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  Address(Register rn, Register rm, AsmExtendOp extend = ex_lsl, int shift_imm = 0) {
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    assert ((extend == ex_uxtw) || (extend == ex_lsl) || (extend == ex_sxtw) || (extend == ex_sxtx), "invalid extend for address mode");
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    assert ((0 <= shift_imm) && (shift_imm <= 4), "shift amount is out of range");
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    _base = rn;
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    _index = rm;
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    _disp = 0;
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    _mode = basic_offset;
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    _extend = extend;
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    _shift_imm = shift_imm;
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  }
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#else
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  Address(Register rn, Register rm, AsmShift shift = lsl,
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          int shift_imm = 0, AsmOffset mode = basic_offset,
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          AsmOffsetOp offset_op = add_offset) {
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    _base = rn;
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    _index = rm;
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    _disp = 0;
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    _shift = shift;
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    _shift_imm = shift_imm;
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    _mode = mode;
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    _offset_op = offset_op;
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  }
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  Address(Register rn, RegisterOrConstant offset, AsmShift shift = lsl,
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   161
          int shift_imm = 0) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   162
    _base = rn;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   163
    if (offset.is_constant()) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   164
      _index = noreg;
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bobv
parents:
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   165
      {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   166
        int off = (int) offset.as_constant();
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bobv
parents:
diff changeset
   167
        if (shift_imm != 0) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   168
          assert(shift == lsl,"shift not yet encoded");
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bobv
parents:
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   169
          off =  off << shift_imm;
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bobv
parents:
diff changeset
   170
        }
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bobv
parents:
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   171
        _disp = off;
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bobv
parents:
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   172
      }
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bobv
parents:
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   173
      _shift = lsl;
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bobv
parents:
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   174
      _shift_imm = 0;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   175
    } else {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
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parents:
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   176
      _index = offset.as_register();
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   177
      _disp = 0;
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bobv
parents:
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   178
      _shift = shift;
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bobv
parents:
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   179
      _shift_imm = shift_imm;
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bobv
parents:
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   180
    }
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   181
    _mode = basic_offset;
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bobv
parents:
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   182
    _offset_op = add_offset;
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bobv
parents:
diff changeset
   183
  }
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bobv
parents:
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   184
#endif // AARCH64
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parents:
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   185
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
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   186
  // [base + index * wordSize]
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parents:
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   187
  static Address indexed_ptr(Register base, Register index) {
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parents:
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   188
    return Address(base, index, LSL, LogBytesPerWord);
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bobv
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   189
  }
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parents:
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   190
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   191
  // [base + index * BytesPerInt]
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bobv
parents:
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   192
  static Address indexed_32(Register base, Register index) {
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bobv
parents:
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   193
    return Address(base, index, LSL, LogBytesPerInt);
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bobv
parents:
diff changeset
   194
  }
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bobv
parents:
diff changeset
   195
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   196
  // [base + index * BytesPerHeapOop]
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bobv
parents:
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   197
  static Address indexed_oop(Register base, Register index) {
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bobv
parents:
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   198
    return Address(base, index, LSL, LogBytesPerHeapOop);
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bobv
parents:
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   199
  }
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bobv
parents:
diff changeset
   200
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   201
  Address plus_disp(int disp) const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   202
    assert((disp == 0) || (_index == noreg),"can't apply an offset to a register indexed address");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   203
    Address a = (*this);
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   204
    a._disp += disp;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   205
    return a;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   206
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   207
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   208
  Address rebase(Register new_base) const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   209
    Address a = (*this);
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   210
    a._base = new_base;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   211
    return a;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   212
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   213
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   214
#ifdef AARCH64
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bobv
parents:
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   215
  int encoding_simd() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
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   216
    assert(_index != SP, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   217
    assert(_disp == 0 || _mode == post_indexed,  "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   218
    assert(_index == noreg || _mode == basic_offset, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   219
    assert(_mode == basic_offset || _mode == post_indexed, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   220
    assert(_extend == ex_lsl, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   221
    int index;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   222
    if (_index == noreg) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   223
      if (_mode == post_indexed)
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   224
        index = 0b100 << 5 | 31;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   225
      else
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   226
        index = 0;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   227
    } else {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   228
      index = 0b100 << 5 | _index->encoding();
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   229
    }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   230
    return index << 16 | _base->encoding_with_sp() << 5;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   231
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   232
#else /* !AARCH64 */
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   233
  int encoding2() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   234
    assert(_mode == basic_offset || _base != PC, "unpredictable instruction");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   235
    if (_index == noreg) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   236
      assert(-4096 < _disp && _disp < 4096, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   237
      return _mode | up(_disp) << 23 | _base->encoding() << 16 | abs(_disp);
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   238
    } else {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   239
      assert(_index != PC && (_mode == basic_offset || _index != _base), "unpredictable instruction");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   240
      assert(_disp == 0 && (_shift_imm >> 5) == 0, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   241
      return 1 << 25 | _offset_op << 23 | _mode | _base->encoding() << 16 |
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   242
             _shift_imm << 7 | _shift << 5 | _index->encoding();
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   243
    }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   244
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   245
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   246
  int encoding3() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   247
    assert(_mode == basic_offset || _base != PC, "unpredictable instruction");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   248
    if (_index == noreg) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   249
      assert(-256 < _disp && _disp < 256, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   250
      return _mode | up(_disp) << 23 | 1 << 22 | _base->encoding() << 16 |
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   251
             (abs(_disp) & 0xf0) << 4 | abs(_disp) & 0x0f;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   252
    } else {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   253
      assert(_index != PC && (_mode == basic_offset || _index != _base), "unpredictable instruction");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   254
      assert(_disp == 0 && _shift == lsl && _shift_imm == 0, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   255
      return _mode | _offset_op << 23 | _base->encoding() << 16 | _index->encoding();
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   256
    }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   257
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   258
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   259
  int encoding_ex() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   260
    assert(_index == noreg && _disp == 0 && _mode == basic_offset &&
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   261
           _base != PC, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   262
    return _base->encoding() << 16;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   263
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   264
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   265
  int encoding_vfp() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   266
    assert(_index == noreg && _mode == basic_offset, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   267
    assert(-1024 < _disp && _disp < 1024 && (_disp & 3) == 0, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   268
    return _base->encoding() << 16 | up(_disp) << 23 | abs(_disp) >> 2;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   269
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   270
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   271
  int encoding_simd() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   272
    assert(_base != PC, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   273
    assert(_index != PC && _index != SP, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   274
    assert(_disp == 0, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   275
    assert(_shift == 0, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   276
    assert(_index == noreg || _mode == basic_offset, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   277
    assert(_mode == basic_offset || _mode == post_indexed, "encoding constraint");
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   278
    int index;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   279
    if (_index == noreg) {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   280
      if (_mode == post_indexed)
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   281
        index = 13;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   282
      else
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   283
        index = 15;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   284
    } else {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   285
      index = _index->encoding();
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   286
    }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   287
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   288
    return _base->encoding() << 16 | index;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   289
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   290
#endif // !AARCH64
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   291
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   292
  Register base() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   293
    return _base;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   294
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   295
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   296
  Register index() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   297
    return _index;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   298
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   299
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   300
  int disp() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   301
    return _disp;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   302
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   303
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   304
  AsmOffset mode() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   305
    return _mode;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   306
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   307
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   308
  int shift_imm() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   309
    return _shift_imm;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   310
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   311
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   312
#ifdef AARCH64
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   313
  AsmExtendOp extend() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   314
    return _extend;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   315
  }
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   316
#else
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   317
  AsmShift shift() const {
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
parents:
diff changeset
   318
    return _shift;
29142a56c193 8168503: JEP 297: Unified arm32/arm64 Port
bobv
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  }
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  AsmOffsetOp offset_op() const {
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    return _offset_op;
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  }
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#endif
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  bool uses(Register reg) const { return _base == reg || _index == reg; }
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  const relocInfo::relocType rtype() { return _rspec.type(); }
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  const RelocationHolder&    rspec() { return _rspec; }
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  // Convert the raw encoding form into the form expected by the
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  // constructor for Address.
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  static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
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};
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#ifdef COMPILER2
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class VFP VALUE_OBJ_CLASS_SPEC {
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  // Helper classes to detect whether a floating point constant can be
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  // encoded in a fconstd or fconsts instruction
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  // The conversion from the imm8, 8 bit constant, to the floating
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  // point value encoding is done with either:
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  // for single precision: imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5):imm8<5:0>:Zeros(19)
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  // or
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  // for double precision: imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8):imm8<5:0>:Zeros(48)
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 private:
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  class fpnum {
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   public:
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    virtual unsigned int f_hi4() const = 0;
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    virtual bool f_lo_is_null() const = 0;
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    virtual int e() const = 0;
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    virtual unsigned int s() const = 0;
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    inline bool can_be_imm8() const { return e() >= -3 && e() <= 4 && f_lo_is_null(); }
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    inline unsigned char imm8() const { int v = (s() << 7) | (((e() - 1) & 0x7) << 4) | f_hi4(); assert((v >> 8) == 0, "overflow"); return v; }
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  };
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 public:
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  class float_num : public fpnum {
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   public:
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    float_num(float v) {
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      _num.val = v;
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    }
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    virtual unsigned int f_hi4() const { return (_num.bits << 9) >> (19+9); }
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    virtual bool f_lo_is_null() const { return (_num.bits & ((1 << 19) - 1)) == 0; }
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    virtual int e() const { return ((_num.bits << 1) >> (23+1)) - 127; }
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    virtual unsigned int s() const { return _num.bits >> 31; }
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   private:
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    union {
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      float val;
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      unsigned int bits;
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    } _num;
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  };
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  class double_num : public fpnum {
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   public:
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    double_num(double v) {
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      _num.val = v;
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    }
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    virtual unsigned int f_hi4() const { return (_num.bits << 12) >> (48+12); }
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    virtual bool f_lo_is_null() const { return (_num.bits & ((1LL << 48) - 1)) == 0; }
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    virtual int e() const { return ((_num.bits << 1) >> (52+1)) - 1023; }
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    virtual unsigned int s() const { return _num.bits >> 63; }
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   private:
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    union {
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      double val;
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      unsigned long long bits;
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    } _num;
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  };
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};
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#endif
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#ifdef AARCH64
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#include "assembler_arm_64.hpp"
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#else
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#include "assembler_arm_32.hpp"
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#endif
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#endif // CPU_ARM_VM_ASSEMBLER_ARM_HPP