hotspot/src/cpu/x86/vm/vm_version_x86_64.cpp
author never
Wed, 27 Aug 2008 00:21:55 -0700
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5108146: Merge i486 and amd64 cpu directories 6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
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/*
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 * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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 * CA 95054 USA or visit www.sun.com if you need additional information or
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 * have any questions.
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 *
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 */
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# include "incls/_precompiled.incl"
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# include "incls/_vm_version_x86_64.cpp.incl"
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_stepping;
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int VM_Version::_cpuFeatures;
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const char*           VM_Version::_features_str = "";
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VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
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static BufferBlob* stub_blob;
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static const int stub_size = 300;
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extern "C" {
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  typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_getPsrInfo() {
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    Label std_cpuid1, ext_cpuid1, ext_cpuid5, done;
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    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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#   define __ _masm->
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    address start = __ pc();
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    //
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    // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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    //
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    // rcx and rdx are first and second argument registers on windows
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    __ push(rbp);
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    __ mov(rbp, c_rarg0); // cpuid_info address
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    __ push(rbx);
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    __ push(rsi);
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    //
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    // we have a chip which supports the "cpuid" instruction
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    //
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    __ xorl(rax, rax);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    __ cmpl(rax, 3);     // Is cpuid(0x4) supported?
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    __ jccb(Assembler::belowEqual, std_cpuid1);
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    //
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    // cpuid(0x4) Deterministic cache params
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    //
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    __ movl(rax, 4);
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    __ xorl(rcx, rcx);   // L1 cache
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    __ cpuid();
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    __ push(rax);
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    __ andl(rax, 0x1f);  // Determine if valid cache parameters used
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    __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid1);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Standard cpuid(0x1)
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    //
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    __ bind(std_cpuid1);
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    __ movl(rax, 1);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    __ movl(rax, 0x80000000);
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    __ cpuid();
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    __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
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    __ jcc(Assembler::belowEqual, done);
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    __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid1);
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    __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid5);
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    //
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    // Extended cpuid(0x80000008)
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    //
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    __ movl(rax, 0x80000008);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Extended cpuid(0x80000005)
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    //
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    __ bind(ext_cpuid5);
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    __ movl(rax, 0x80000005);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Extended cpuid(0x80000001)
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    //
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    __ bind(ext_cpuid1);
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    __ movl(rax, 0x80000001);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // return
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    //
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    __ bind(done);
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    __ pop(rsi);
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    __ pop(rbx);
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    __ pop(rbp);
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    __ ret(0);
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#   undef __
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    return start;
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  };
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};
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void VM_Version::get_processor_features() {
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  _logical_processors_per_package = 1;
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  // Get raw processor info
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  getPsrInfo_stub(&_cpuid_info);
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  assert_is_initialized();
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  _cpu = extended_cpu_family();
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  _model = extended_cpu_model();
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  _stepping = cpu_stepping();
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  _cpuFeatures = feature_flags();
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  // Logical processors are only available on P4s and above,
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  // and only if hyperthreading is available.
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  _logical_processors_per_package = logical_processor_count();
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  _supports_cx8    = supports_cmpxchg8();
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  // OS should support SSE for x64 and hardware should support at least SSE2.
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  if (!VM_Version::supports_sse2()) {
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    vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
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  }
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  if (UseSSE < 4)
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    _cpuFeatures &= ~CPU_SSE4;
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  if (UseSSE < 3) {
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    _cpuFeatures &= ~CPU_SSE3;
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    _cpuFeatures &= ~CPU_SSSE3;
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    _cpuFeatures &= ~CPU_SSE4A;
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  }
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  if (UseSSE < 2)
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    _cpuFeatures &= ~CPU_SSE2;
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  if (UseSSE < 1)
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    _cpuFeatures &= ~CPU_SSE;
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   200
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  if (logical_processors_per_package() == 1) {
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    // HT processor could be installed on a system which doesn't support HT.
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    _cpuFeatures &= ~CPU_HT;
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  }
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  char buf[256];
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  jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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               cores_per_cpu(), threads_per_core(),
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               cpu_family(), _model, _stepping,
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               (supports_cmov() ? ", cmov" : ""),
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               (supports_cmpxchg8() ? ", cx8" : ""),
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               (supports_fxsr() ? ", fxsr" : ""),
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               (supports_mmx()  ? ", mmx"  : ""),
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               (supports_sse()  ? ", sse"  : ""),
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               (supports_sse2() ? ", sse2" : ""),
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               (supports_sse3() ? ", sse3" : ""),
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               (supports_ssse3()? ", ssse3": ""),
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               (supports_sse4() ? ", sse4" : ""),
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               (supports_mmx_ext() ? ", mmxext" : ""),
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               (supports_3dnow()   ? ", 3dnow"  : ""),
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               (supports_3dnow2()  ? ", 3dnowext" : ""),
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               (supports_sse4a()   ? ", sse4a": ""),
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               (supports_ht() ? ", ht": ""));
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  _features_str = strdup(buf);
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  // UseSSE is set to the smaller of what hardware supports and what
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  // the command line requires.  I.e., you cannot set UseSSE to 2 on
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  // older Pentiums which do not support it.
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  if( UseSSE > 4 ) UseSSE=4;
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  if( UseSSE < 0 ) UseSSE=0;
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  if( !supports_sse4() ) // Drop to 3 if no SSE4 support
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    UseSSE = MIN2((intx)3,UseSSE);
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  if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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    UseSSE = MIN2((intx)2,UseSSE);
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   235
  if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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    UseSSE = MIN2((intx)1,UseSSE);
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  if( !supports_sse () ) // Drop to 0 if no SSE  support
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    UseSSE = 0;
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  // On new cpus instructions which update whole XMM register should be used
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  // to prevent partial register stall due to dependencies on high half.
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  //
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  // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
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  // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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  // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
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  // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
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  if( is_amd() ) { // AMD cpus specific settings
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    if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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      // Use it on all AMD cpus starting from Opteron (don't need
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      // a cpu check since only Opteron and new cpus support 64-bits mode).
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      UseAddressNop = true;
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    }
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    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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   255
      if( supports_sse4a() ) {
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        UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
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      } else {
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        UseXmmLoadAndClearUpper = false;
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      }
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    }
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    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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      if( supports_sse4a() ) {
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        UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
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      } else {
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        UseXmmRegToRegMoveAll = false;
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      }
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    }
244
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    if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
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      if( supports_sse4a() ) {
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        UseXmmI2F = true;
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      } else {
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        UseXmmI2F = false;
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      }
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    }
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    if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
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      if( supports_sse4a() ) {
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        UseXmmI2D = true;
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      } else {
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        UseXmmI2D = false;
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      }
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    }
1
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  }
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  if( is_intel() ) { // Intel cpus specific settings
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    if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
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      UseStoreImmI16 = false; // don't use it on Intel cpus
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    }
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    if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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      // Use it on all Intel cpus starting from PentiumPro
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      // (don't need a cpu check since only new cpus support 64-bits mode).
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      UseAddressNop = true;
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    }
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   293
    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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      UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
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   295
    }
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   296
    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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   297
      if( supports_sse3() ) {
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        UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
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   299
      } else {
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        UseXmmRegToRegMoveAll = false;
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      }
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    }
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   303
    if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
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   304
#ifdef COMPILER2
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   305
      if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
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   306
        // For new Intel cpus do the next optimization:
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        // don't align the beginning of a loop if there are enough instructions
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        // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
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        // in current fetch line (OptoLoopAlignment) or the padding
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        // is big (> MaxLoopPad).
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        // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
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        // generated NOP instructions. 11 is the largest size of one
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        // address NOP instruction '0F 1F' (see Assembler::nop(i)).
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        MaxLoopPad = 11;
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   315
      }
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#endif // COMPILER2
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    }
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  }
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   319
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  assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
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   321
  assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
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   322
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  // set valid Prefetch instruction
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   324
  if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
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   325
  if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
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   326
  if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
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   327
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   328
  if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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   329
  if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
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   330
  if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
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   331
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  // Allocation prefetch settings
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   333
  intx cache_line_size = L1_data_cache_line_size();
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   334
  if( cache_line_size > AllocatePrefetchStepSize )
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   335
    AllocatePrefetchStepSize = cache_line_size;
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   336
  if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
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   337
    AllocatePrefetchLines = 3; // Optimistic value
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   338
  assert(AllocatePrefetchLines > 0, "invalid value");
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   339
  if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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   340
    AllocatePrefetchLines = 1; // Conservative value
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   341
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   342
  AllocatePrefetchDistance = allocate_prefetch_distance();
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   343
  AllocatePrefetchStyle    = allocate_prefetch_style();
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   344
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   345
  if( AllocatePrefetchStyle == 2 && is_intel() &&
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   346
      cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
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   347
    AllocatePrefetchDistance = 384;
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   348
  }
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   349
  assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
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   350
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  // Prefetch settings
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   352
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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   353
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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   354
  PrefetchFieldsAhead         = prefetch_fields_ahead();
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   355
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   356
#ifndef PRODUCT
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   357
  if (PrintMiscellaneous && Verbose) {
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   358
    tty->print_cr("Logical CPUs per package: %u",
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   359
                  logical_processors_per_package());
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   360
    tty->print_cr("UseSSE=%d",UseSSE);
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   361
    tty->print("Allocation: ");
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   362
    if (AllocatePrefetchStyle <= 0) {
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   363
      tty->print_cr("no prefetching");
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   364
    } else {
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   365
      if (AllocatePrefetchInstr == 0) {
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   366
        tty->print("PREFETCHNTA");
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   367
      } else if (AllocatePrefetchInstr == 1) {
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   368
        tty->print("PREFETCHT0");
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   369
      } else if (AllocatePrefetchInstr == 2) {
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   370
        tty->print("PREFETCHT2");
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   371
      } else if (AllocatePrefetchInstr == 3) {
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   372
        tty->print("PREFETCHW");
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   373
      }
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   374
      if (AllocatePrefetchLines > 1) {
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        tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
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      } else {
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   377
        tty->print_cr(" %d, one line", AllocatePrefetchDistance);
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   378
      }
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   379
    }
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   380
    if (PrefetchCopyIntervalInBytes > 0) {
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   381
      tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
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   382
    }
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   383
    if (PrefetchScanIntervalInBytes > 0) {
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   384
      tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
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   385
    }
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   386
    if (PrefetchFieldsAhead > 0) {
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   387
      tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
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   388
    }
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   389
  }
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#endif // !PRODUCT
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}
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   392
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   393
void VM_Version::initialize() {
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   394
  ResourceMark rm;
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  // Making this stub must be FIRST use of assembler
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   396
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   397
  stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
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   398
  if (stub_blob == NULL) {
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   399
    vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
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   400
  }
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   401
  CodeBuffer c(stub_blob->instructions_begin(),
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   402
               stub_blob->instructions_size());
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   403
  VM_Version_StubGenerator g(&c);
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  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
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                                   g.generate_getPsrInfo());
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   406
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   407
  get_processor_features();
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}