author | stefank |
Tue, 23 Nov 2010 13:22:55 -0800 | |
changeset 7397 | 5b173b4ca846 |
parent 5547 | f4b087cbb361 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
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* Copyright 2007, 2009 Red Hat, Inc. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP |
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#define CPU_ZERO_VM_ICACHE_ZERO_HPP |
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// Interface for updating the instruction cache. Whenever the VM |
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// modifies code, part of the processor instruction cache potentially |
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// has to be flushed. This implementation is empty: Zero never deals |
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// with code, and LLVM handles cache flushing for Shark. |
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class ICache : public AbstractICache { |
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public: |
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static void initialize() {} |
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static void invalidate_word(address addr) {} |
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static void invalidate_range(address start, int nbytes) {} |
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}; |
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#endif // CPU_ZERO_VM_ICACHE_ZERO_HPP |