hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp
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/*
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 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_X86_VM_C1_DEFS_X86_HPP
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#define CPU_X86_VM_C1_DEFS_X86_HPP
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// native word offsets from memory address (little endian)
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enum {
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  pd_lo_word_offset_in_bytes = 0,
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  pd_hi_word_offset_in_bytes = BytesPerWord
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};
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// explicit rounding operations are required to implement the strictFP mode
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enum {
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  pd_strict_fp_requires_explicit_rounding = true
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};
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// registers
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enum {
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  pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
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  pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of registers used during code emission
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  pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers,    // number of registers used during code emission
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#ifdef _LP64
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  #define UNALLOCATED 4    // rsp, rbp, r15, r10
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#else
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  #define UNALLOCATED 2    // rsp, rbp
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#endif // LP64
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  pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED,  // number of registers killed by calls
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  pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map,  // number of registers killed by calls
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  pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map,  // number of registers killed by calls
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  pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
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  pd_nof_fpu_regs_reg_alloc = 6,  // number of registers that are visible to register allocator
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  pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
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  pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
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  pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
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  pd_first_cpu_reg = 0,
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  pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
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  pd_first_byte_reg = 2,
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  pd_last_byte_reg = 5,
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  pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
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  pd_last_fpu_reg =  pd_first_fpu_reg + 7,
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  pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
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  pd_last_xmm_reg =  pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
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};
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// encoding of float value in debug info:
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enum {
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  pd_float_saved_as_double = true
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};
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#endif // CPU_X86_VM_C1_DEFS_X86_HPP