author | phh |
Sun, 01 Jan 2012 11:17:59 -0500 | |
changeset 11417 | 4ecc3253bec4 |
parent 10278 | e656a9aae10d |
child 11439 | 7af64224c70b |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
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#define CPU_X86_VM_VM_VERSION_X86_HPP |
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||
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#include "runtime/globals_extension.hpp" |
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#include "runtime/vm_version.hpp" |
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class VM_Version : public Abstract_VM_Version { |
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public: |
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// cpuid result register layouts. These are all unions of a uint32_t |
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// (in case anyone wants access to the register as a whole) and a bitfield. |
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||
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union StdCpuid1Eax { |
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uint32_t value; |
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struct { |
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uint32_t stepping : 4, |
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model : 4, |
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family : 4, |
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proc_type : 2, |
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: 2, |
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ext_model : 4, |
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ext_family : 8, |
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: 4; |
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} bits; |
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}; |
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||
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union StdCpuid1Ebx { // example, unused |
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uint32_t value; |
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struct { |
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uint32_t brand_id : 8, |
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clflush_size : 8, |
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threads_per_cpu : 8, |
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apic_id : 8; |
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} bits; |
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}; |
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||
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union StdCpuid1Ecx { |
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uint32_t value; |
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struct { |
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uint32_t sse3 : 1, |
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: 2, |
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monitor : 1, |
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: 1, |
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vmx : 1, |
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: 1, |
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est : 1, |
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: 1, |
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ssse3 : 1, |
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cid : 1, |
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: 2, |
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cmpxchg16: 1, |
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: 4, |
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dca : 1, |
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sse4_1 : 1, |
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sse4_2 : 1, |
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: 2, |
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popcnt : 1, |
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: 8; |
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} bits; |
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}; |
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||
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union StdCpuid1Edx { |
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uint32_t value; |
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struct { |
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uint32_t : 4, |
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tsc : 1, |
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: 3, |
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cmpxchg8 : 1, |
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: 6, |
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cmov : 1, |
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: 3, |
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clflush : 1, |
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: 3, |
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mmx : 1, |
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fxsr : 1, |
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sse : 1, |
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sse2 : 1, |
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: 1, |
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ht : 1, |
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: 3; |
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} bits; |
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}; |
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||
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union DcpCpuid4Eax { |
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uint32_t value; |
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struct { |
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uint32_t cache_type : 5, |
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: 21, |
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cores_per_cpu : 6; |
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} bits; |
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}; |
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||
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union DcpCpuid4Ebx { |
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uint32_t value; |
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struct { |
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uint32_t L1_line_size : 12, |
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partitions : 10, |
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associativity : 10; |
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} bits; |
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}; |
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union TplCpuidBEbx { |
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uint32_t value; |
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struct { |
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uint32_t logical_cpus : 16, |
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: 16; |
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} bits; |
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}; |
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union ExtCpuid1Ecx { |
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uint32_t value; |
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struct { |
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uint32_t LahfSahf : 1, |
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CmpLegacy : 1, |
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: 4, |
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lzcnt : 1, |
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sse4a : 1, |
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misalignsse : 1, |
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prefetchw : 1, |
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: 22; |
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} bits; |
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}; |
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||
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union ExtCpuid1Edx { |
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uint32_t value; |
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struct { |
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uint32_t : 22, |
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mmx_amd : 1, |
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mmx : 1, |
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fxsr : 1, |
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: 4, |
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long_mode : 1, |
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tdnow2 : 1, |
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tdnow : 1; |
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} bits; |
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}; |
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||
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union ExtCpuid5Ex { |
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uint32_t value; |
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struct { |
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uint32_t L1_line_size : 8, |
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L1_tag_lines : 8, |
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L1_assoc : 8, |
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L1_size : 8; |
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} bits; |
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}; |
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||
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union ExtCpuid8Ecx { |
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uint32_t value; |
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struct { |
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uint32_t cores_per_cpu : 8, |
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: 24; |
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} bits; |
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}; |
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||
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union ExtCpuid7Edx { |
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uint32_t value; |
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struct { |
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uint32_t : 8, |
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tsc_invariance : 1, |
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: 23; |
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} bits; |
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}; |
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protected: |
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static int _cpu; |
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static int _model; |
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static int _stepping; |
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static int _cpuFeatures; // features returned by the "cpuid" instruction |
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// 0 if this instruction is not available |
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static const char* _features_str; |
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enum { |
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CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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CPU_CMOV = (1 << 1), |
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CPU_FXSR = (1 << 2), |
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CPU_HT = (1 << 3), |
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CPU_MMX = (1 << 4), |
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CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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// may not necessarily support other 3dnow instructions |
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CPU_SSE = (1 << 6), |
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CPU_SSE2 = (1 << 7), |
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CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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CPU_SSSE3 = (1 << 9), |
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CPU_SSE4A = (1 << 10), |
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CPU_SSE4_1 = (1 << 11), |
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CPU_SSE4_2 = (1 << 12), |
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CPU_POPCNT = (1 << 13), |
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CPU_LZCNT = (1 << 14), |
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CPU_TSC = (1 << 15), |
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CPU_TSCINV = (1 << 16) |
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} cpuFeatureFlags; |
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|
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217 |
enum { |
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218 |
// AMD |
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CPU_FAMILY_AMD_11H = 17, |
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220 |
// Intel |
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CPU_FAMILY_INTEL_CORE = 6, |
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CPU_MODEL_NEHALEM_EP = 26, |
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CPU_MODEL_WESTMERE_EP = 44, |
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// CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value |
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CPU_MODEL_SANDYBRIDGE_EP = 45 |
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226 |
} cpuExtendedFamily; |
2111 | 227 |
|
228 |
// cpuid information block. All info derived from executing cpuid with |
|
229 |
// various function numbers is stored here. Intel and AMD info is |
|
230 |
// merged in this block: accessor methods disentangle it. |
|
231 |
// |
|
232 |
// The info block is laid out in subblocks of 4 dwords corresponding to |
|
233 |
// eax, ebx, ecx and edx, whether or not they contain anything useful. |
|
234 |
struct CpuidInfo { |
|
235 |
// cpuid function 0 |
|
236 |
uint32_t std_max_function; |
|
237 |
uint32_t std_vendor_name_0; |
|
238 |
uint32_t std_vendor_name_1; |
|
239 |
uint32_t std_vendor_name_2; |
|
240 |
||
241 |
// cpuid function 1 |
|
242 |
StdCpuid1Eax std_cpuid1_eax; |
|
243 |
StdCpuid1Ebx std_cpuid1_ebx; |
|
244 |
StdCpuid1Ecx std_cpuid1_ecx; |
|
245 |
StdCpuid1Edx std_cpuid1_edx; |
|
246 |
||
247 |
// cpuid function 4 (deterministic cache parameters) |
|
248 |
DcpCpuid4Eax dcp_cpuid4_eax; |
|
249 |
DcpCpuid4Ebx dcp_cpuid4_ebx; |
|
250 |
uint32_t dcp_cpuid4_ecx; // unused currently |
|
251 |
uint32_t dcp_cpuid4_edx; // unused currently |
|
252 |
||
5902 | 253 |
// cpuid function 0xB (processor topology) |
254 |
// ecx = 0 |
|
255 |
uint32_t tpl_cpuidB0_eax; |
|
256 |
TplCpuidBEbx tpl_cpuidB0_ebx; |
|
257 |
uint32_t tpl_cpuidB0_ecx; // unused currently |
|
258 |
uint32_t tpl_cpuidB0_edx; // unused currently |
|
259 |
||
260 |
// ecx = 1 |
|
261 |
uint32_t tpl_cpuidB1_eax; |
|
262 |
TplCpuidBEbx tpl_cpuidB1_ebx; |
|
263 |
uint32_t tpl_cpuidB1_ecx; // unused currently |
|
264 |
uint32_t tpl_cpuidB1_edx; // unused currently |
|
265 |
||
266 |
// ecx = 2 |
|
267 |
uint32_t tpl_cpuidB2_eax; |
|
268 |
TplCpuidBEbx tpl_cpuidB2_ebx; |
|
269 |
uint32_t tpl_cpuidB2_ecx; // unused currently |
|
270 |
uint32_t tpl_cpuidB2_edx; // unused currently |
|
271 |
||
2111 | 272 |
// cpuid function 0x80000000 // example, unused |
273 |
uint32_t ext_max_function; |
|
274 |
uint32_t ext_vendor_name_0; |
|
275 |
uint32_t ext_vendor_name_1; |
|
276 |
uint32_t ext_vendor_name_2; |
|
277 |
||
278 |
// cpuid function 0x80000001 |
|
279 |
uint32_t ext_cpuid1_eax; // reserved |
|
280 |
uint32_t ext_cpuid1_ebx; // reserved |
|
281 |
ExtCpuid1Ecx ext_cpuid1_ecx; |
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282 |
ExtCpuid1Edx ext_cpuid1_edx; |
|
283 |
||
284 |
// cpuid functions 0x80000002 thru 0x80000004: example, unused |
|
285 |
uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; |
|
286 |
uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; |
|
287 |
uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; |
|
288 |
||
289 |
// cpuid function 0x80000005 //AMD L1, Intel reserved |
|
290 |
uint32_t ext_cpuid5_eax; // unused currently |
|
291 |
uint32_t ext_cpuid5_ebx; // reserved |
|
292 |
ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) |
|
293 |
ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) |
|
294 |
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// cpuid function 0x80000007 |
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uint32_t ext_cpuid7_eax; // reserved |
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uint32_t ext_cpuid7_ebx; // reserved |
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uint32_t ext_cpuid7_ecx; // reserved |
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299 |
ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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300 |
|
2111 | 301 |
// cpuid function 0x80000008 |
302 |
uint32_t ext_cpuid8_eax; // unused currently |
|
303 |
uint32_t ext_cpuid8_ebx; // reserved |
|
304 |
ExtCpuid8Ecx ext_cpuid8_ecx; |
|
305 |
uint32_t ext_cpuid8_edx; // reserved |
|
306 |
}; |
|
307 |
||
308 |
// The actual cpuid info block |
|
309 |
static CpuidInfo _cpuid_info; |
|
310 |
||
311 |
// Extractors and predicates |
|
312 |
static uint32_t extended_cpu_family() { |
|
313 |
uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; |
|
314 |
result += _cpuid_info.std_cpuid1_eax.bits.ext_family; |
|
315 |
return result; |
|
316 |
} |
|
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317 |
|
2111 | 318 |
static uint32_t extended_cpu_model() { |
319 |
uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; |
|
320 |
result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; |
|
321 |
return result; |
|
322 |
} |
|
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323 |
|
2111 | 324 |
static uint32_t cpu_stepping() { |
325 |
uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; |
|
326 |
return result; |
|
327 |
} |
|
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328 |
|
2111 | 329 |
static uint logical_processor_count() { |
330 |
uint result = threads_per_core(); |
|
331 |
return result; |
|
332 |
} |
|
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333 |
|
2111 | 334 |
static uint32_t feature_flags() { |
335 |
uint32_t result = 0; |
|
336 |
if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) |
|
337 |
result |= CPU_CX8; |
|
338 |
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) |
|
339 |
result |= CPU_CMOV; |
|
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340 |
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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341 |
_cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
2111 | 342 |
result |= CPU_FXSR; |
343 |
// HT flag is set for multi-core processors also. |
|
344 |
if (threads_per_core() > 1) |
|
345 |
result |= CPU_HT; |
|
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346 |
if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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347 |
_cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
2111 | 348 |
result |= CPU_MMX; |
349 |
if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) |
|
350 |
result |= CPU_SSE; |
|
351 |
if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) |
|
352 |
result |= CPU_SSE2; |
|
353 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) |
|
354 |
result |= CPU_SSE3; |
|
355 |
if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) |
|
356 |
result |= CPU_SSSE3; |
|
357 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) |
|
358 |
result |= CPU_SSE4_1; |
|
359 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) |
|
360 |
result |= CPU_SSE4_2; |
|
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if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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362 |
result |= CPU_POPCNT; |
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363 |
if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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364 |
result |= CPU_TSC; |
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365 |
if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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366 |
result |= CPU_TSCINV; |
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|
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368 |
// AMD features. |
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369 |
if (is_amd()) { |
9135 | 370 |
if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
371 |
(_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) |
|
372 |
result |= CPU_3DNOW_PREFETCH; |
|
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if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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result |= CPU_LZCNT; |
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if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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result |= CPU_SSE4A; |
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377 |
} |
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378 |
|
2111 | 379 |
return result; |
380 |
} |
|
381 |
||
382 |
static void get_processor_features(); |
|
383 |
||
384 |
public: |
|
385 |
// Offsets for cpuid asm stub |
|
386 |
static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } |
|
387 |
static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } |
|
388 |
static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } |
|
389 |
static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
|
390 |
static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } |
|
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391 |
static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
2111 | 392 |
static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
5902 | 393 |
static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
394 |
static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } |
|
395 |
static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } |
|
2111 | 396 |
|
397 |
// Initialization |
|
398 |
static void initialize(); |
|
399 |
||
400 |
// Asserts |
|
401 |
static void assert_is_initialized() { |
|
402 |
assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); |
|
403 |
} |
|
404 |
||
405 |
// |
|
406 |
// Processor family: |
|
407 |
// 3 - 386 |
|
408 |
// 4 - 486 |
|
409 |
// 5 - Pentium |
|
410 |
// 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, |
|
411 |
// Pentium M, Core Solo, Core Duo, Core2 Duo |
|
412 |
// family 6 model: 9, 13, 14, 15 |
|
413 |
// 0x0f - Pentium 4, Opteron |
|
414 |
// |
|
415 |
// Note: The cpu family should be used to select between |
|
416 |
// instruction sequences which are valid on all Intel |
|
417 |
// processors. Use the feature test functions below to |
|
418 |
// determine whether a particular instruction is supported. |
|
419 |
// |
|
420 |
static int cpu_family() { return _cpu;} |
|
421 |
static bool is_P6() { return cpu_family() >= 6; } |
|
422 |
static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' |
|
423 |
static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' |
|
424 |
||
5927 | 425 |
static bool supports_processor_topology() { |
426 |
return (_cpuid_info.std_max_function >= 0xB) && |
|
427 |
// eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. |
|
428 |
// Some cpus have max cpuid >= 0xB but do not support processor topology. |
|
429 |
((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
|
430 |
} |
|
431 |
||
2111 | 432 |
static uint cores_per_cpu() { |
433 |
uint result = 1; |
|
434 |
if (is_intel()) { |
|
5927 | 435 |
if (supports_processor_topology()) { |
5902 | 436 |
result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
437 |
_cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
|
438 |
} else { |
|
439 |
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); |
|
440 |
} |
|
2111 | 441 |
} else if (is_amd()) { |
442 |
result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); |
|
443 |
} |
|
444 |
return result; |
|
445 |
} |
|
446 |
||
447 |
static uint threads_per_core() { |
|
448 |
uint result = 1; |
|
5927 | 449 |
if (is_intel() && supports_processor_topology()) { |
5902 | 450 |
result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
451 |
} else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { |
|
2111 | 452 |
result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
453 |
cores_per_cpu(); |
|
454 |
} |
|
455 |
return result; |
|
456 |
} |
|
457 |
||
10267 | 458 |
static intx prefetch_data_size() { |
2111 | 459 |
intx result = 0; |
460 |
if (is_intel()) { |
|
461 |
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); |
|
462 |
} else if (is_amd()) { |
|
463 |
result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; |
|
464 |
} |
|
465 |
if (result < 32) // not defined ? |
|
466 |
result = 32; // 32 bytes by default on x86 and other x64 |
|
467 |
return result; |
|
468 |
} |
|
469 |
||
470 |
// |
|
471 |
// Feature identification |
|
472 |
// |
|
473 |
static bool supports_cpuid() { return _cpuFeatures != 0; } |
|
474 |
static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } |
|
475 |
static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } |
|
476 |
static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } |
|
477 |
static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } |
|
478 |
static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } |
|
479 |
static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } |
|
480 |
static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } |
|
481 |
static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } |
|
482 |
static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } |
|
483 |
static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } |
|
484 |
static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } |
|
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485 |
static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
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486 |
static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
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487 |
|
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|
488 |
// Intel features |
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|
489 |
static bool is_intel_family_core() { return is_intel() && |
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|
490 |
extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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|
491 |
|
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|
492 |
static bool is_intel_tsc_synched_at_init() { |
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|
493 |
if (is_intel_family_core()) { |
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|
494 |
uint32_t ext_model = extended_cpu_model(); |
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495 |
if (ext_model == CPU_MODEL_NEHALEM_EP || |
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|
496 |
ext_model == CPU_MODEL_WESTMERE_EP || |
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|
497 |
// TODO ext_model == CPU_MODEL_IVYBRIDGE_EP || |
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|
498 |
ext_model == CPU_MODEL_SANDYBRIDGE_EP) { |
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|
499 |
// 2-socket invtsc support. EX versions with 4 sockets are not |
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|
500 |
// guaranteed to synchronize tscs at initialization via a double |
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|
501 |
// handshake. The tscs can be explicitly set in software. Code |
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|
502 |
// that uses tsc values must be prepared for them to arbitrarily |
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|
503 |
// jump backward or forward. |
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|
504 |
return true; |
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|
505 |
} |
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|
506 |
} |
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|
507 |
return false; |
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|
508 |
} |
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|
509 |
|
2111 | 510 |
// AMD features |
9135 | 511 |
static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
2111 | 512 |
static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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513 |
static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
2111 | 514 |
static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
515 |
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516 |
static bool is_amd_Barcelona() { return is_amd() && |
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517 |
extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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|
518 |
|
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519 |
// Intel and AMD newer cores support fast timestamps well |
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520 |
static bool supports_tscinv_bit() { |
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521 |
return (_cpuFeatures & CPU_TSCINV) != 0; |
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522 |
} |
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523 |
static bool supports_tscinv() { |
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524 |
return supports_tscinv_bit() && |
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525 |
( (is_amd() && !is_amd_Barcelona()) || |
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526 |
is_intel_tsc_synched_at_init() ); |
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527 |
} |
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528 |
|
7115
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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529 |
// Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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531 |
supports_sse3() && _model != 0x1C; } |
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532 |
|
2111 | 533 |
static bool supports_compare_and_exchange() { return true; } |
534 |
||
535 |
static const char* cpu_features() { return _features_str; } |
|
536 |
||
537 |
static intx allocate_prefetch_distance() { |
|
538 |
// This method should be called before allocate_prefetch_style(). |
|
539 |
// |
|
540 |
// Hardware prefetching (distance/size in bytes): |
|
541 |
// Pentium 3 - 64 / 32 |
|
542 |
// Pentium 4 - 256 / 128 |
|
543 |
// Athlon - 64 / 32 ???? |
|
544 |
// Opteron - 128 / 64 only when 2 sequential cache lines accessed |
|
545 |
// Core - 128 / 64 |
|
546 |
// |
|
547 |
// Software prefetching (distance in bytes / instruction with best score): |
|
548 |
// Pentium 3 - 128 / prefetchnta |
|
549 |
// Pentium 4 - 512 / prefetchnta |
|
550 |
// Athlon - 128 / prefetchnta |
|
551 |
// Opteron - 256 / prefetchnta |
|
552 |
// Core - 256 / prefetchnta |
|
553 |
// It will be used only when AllocatePrefetchStyle > 0 |
|
554 |
||
555 |
intx count = AllocatePrefetchDistance; |
|
556 |
if (count < 0) { // default ? |
|
557 |
if (is_amd()) { // AMD |
|
558 |
if (supports_sse2()) |
|
559 |
count = 256; // Opteron |
|
560 |
else |
|
561 |
count = 128; // Athlon |
|
562 |
} else { // Intel |
|
563 |
if (supports_sse2()) |
|
564 |
if (cpu_family() == 6) { |
|
565 |
count = 256; // Pentium M, Core, Core2 |
|
566 |
} else { |
|
567 |
count = 512; // Pentium 4 |
|
568 |
} |
|
569 |
else |
|
570 |
count = 128; // Pentium 3 (and all other old CPUs) |
|
571 |
} |
|
572 |
} |
|
573 |
return count; |
|
574 |
} |
|
575 |
static intx allocate_prefetch_style() { |
|
576 |
assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); |
|
577 |
// Return 0 if AllocatePrefetchDistance was not defined. |
|
578 |
return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; |
|
579 |
} |
|
580 |
||
581 |
// Prefetch interval for gc copy/scan == 9 dcache lines. Derived from |
|
582 |
// 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. |
|
583 |
// Tested intervals from 128 to 2048 in increments of 64 == one cache line. |
|
584 |
// 256 bytes (4 dcache lines) was the nearest runner-up to 576. |
|
585 |
||
586 |
// gc copy/scan is disabled if prefetchw isn't supported, because |
|
587 |
// Prefetch::write emits an inlined prefetchw on Linux. |
|
588 |
// Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. |
|
589 |
// The used prefetcht0 instruction works for both amd64 and em64t. |
|
590 |
static intx prefetch_copy_interval_in_bytes() { |
|
591 |
intx interval = PrefetchCopyIntervalInBytes; |
|
592 |
return interval >= 0 ? interval : 576; |
|
593 |
} |
|
594 |
static intx prefetch_scan_interval_in_bytes() { |
|
595 |
intx interval = PrefetchScanIntervalInBytes; |
|
596 |
return interval >= 0 ? interval : 576; |
|
597 |
} |
|
598 |
static intx prefetch_fields_ahead() { |
|
599 |
intx count = PrefetchFieldsAhead; |
|
600 |
return count >= 0 ? count : 1; |
|
601 |
} |
|
602 |
}; |
|
7397 | 603 |
|
604 |
#endif // CPU_X86_VM_VM_VERSION_X86_HPP |