hotspot/src/cpu/aarch64/vm/icBuffer_aarch64.cpp
author fyang
Tue, 12 Apr 2016 11:53:44 +0800
changeset 38037 31c22b526d30
parent 30764 fec48bf5a827
permissions -rw-r--r--
8153713: aarch64: improve short array clearing using store pair Summary: aarch64: generate store pair instruction to clear short arrays Reviewed-by: aph
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/*
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 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "code/icBuffer.hpp"
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#include "gc/shared/collectedHeap.inline.hpp"
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#include "interpreter/bytecodes.hpp"
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#include "memory/resourceArea.hpp"
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#include "nativeInst_aarch64.hpp"
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#include "oops/oop.inline.hpp"
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int InlineCacheBuffer::ic_stub_code_size() {
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  return (MacroAssembler::far_branches() ? 6 : 4) * NativeInstruction::instruction_size;
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}
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#define __ masm->
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void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) {
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  ResourceMark rm;
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  CodeBuffer      code(code_begin, ic_stub_code_size());
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  MacroAssembler* masm            = new MacroAssembler(&code);
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  // note: even though the code contains an embedded value, we do not need reloc info
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  // because
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  // (1) the value is old (i.e., doesn't matter for scavenges)
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  // (2) these ICStubs are removed *before* a GC happens, so the roots disappear
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  // assert(cached_value == NULL || cached_oop->is_perm(), "must be perm oop");
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  address start = __ pc();
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  Label l;
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  __ ldr(rscratch2, l);
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  __ far_jump(ExternalAddress(entry_point));
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  __ align(wordSize);
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  __ bind(l);
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  __ emit_int64((int64_t)cached_value);
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  // Only need to invalidate the 1st two instructions - not the whole ic stub
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  ICache::invalidate_range(code_begin, InlineCacheBuffer::ic_stub_code_size());
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  assert(__ pc() - start == ic_stub_code_size(), "must be");
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}
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address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) {
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  NativeMovConstReg* move = nativeMovConstReg_at(code_begin);   // creation also verifies the object
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  NativeJump* jump = nativeJump_at(code_begin + 4);
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  return jump->jump_destination();
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}
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void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) {
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  // The word containing the cached value is at the end of this IC buffer
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  uintptr_t *p = (uintptr_t *)(code_begin + ic_stub_code_size() - wordSize);
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  void* o = (void*)*p;
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  return o;
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}