| author | goetz |
| Thu, 27 Feb 2014 20:40:24 +0100 | |
| changeset 22927 | 3064556d178d |
| parent 22879 | 177361c49b26 |
| child 23211 | 954e3a81da29 |
| permissions | -rw-r--r-- |
| 22861 | 1 |
// |
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// Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved. |
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// Copyright 2012, 2013 SAP AG. All rights reserved. |
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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// |
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// This code is free software; you can redistribute it and/or modify it |
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// under the terms of the GNU General Public License version 2 only, as |
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// published by the Free Software Foundation. |
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// |
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// This code is distributed in the hope that it will be useful, but WITHOUT |
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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// version 2 for more details (a copy is included in the LICENSE file that |
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// accompanied this code). |
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// |
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// You should have received a copy of the GNU General Public License version |
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// 2 along with this work; if not, write to the Free Software Foundation, |
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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// |
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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// or visit www.oracle.com if you need additional information or have any |
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// questions. |
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// |
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// |
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// |
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// PPC64 Architecture Description File |
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// |
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//----------REGISTER DEFINITION BLOCK------------------------------------------ |
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// This information is used by the matcher and the register allocator to |
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// describe individual registers and classes of registers within the target |
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// architecture. |
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register %{
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//----------Architecture Description Register Definitions---------------------- |
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// General Registers |
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// "reg_def" name (register save type, C convention save type, |
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// ideal register type, encoding); |
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// |
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// Register Save Types: |
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// |
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// NS = No-Save: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, & |
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// that they do not need to be saved at call sites. |
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// |
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// SOC = Save-On-Call: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, |
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// but that they must be saved at call sites. |
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// These are called "volatiles" on ppc. |
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// |
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// SOE = Save-On-Entry: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, but they do not need to be saved at call |
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// sites. |
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// These are called "nonvolatiles" on ppc. |
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// |
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// AS = Always-Save: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, & that they must be saved at call sites. |
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// |
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// Ideal Register Type is used to determine how to save & restore a |
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// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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// |
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// The encoding number is the actual bit-pattern placed into the opcodes. |
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// |
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// PPC64 register definitions, based on the 64-bit PowerPC ELF ABI |
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// Supplement Version 1.7 as of 2003-10-29. |
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// |
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// For each 64-bit register we must define two registers: the register |
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// itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', |
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// e.g. R3_H, which is needed by the allocator, but is not used |
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// for stores, loads, etc. |
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// ---------------------------- |
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// Integer/Long Registers |
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// ---------------------------- |
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// PPC64 has 32 64-bit integer registers. |
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// types: v = volatile, nv = non-volatile, s = system |
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reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs |
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reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); |
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reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP |
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reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); |
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reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC |
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reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); |
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reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret |
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reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); |
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reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 |
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reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); |
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reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 |
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reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); |
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reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 |
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reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); |
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reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 |
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reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); |
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reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 |
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reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); |
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reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 |
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reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); |
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reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 |
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reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); |
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reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch |
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reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); |
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reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch |
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reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); |
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reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id |
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reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); |
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reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv |
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reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); |
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reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv |
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reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); |
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reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv |
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reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); |
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reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv |
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reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); |
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reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv |
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reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); |
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reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv |
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reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); |
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reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv |
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reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); |
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reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv |
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reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); |
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reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv |
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reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); |
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reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv |
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reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); |
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reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv |
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reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); |
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reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv |
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reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); |
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reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv |
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reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); |
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reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv |
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reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); |
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reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv |
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reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); |
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reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv |
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reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); |
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reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv |
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reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); |
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reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv |
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reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); |
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// ---------------------------- |
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// Float/Double Registers |
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// ---------------------------- |
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// Double Registers |
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// The rules of ADL require that double registers be defined in pairs. |
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// Each pair must be two 32-bit values, but not necessarily a pair of |
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// single float registers. In each pair, ADLC-assigned register numbers |
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// must be adjacent, with the lower number even. Finally, when the |
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// CPU stores such a register pair to memory, the word associated with |
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// the lower ADLC-assigned number must be stored to the lower address. |
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// PPC64 has 32 64-bit floating-point registers. Each can store a single |
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// or double precision floating-point value. |
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// types: v = volatile, nv = non-volatile, s = system |
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reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch |
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reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); |
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reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret |
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reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); |
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reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 |
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reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); |
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reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 |
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reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); |
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reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 |
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reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); |
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reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 |
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reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); |
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reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 |
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reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); |
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reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 |
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reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); |
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reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 |
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reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); |
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reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 |
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reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); |
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reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 |
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reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); |
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reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 |
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reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); |
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reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 |
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reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); |
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reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 |
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reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); |
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reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv |
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reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); |
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reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv |
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reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); |
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reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv |
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reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); |
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reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv |
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reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); |
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reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv |
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reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); |
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reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv |
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reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); |
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reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv |
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reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); |
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reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv |
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reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); |
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reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv |
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reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); |
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reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv |
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reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); |
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reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv |
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reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); |
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reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv |
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reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); |
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reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv |
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reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); |
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reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv |
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reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); |
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reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv |
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reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); |
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reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv |
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reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); |
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reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv |
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reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); |
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reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv |
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reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); |
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// ---------------------------- |
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// Special Registers |
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// ---------------------------- |
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// Condition Codes Flag Registers |
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// PPC64 has 8 condition code "registers" which are all contained |
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// in the CR register. |
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// types: v = volatile, nv = non-volatile, s = system |
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reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v |
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reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v |
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reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv |
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reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv |
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reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv |
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reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v |
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reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v |
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reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v |
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// Special registers of PPC64 |
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reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v |
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reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v |
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reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v |
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reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v |
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reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v |
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reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v |
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// ---------------------------- |
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// Specify priority of register selection within phases of register |
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// allocation. Highest priority is first. A useful heuristic is to |
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// give registers a low priority when they are required by machine |
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// instructions, like EAX and EDX on I486, and choose no-save registers |
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// before save-on-call, & save-on-call before save-on-entry. Registers |
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// which participate in fixed calling sequences should come last. |
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// Registers which are used as pairs must fall on an even boundary. |
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// It's worth about 1% on SPEC geomean to get this right. |
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// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration |
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// in adGlobals_ppc64.hpp which defines the <register>_num values, e.g. |
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// R3_num. Therefore, R3_num may not be (and in reality is not) |
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// the same as R3->encoding()! Furthermore, we cannot make any |
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// assumptions on ordering, e.g. R3_num may be less than R2_num. |
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// Additionally, the function |
|
275 |
// static enum RC rc_class(OptoReg::Name reg ) |
|
276 |
// maps a given <register>_num value to its chunk type (except for flags) |
|
277 |
// and its current implementation relies on chunk0 and chunk1 having a |
|
278 |
// size of 64 each. |
|
279 |
||
280 |
// If you change this allocation class, please have a look at the |
|
281 |
// default values for the parameters RoundRobinIntegerRegIntervalStart |
|
282 |
// and RoundRobinFloatRegIntervalStart |
|
283 |
||
284 |
alloc_class chunk0 ( |
|
285 |
// Chunk0 contains *all* 64 integer registers halves. |
|
286 |
||
287 |
// "non-volatile" registers |
|
288 |
R14, R14_H, |
|
289 |
R15, R15_H, |
|
290 |
R17, R17_H, |
|
291 |
R18, R18_H, |
|
292 |
R19, R19_H, |
|
293 |
R20, R20_H, |
|
294 |
R21, R21_H, |
|
295 |
R22, R22_H, |
|
296 |
R23, R23_H, |
|
297 |
R24, R24_H, |
|
298 |
R25, R25_H, |
|
299 |
R26, R26_H, |
|
300 |
R27, R27_H, |
|
301 |
R28, R28_H, |
|
302 |
R29, R29_H, |
|
303 |
R30, R30_H, |
|
304 |
R31, R31_H, |
|
305 |
||
306 |
// scratch/special registers |
|
307 |
R11, R11_H, |
|
308 |
R12, R12_H, |
|
309 |
||
310 |
// argument registers |
|
311 |
R10, R10_H, |
|
312 |
R9, R9_H, |
|
313 |
R8, R8_H, |
|
314 |
R7, R7_H, |
|
315 |
R6, R6_H, |
|
316 |
R5, R5_H, |
|
317 |
R4, R4_H, |
|
318 |
R3, R3_H, |
|
319 |
||
320 |
// special registers, not available for allocation |
|
321 |
R16, R16_H, // R16_thread |
|
322 |
R13, R13_H, // system thread id |
|
323 |
R2, R2_H, // may be used for TOC |
|
324 |
R1, R1_H, // SP |
|
325 |
R0, R0_H // R0 (scratch) |
|
326 |
); |
|
327 |
||
328 |
// If you change this allocation class, please have a look at the |
|
329 |
// default values for the parameters RoundRobinIntegerRegIntervalStart |
|
330 |
// and RoundRobinFloatRegIntervalStart |
|
331 |
||
332 |
alloc_class chunk1 ( |
|
333 |
// Chunk1 contains *all* 64 floating-point registers halves. |
|
334 |
||
335 |
// scratch register |
|
336 |
F0, F0_H, |
|
337 |
||
338 |
// argument registers |
|
339 |
F13, F13_H, |
|
340 |
F12, F12_H, |
|
341 |
F11, F11_H, |
|
342 |
F10, F10_H, |
|
343 |
F9, F9_H, |
|
344 |
F8, F8_H, |
|
345 |
F7, F7_H, |
|
346 |
F6, F6_H, |
|
347 |
F5, F5_H, |
|
348 |
F4, F4_H, |
|
349 |
F3, F3_H, |
|
350 |
F2, F2_H, |
|
351 |
F1, F1_H, |
|
352 |
||
353 |
// non-volatile registers |
|
354 |
F14, F14_H, |
|
355 |
F15, F15_H, |
|
356 |
F16, F16_H, |
|
357 |
F17, F17_H, |
|
358 |
F18, F18_H, |
|
359 |
F19, F19_H, |
|
360 |
F20, F20_H, |
|
361 |
F21, F21_H, |
|
362 |
F22, F22_H, |
|
363 |
F23, F23_H, |
|
364 |
F24, F24_H, |
|
365 |
F25, F25_H, |
|
366 |
F26, F26_H, |
|
367 |
F27, F27_H, |
|
368 |
F28, F28_H, |
|
369 |
F29, F29_H, |
|
370 |
F30, F30_H, |
|
371 |
F31, F31_H |
|
372 |
); |
|
373 |
||
374 |
alloc_class chunk2 ( |
|
375 |
// Chunk2 contains *all* 8 condition code registers. |
|
376 |
||
377 |
CCR0, |
|
378 |
CCR1, |
|
379 |
CCR2, |
|
380 |
CCR3, |
|
381 |
CCR4, |
|
382 |
CCR5, |
|
383 |
CCR6, |
|
384 |
CCR7 |
|
385 |
); |
|
386 |
||
387 |
alloc_class chunk3 ( |
|
388 |
// special registers |
|
389 |
// These registers are not allocated, but used for nodes generated by postalloc expand. |
|
390 |
SR_XER, |
|
391 |
SR_LR, |
|
392 |
SR_CTR, |
|
393 |
SR_VRSAVE, |
|
394 |
SR_SPEFSCR, |
|
395 |
SR_PPR |
|
396 |
); |
|
397 |
||
398 |
//-------Architecture Description Register Classes----------------------- |
|
399 |
||
400 |
// Several register classes are automatically defined based upon |
|
401 |
// information in this architecture description. |
|
402 |
||
403 |
// 1) reg_class inline_cache_reg ( as defined in frame section ) |
|
404 |
// 2) reg_class compiler_method_oop_reg ( as defined in frame section ) |
|
405 |
// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) |
|
406 |
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) |
|
407 |
// |
|
408 |
||
409 |
// ---------------------------- |
|
410 |
// 32 Bit Register Classes |
|
411 |
// ---------------------------- |
|
412 |
||
413 |
// We specify registers twice, once as read/write, and once read-only. |
|
414 |
// We use the read-only registers for source operands. With this, we |
|
415 |
// can include preset read only registers in this class, as a hard-coded |
|
416 |
// '0'-register. (We used to simulate this on ppc.) |
|
417 |
||
418 |
// 32 bit registers that can be read and written i.e. these registers |
|
419 |
// can be dest (or src) of normal instructions. |
|
420 |
reg_class bits32_reg_rw( |
|
421 |
/*R0*/ // R0 |
|
422 |
/*R1*/ // SP |
|
423 |
R2, // TOC |
|
424 |
R3, |
|
425 |
R4, |
|
426 |
R5, |
|
427 |
R6, |
|
428 |
R7, |
|
429 |
R8, |
|
430 |
R9, |
|
431 |
R10, |
|
432 |
R11, |
|
433 |
R12, |
|
434 |
/*R13*/ // system thread id |
|
435 |
R14, |
|
436 |
R15, |
|
437 |
/*R16*/ // R16_thread |
|
438 |
R17, |
|
439 |
R18, |
|
440 |
R19, |
|
441 |
R20, |
|
442 |
R21, |
|
443 |
R22, |
|
444 |
R23, |
|
445 |
R24, |
|
446 |
R25, |
|
447 |
R26, |
|
448 |
R27, |
|
449 |
R28, |
|
450 |
/*R29*/ // global TOC |
|
451 |
/*R30*/ // Narrow Oop Base |
|
452 |
R31 |
|
453 |
); |
|
454 |
||
455 |
// 32 bit registers that can only be read i.e. these registers can |
|
456 |
// only be src of all instructions. |
|
457 |
reg_class bits32_reg_ro( |
|
458 |
/*R0*/ // R0 |
|
459 |
/*R1*/ // SP |
|
460 |
R2 // TOC |
|
461 |
R3, |
|
462 |
R4, |
|
463 |
R5, |
|
464 |
R6, |
|
465 |
R7, |
|
466 |
R8, |
|
467 |
R9, |
|
468 |
R10, |
|
469 |
R11, |
|
470 |
R12, |
|
471 |
/*R13*/ // system thread id |
|
472 |
R14, |
|
473 |
R15, |
|
474 |
/*R16*/ // R16_thread |
|
475 |
R17, |
|
476 |
R18, |
|
477 |
R19, |
|
478 |
R20, |
|
479 |
R21, |
|
480 |
R22, |
|
481 |
R23, |
|
482 |
R24, |
|
483 |
R25, |
|
484 |
R26, |
|
485 |
R27, |
|
486 |
R28, |
|
487 |
/*R29*/ |
|
488 |
/*R30*/ // Narrow Oop Base |
|
489 |
R31 |
|
490 |
); |
|
491 |
||
492 |
// Complement-required-in-pipeline operands for narrow oops. |
|
493 |
reg_class bits32_reg_ro_not_complement ( |
|
494 |
/*R0*/ // R0 |
|
495 |
R1, // SP |
|
496 |
R2, // TOC |
|
497 |
R3, |
|
498 |
R4, |
|
499 |
R5, |
|
500 |
R6, |
|
501 |
R7, |
|
502 |
R8, |
|
503 |
R9, |
|
504 |
R10, |
|
505 |
R11, |
|
506 |
R12, |
|
507 |
/*R13,*/ // system thread id |
|
508 |
R14, |
|
509 |
R15, |
|
510 |
R16, // R16_thread |
|
511 |
R17, |
|
512 |
R18, |
|
513 |
R19, |
|
514 |
R20, |
|
515 |
R21, |
|
516 |
R22, |
|
517 |
/*R23, |
|
518 |
R24, |
|
519 |
R25, |
|
520 |
R26, |
|
521 |
R27, |
|
522 |
R28,*/ |
|
523 |
/*R29,*/ // TODO: let allocator handle TOC!! |
|
524 |
/*R30,*/ |
|
525 |
R31 |
|
526 |
); |
|
527 |
||
528 |
// Complement-required-in-pipeline operands for narrow oops. |
|
529 |
// See 64-bit declaration. |
|
530 |
reg_class bits32_reg_ro_complement ( |
|
531 |
R23, |
|
532 |
R24, |
|
533 |
R25, |
|
534 |
R26, |
|
535 |
R27, |
|
536 |
R28 |
|
537 |
); |
|
538 |
||
539 |
reg_class rscratch1_bits32_reg(R11); |
|
540 |
reg_class rscratch2_bits32_reg(R12); |
|
541 |
reg_class rarg1_bits32_reg(R3); |
|
542 |
reg_class rarg2_bits32_reg(R4); |
|
543 |
reg_class rarg3_bits32_reg(R5); |
|
544 |
reg_class rarg4_bits32_reg(R6); |
|
545 |
||
546 |
// ---------------------------- |
|
547 |
// 64 Bit Register Classes |
|
548 |
// ---------------------------- |
|
549 |
// 64-bit build means 64-bit pointers means hi/lo pairs |
|
550 |
||
551 |
reg_class rscratch1_bits64_reg(R11_H, R11); |
|
552 |
reg_class rscratch2_bits64_reg(R12_H, R12); |
|
553 |
reg_class rarg1_bits64_reg(R3_H, R3); |
|
554 |
reg_class rarg2_bits64_reg(R4_H, R4); |
|
555 |
reg_class rarg3_bits64_reg(R5_H, R5); |
|
556 |
reg_class rarg4_bits64_reg(R6_H, R6); |
|
557 |
// Thread register, 'written' by tlsLoadP, see there. |
|
558 |
reg_class thread_bits64_reg(R16_H, R16); |
|
559 |
||
560 |
reg_class r19_bits64_reg(R19_H, R19); |
|
561 |
||
562 |
// 64 bit registers that can be read and written i.e. these registers |
|
563 |
// can be dest (or src) of normal instructions. |
|
564 |
reg_class bits64_reg_rw( |
|
565 |
/*R0_H, R0*/ // R0 |
|
566 |
/*R1_H, R1*/ // SP |
|
567 |
R2_H, R2, // TOC |
|
568 |
R3_H, R3, |
|
569 |
R4_H, R4, |
|
570 |
R5_H, R5, |
|
571 |
R6_H, R6, |
|
572 |
R7_H, R7, |
|
573 |
R8_H, R8, |
|
574 |
R9_H, R9, |
|
575 |
R10_H, R10, |
|
576 |
R11_H, R11, |
|
577 |
R12_H, R12, |
|
578 |
/*R13_H, R13*/ // system thread id |
|
579 |
R14_H, R14, |
|
580 |
R15_H, R15, |
|
581 |
/*R16_H, R16*/ // R16_thread |
|
582 |
R17_H, R17, |
|
583 |
R18_H, R18, |
|
584 |
R19_H, R19, |
|
585 |
R20_H, R20, |
|
586 |
R21_H, R21, |
|
587 |
R22_H, R22, |
|
588 |
R23_H, R23, |
|
589 |
R24_H, R24, |
|
590 |
R25_H, R25, |
|
591 |
R26_H, R26, |
|
592 |
R27_H, R27, |
|
593 |
R28_H, R28, |
|
594 |
/*R29_H, R29*/ |
|
595 |
/*R30_H, R30*/ |
|
596 |
R31_H, R31 |
|
597 |
); |
|
598 |
||
599 |
// 64 bit registers used excluding r2, r11 and r12 |
|
600 |
// Used to hold the TOC to avoid collisions with expanded LeafCall which uses |
|
601 |
// r2, r11 and r12 internally. |
|
602 |
reg_class bits64_reg_leaf_call( |
|
603 |
/*R0_H, R0*/ // R0 |
|
604 |
/*R1_H, R1*/ // SP |
|
605 |
/*R2_H, R2*/ // TOC |
|
606 |
R3_H, R3, |
|
607 |
R4_H, R4, |
|
608 |
R5_H, R5, |
|
609 |
R6_H, R6, |
|
610 |
R7_H, R7, |
|
611 |
R8_H, R8, |
|
612 |
R9_H, R9, |
|
613 |
R10_H, R10, |
|
614 |
/*R11_H, R11*/ |
|
615 |
/*R12_H, R12*/ |
|
616 |
/*R13_H, R13*/ // system thread id |
|
617 |
R14_H, R14, |
|
618 |
R15_H, R15, |
|
619 |
/*R16_H, R16*/ // R16_thread |
|
620 |
R17_H, R17, |
|
621 |
R18_H, R18, |
|
622 |
R19_H, R19, |
|
623 |
R20_H, R20, |
|
624 |
R21_H, R21, |
|
625 |
R22_H, R22, |
|
626 |
R23_H, R23, |
|
627 |
R24_H, R24, |
|
628 |
R25_H, R25, |
|
629 |
R26_H, R26, |
|
630 |
R27_H, R27, |
|
631 |
R28_H, R28, |
|
632 |
/*R29_H, R29*/ |
|
633 |
/*R30_H, R30*/ |
|
634 |
R31_H, R31 |
|
635 |
); |
|
636 |
||
637 |
// Used to hold the TOC to avoid collisions with expanded DynamicCall |
|
638 |
// which uses r19 as inline cache internally and expanded LeafCall which uses |
|
639 |
// r2, r11 and r12 internally. |
|
640 |
reg_class bits64_constant_table_base( |
|
641 |
/*R0_H, R0*/ // R0 |
|
642 |
/*R1_H, R1*/ // SP |
|
643 |
/*R2_H, R2*/ // TOC |
|
644 |
R3_H, R3, |
|
645 |
R4_H, R4, |
|
646 |
R5_H, R5, |
|
647 |
R6_H, R6, |
|
648 |
R7_H, R7, |
|
649 |
R8_H, R8, |
|
650 |
R9_H, R9, |
|
651 |
R10_H, R10, |
|
652 |
/*R11_H, R11*/ |
|
653 |
/*R12_H, R12*/ |
|
654 |
/*R13_H, R13*/ // system thread id |
|
655 |
R14_H, R14, |
|
656 |
R15_H, R15, |
|
657 |
/*R16_H, R16*/ // R16_thread |
|
658 |
R17_H, R17, |
|
659 |
R18_H, R18, |
|
660 |
/*R19_H, R19*/ |
|
661 |
R20_H, R20, |
|
662 |
R21_H, R21, |
|
663 |
R22_H, R22, |
|
664 |
R23_H, R23, |
|
665 |
R24_H, R24, |
|
666 |
R25_H, R25, |
|
667 |
R26_H, R26, |
|
668 |
R27_H, R27, |
|
669 |
R28_H, R28, |
|
670 |
/*R29_H, R29*/ |
|
671 |
/*R30_H, R30*/ |
|
672 |
R31_H, R31 |
|
673 |
); |
|
674 |
||
675 |
// 64 bit registers that can only be read i.e. these registers can |
|
676 |
// only be src of all instructions. |
|
677 |
reg_class bits64_reg_ro( |
|
678 |
/*R0_H, R0*/ // R0 |
|
679 |
R1_H, R1, |
|
680 |
R2_H, R2, // TOC |
|
681 |
R3_H, R3, |
|
682 |
R4_H, R4, |
|
683 |
R5_H, R5, |
|
684 |
R6_H, R6, |
|
685 |
R7_H, R7, |
|
686 |
R8_H, R8, |
|
687 |
R9_H, R9, |
|
688 |
R10_H, R10, |
|
689 |
R11_H, R11, |
|
690 |
R12_H, R12, |
|
691 |
/*R13_H, R13*/ // system thread id |
|
692 |
R14_H, R14, |
|
693 |
R15_H, R15, |
|
694 |
R16_H, R16, // R16_thread |
|
695 |
R17_H, R17, |
|
696 |
R18_H, R18, |
|
697 |
R19_H, R19, |
|
698 |
R20_H, R20, |
|
699 |
R21_H, R21, |
|
700 |
R22_H, R22, |
|
701 |
R23_H, R23, |
|
702 |
R24_H, R24, |
|
703 |
R25_H, R25, |
|
704 |
R26_H, R26, |
|
705 |
R27_H, R27, |
|
706 |
R28_H, R28, |
|
707 |
/*R29_H, R29*/ // TODO: let allocator handle TOC!! |
|
708 |
/*R30_H, R30,*/ |
|
709 |
R31_H, R31 |
|
710 |
); |
|
711 |
||
712 |
// Complement-required-in-pipeline operands. |
|
713 |
reg_class bits64_reg_ro_not_complement ( |
|
714 |
/*R0_H, R0*/ // R0 |
|
715 |
R1_H, R1, // SP |
|
716 |
R2_H, R2, // TOC |
|
717 |
R3_H, R3, |
|
718 |
R4_H, R4, |
|
719 |
R5_H, R5, |
|
720 |
R6_H, R6, |
|
721 |
R7_H, R7, |
|
722 |
R8_H, R8, |
|
723 |
R9_H, R9, |
|
724 |
R10_H, R10, |
|
725 |
R11_H, R11, |
|
726 |
R12_H, R12, |
|
727 |
/*R13_H, R13*/ // system thread id |
|
728 |
R14_H, R14, |
|
729 |
R15_H, R15, |
|
730 |
R16_H, R16, // R16_thread |
|
731 |
R17_H, R17, |
|
732 |
R18_H, R18, |
|
733 |
R19_H, R19, |
|
734 |
R20_H, R20, |
|
735 |
R21_H, R21, |
|
736 |
R22_H, R22, |
|
737 |
/*R23_H, R23, |
|
738 |
R24_H, R24, |
|
739 |
R25_H, R25, |
|
740 |
R26_H, R26, |
|
741 |
R27_H, R27, |
|
742 |
R28_H, R28,*/ |
|
743 |
/*R29_H, R29*/ // TODO: let allocator handle TOC!! |
|
744 |
/*R30_H, R30,*/ |
|
745 |
R31_H, R31 |
|
746 |
); |
|
747 |
||
748 |
// Complement-required-in-pipeline operands. |
|
749 |
// This register mask is used for the trap instructions that implement |
|
750 |
// the null checks on AIX. The trap instruction first computes the |
|
751 |
// complement of the value it shall trap on. Because of this, the |
|
752 |
// instruction can not be scheduled in the same cycle as an other |
|
753 |
// instruction reading the normal value of the same register. So we |
|
754 |
// force the value to check into 'bits64_reg_ro_not_complement' |
|
755 |
// and then copy it to 'bits64_reg_ro_complement' for the trap. |
|
756 |
reg_class bits64_reg_ro_complement ( |
|
757 |
R23_H, R23, |
|
758 |
R24_H, R24, |
|
759 |
R25_H, R25, |
|
760 |
R26_H, R26, |
|
761 |
R27_H, R27, |
|
762 |
R28_H, R28 |
|
763 |
); |
|
764 |
||
765 |
||
766 |
// ---------------------------- |
|
767 |
// Special Class for Condition Code Flags Register |
|
768 |
||
769 |
reg_class int_flags( |
|
770 |
/*CCR0*/ // scratch |
|
771 |
/*CCR1*/ // scratch |
|
772 |
/*CCR2*/ // nv! |
|
773 |
/*CCR3*/ // nv! |
|
774 |
/*CCR4*/ // nv! |
|
775 |
CCR5, |
|
776 |
CCR6, |
|
777 |
CCR7 |
|
778 |
); |
|
779 |
||
780 |
reg_class int_flags_CR0(CCR0); |
|
781 |
reg_class int_flags_CR1(CCR1); |
|
782 |
reg_class int_flags_CR6(CCR6); |
|
783 |
reg_class ctr_reg(SR_CTR); |
|
784 |
||
785 |
// ---------------------------- |
|
786 |
// Float Register Classes |
|
787 |
// ---------------------------- |
|
788 |
||
789 |
reg_class flt_reg( |
|
790 |
/*F0*/ // scratch |
|
791 |
F1, |
|
792 |
F2, |
|
793 |
F3, |
|
794 |
F4, |
|
795 |
F5, |
|
796 |
F6, |
|
797 |
F7, |
|
798 |
F8, |
|
799 |
F9, |
|
800 |
F10, |
|
801 |
F11, |
|
802 |
F12, |
|
803 |
F13, |
|
804 |
F14, // nv! |
|
805 |
F15, // nv! |
|
806 |
F16, // nv! |
|
807 |
F17, // nv! |
|
808 |
F18, // nv! |
|
809 |
F19, // nv! |
|
810 |
F20, // nv! |
|
811 |
F21, // nv! |
|
812 |
F22, // nv! |
|
813 |
F23, // nv! |
|
814 |
F24, // nv! |
|
815 |
F25, // nv! |
|
816 |
F26, // nv! |
|
817 |
F27, // nv! |
|
818 |
F28, // nv! |
|
819 |
F29, // nv! |
|
820 |
F30, // nv! |
|
821 |
F31 // nv! |
|
822 |
); |
|
823 |
||
824 |
// Double precision float registers have virtual `high halves' that |
|
825 |
// are needed by the allocator. |
|
826 |
reg_class dbl_reg( |
|
827 |
/*F0, F0_H*/ // scratch |
|
828 |
F1, F1_H, |
|
829 |
F2, F2_H, |
|
830 |
F3, F3_H, |
|
831 |
F4, F4_H, |
|
832 |
F5, F5_H, |
|
833 |
F6, F6_H, |
|
834 |
F7, F7_H, |
|
835 |
F8, F8_H, |
|
836 |
F9, F9_H, |
|
837 |
F10, F10_H, |
|
838 |
F11, F11_H, |
|
839 |
F12, F12_H, |
|
840 |
F13, F13_H, |
|
841 |
F14, F14_H, // nv! |
|
842 |
F15, F15_H, // nv! |
|
843 |
F16, F16_H, // nv! |
|
844 |
F17, F17_H, // nv! |
|
845 |
F18, F18_H, // nv! |
|
846 |
F19, F19_H, // nv! |
|
847 |
F20, F20_H, // nv! |
|
848 |
F21, F21_H, // nv! |
|
849 |
F22, F22_H, // nv! |
|
850 |
F23, F23_H, // nv! |
|
851 |
F24, F24_H, // nv! |
|
852 |
F25, F25_H, // nv! |
|
853 |
F26, F26_H, // nv! |
|
854 |
F27, F27_H, // nv! |
|
855 |
F28, F28_H, // nv! |
|
856 |
F29, F29_H, // nv! |
|
857 |
F30, F30_H, // nv! |
|
858 |
F31, F31_H // nv! |
|
859 |
); |
|
860 |
||
861 |
%} |
|
862 |
||
863 |
//----------DEFINITION BLOCK--------------------------------------------------- |
|
864 |
// Define name --> value mappings to inform the ADLC of an integer valued name |
|
865 |
// Current support includes integer values in the range [0, 0x7FFFFFFF] |
|
866 |
// Format: |
|
867 |
// int_def <name> ( <int_value>, <expression>); |
|
868 |
// Generated Code in ad_<arch>.hpp |
|
869 |
// #define <name> (<expression>) |
|
870 |
// // value == <int_value> |
|
871 |
// Generated code in ad_<arch>.cpp adlc_verification() |
|
872 |
// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); |
|
873 |
// |
|
874 |
definitions %{
|
|
875 |
// The default cost (of an ALU instruction). |
|
876 |
int_def DEFAULT_COST_LOW ( 30, 30); |
|
877 |
int_def DEFAULT_COST ( 100, 100); |
|
878 |
int_def HUGE_COST (1000000, 1000000); |
|
879 |
||
880 |
// Memory refs |
|
881 |
int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); |
|
882 |
int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); |
|
883 |
||
884 |
// Branches are even more expensive. |
|
885 |
int_def BRANCH_COST ( 900, DEFAULT_COST * 9); |
|
886 |
int_def CALL_COST ( 1300, DEFAULT_COST * 13); |
|
887 |
%} |
|
888 |
||
889 |
||
890 |
//----------SOURCE BLOCK------------------------------------------------------- |
|
891 |
// This is a block of C++ code which provides values, functions, and |
|
892 |
// definitions necessary in the rest of the architecture description. |
|
893 |
source_hpp %{
|
|
894 |
// Returns true if Node n is followed by a MemBar node that |
|
895 |
// will do an acquire. If so, this node must not do the acquire |
|
896 |
// operation. |
|
897 |
bool followed_by_acquire(const Node *n); |
|
898 |
%} |
|
899 |
||
900 |
source %{
|
|
901 |
||
902 |
// Optimize load-acquire. |
|
903 |
// |
|
904 |
// Check if acquire is unnecessary due to following operation that does |
|
905 |
// acquire anyways. |
|
906 |
// Walk the pattern: |
|
907 |
// |
|
908 |
// n: Load.acq |
|
909 |
// | |
|
910 |
// MemBarAcquire |
|
911 |
// | | |
|
912 |
// Proj(ctrl) Proj(mem) |
|
913 |
// | | |
|
914 |
// MemBarRelease/Volatile |
|
915 |
// |
|
916 |
bool followed_by_acquire(const Node *load) {
|
|
917 |
assert(load->is_Load(), "So far implemented only for loads."); |
|
918 |
||
919 |
// Find MemBarAcquire. |
|
920 |
const Node *mba = NULL; |
|
921 |
for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
|
|
922 |
const Node *out = load->fast_out(i); |
|
923 |
if (out->Opcode() == Op_MemBarAcquire) {
|
|
924 |
if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. |
|
925 |
mba = out; |
|
926 |
break; |
|
927 |
} |
|
928 |
} |
|
929 |
if (!mba) return false; |
|
930 |
||
931 |
// Find following MemBar node. |
|
932 |
// |
|
933 |
// The following node must be reachable by control AND memory |
|
934 |
// edge to assure no other operations are in between the two nodes. |
|
935 |
// |
|
936 |
// So first get the Proj node, mem_proj, to use it to iterate forward. |
|
937 |
Node *mem_proj = NULL; |
|
938 |
for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
|
|
939 |
mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found |
|
940 |
assert(mem_proj->is_Proj(), "only projections here"); |
|
941 |
ProjNode *proj = mem_proj->as_Proj(); |
|
942 |
if (proj->_con == TypeFunc::Memory && |
|
943 |
!Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only |
|
944 |
break; |
|
945 |
} |
|
946 |
assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); |
|
947 |
||
948 |
// Search MemBar behind Proj. If there are other memory operations |
|
949 |
// behind the Proj we lost. |
|
950 |
for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
|
|
951 |
Node *x = mem_proj->fast_out(j); |
|
952 |
// Proj might have an edge to a store or load node which precedes the membar. |
|
953 |
if (x->is_Mem()) return false; |
|
954 |
||
955 |
// On PPC64 release and volatile are implemented by an instruction |
|
956 |
// that also has acquire semantics. I.e. there is no need for an |
|
957 |
// acquire before these. |
|
958 |
int xop = x->Opcode(); |
|
959 |
if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
|
|
960 |
// Make sure we're not missing Call/Phi/MergeMem by checking |
|
961 |
// control edges. The control edge must directly lead back |
|
962 |
// to the MemBarAcquire |
|
963 |
Node *ctrl_proj = x->in(0); |
|
964 |
if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
|
|
965 |
return true; |
|
966 |
} |
|
967 |
} |
|
968 |
} |
|
969 |
||
970 |
return false; |
|
971 |
} |
|
972 |
||
973 |
#define __ _masm. |
|
974 |
||
975 |
// Tertiary op of a LoadP or StoreP encoding. |
|
976 |
#define REGP_OP true |
|
977 |
||
978 |
// **************************************************************************** |
|
979 |
||
980 |
// REQUIRED FUNCTIONALITY |
|
981 |
||
982 |
// !!!!! Special hack to get all type of calls to specify the byte offset |
|
983 |
// from the start of the call to the point where the return address |
|
984 |
// will point. |
|
985 |
||
986 |
// PPC port: Removed use of lazy constant construct. |
|
987 |
||
988 |
int MachCallStaticJavaNode::ret_addr_offset() {
|
|
989 |
// It's only a single branch-and-link instruction. |
|
990 |
return 4; |
|
991 |
} |
|
992 |
||
993 |
int MachCallDynamicJavaNode::ret_addr_offset() {
|
|
994 |
// Offset is 4 with postalloc expanded calls (bl is one instruction). We use |
|
995 |
// postalloc expanded calls if we use inline caches and do not update method data. |
|
996 |
if (UseInlineCaches) |
|
997 |
return 4; |
|
998 |
||
999 |
int vtable_index = this->_vtable_index; |
|
1000 |
if (vtable_index < 0) {
|
|
1001 |
// Must be invalid_vtable_index, not nonvirtual_vtable_index. |
|
1002 |
assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
|
1003 |
return 12; |
|
1004 |
} else {
|
|
1005 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
1006 |
return 24; |
|
1007 |
} |
|
1008 |
} |
|
1009 |
||
1010 |
int MachCallRuntimeNode::ret_addr_offset() {
|
|
1011 |
return 40; |
|
1012 |
} |
|
1013 |
||
1014 |
//============================================================================= |
|
1015 |
||
1016 |
// condition code conversions |
|
1017 |
||
1018 |
static int cc_to_boint(int cc) {
|
|
1019 |
return Assembler::bcondCRbiIs0 | (cc & 8); |
|
1020 |
} |
|
1021 |
||
1022 |
static int cc_to_inverse_boint(int cc) {
|
|
1023 |
return Assembler::bcondCRbiIs0 | (8-(cc & 8)); |
|
1024 |
} |
|
1025 |
||
1026 |
static int cc_to_biint(int cc, int flags_reg) {
|
|
1027 |
return (flags_reg << 2) | (cc & 3); |
|
1028 |
} |
|
1029 |
||
1030 |
//============================================================================= |
|
1031 |
||
1032 |
// Compute padding required for nodes which need alignment. The padding |
|
1033 |
// is the number of bytes (not instructions) which will be inserted before |
|
1034 |
// the instruction. The padding must match the size of a NOP instruction. |
|
1035 |
||
1036 |
int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
|
|
1037 |
return (3*4-current_offset)&31; |
|
1038 |
} |
|
1039 |
||
1040 |
int string_indexOf_imm1Node::compute_padding(int current_offset) const {
|
|
1041 |
return (2*4-current_offset)&31; |
|
1042 |
} |
|
1043 |
||
1044 |
int string_indexOf_immNode::compute_padding(int current_offset) const {
|
|
1045 |
return (3*4-current_offset)&31; |
|
1046 |
} |
|
1047 |
||
1048 |
int string_indexOfNode::compute_padding(int current_offset) const {
|
|
1049 |
return (1*4-current_offset)&31; |
|
1050 |
} |
|
1051 |
||
1052 |
int string_compareNode::compute_padding(int current_offset) const {
|
|
1053 |
return (4*4-current_offset)&31; |
|
1054 |
} |
|
1055 |
||
1056 |
int string_equals_immNode::compute_padding(int current_offset) const {
|
|
1057 |
if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). |
|
1058 |
return (2*4-current_offset)&31; |
|
1059 |
} |
|
1060 |
||
1061 |
int string_equalsNode::compute_padding(int current_offset) const {
|
|
1062 |
return (7*4-current_offset)&31; |
|
1063 |
} |
|
1064 |
||
1065 |
int inlineCallClearArrayNode::compute_padding(int current_offset) const {
|
|
1066 |
return (2*4-current_offset)&31; |
|
1067 |
} |
|
1068 |
||
1069 |
//============================================================================= |
|
1070 |
||
1071 |
// Indicate if the safepoint node needs the polling page as an input. |
|
1072 |
bool SafePointNode::needs_polling_address_input() {
|
|
1073 |
// The address is loaded from thread by a seperate node. |
|
1074 |
return true; |
|
1075 |
} |
|
1076 |
||
1077 |
//============================================================================= |
|
1078 |
||
1079 |
// Emit an interrupt that is caught by the debugger (for debugging compiler). |
|
1080 |
void emit_break(CodeBuffer &cbuf) {
|
|
1081 |
MacroAssembler _masm(&cbuf); |
|
1082 |
__ illtrap(); |
|
1083 |
} |
|
1084 |
||
1085 |
#ifndef PRODUCT |
|
1086 |
void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1087 |
st->print("BREAKPOINT");
|
|
1088 |
} |
|
1089 |
#endif |
|
1090 |
||
1091 |
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1092 |
emit_break(cbuf); |
|
1093 |
} |
|
1094 |
||
1095 |
uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
|
|
1096 |
return MachNode::size(ra_); |
|
1097 |
} |
|
1098 |
||
1099 |
//============================================================================= |
|
1100 |
||
1101 |
void emit_nop(CodeBuffer &cbuf) {
|
|
1102 |
MacroAssembler _masm(&cbuf); |
|
1103 |
__ nop(); |
|
1104 |
} |
|
1105 |
||
1106 |
static inline void emit_long(CodeBuffer &cbuf, int value) {
|
|
1107 |
*((int*)(cbuf.insts_end())) = value; |
|
1108 |
cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); |
|
1109 |
} |
|
1110 |
||
1111 |
//============================================================================= |
|
1112 |
||
1113 |
// Emit a trampoline stub for a call to a target which is too far away. |
|
1114 |
// |
|
1115 |
// code sequences: |
|
1116 |
// |
|
1117 |
// call-site: |
|
1118 |
// branch-and-link to <destination> or <trampoline stub> |
|
1119 |
// |
|
1120 |
// Related trampoline stub for this call-site in the stub section: |
|
1121 |
// load the call target from the constant pool |
|
1122 |
// branch via CTR (LR/link still points to the call-site above) |
|
1123 |
||
1124 |
const uint trampoline_stub_size = 6 * BytesPerInstWord; |
|
1125 |
||
1126 |
void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
|
|
1127 |
// Start the stub. |
|
1128 |
address stub = __ start_a_stub(Compile::MAX_stubs_size/2); |
|
1129 |
if (stub == NULL) {
|
|
1130 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
1131 |
return; |
|
1132 |
} |
|
1133 |
||
1134 |
// For java_to_interp stubs we use R11_scratch1 as scratch register |
|
1135 |
// and in call trampoline stubs we use R12_scratch2. This way we |
|
1136 |
// can distinguish them (see is_NativeCallTrampolineStub_at()). |
|
1137 |
Register reg_scratch = R12_scratch2; |
|
1138 |
||
1139 |
// Create a trampoline stub relocation which relates this trampoline stub |
|
1140 |
// with the call instruction at insts_call_instruction_offset in the |
|
1141 |
// instructions code-section. |
|
1142 |
__ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); |
|
1143 |
const int stub_start_offset = __ offset(); |
|
1144 |
||
1145 |
// Now, create the trampoline stub's code: |
|
1146 |
// - load the TOC |
|
1147 |
// - load the call target from the constant pool |
|
1148 |
// - call |
|
1149 |
__ calculate_address_from_global_toc(reg_scratch, __ method_toc()); |
|
1150 |
__ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); |
|
1151 |
__ mtctr(reg_scratch); |
|
1152 |
__ bctr(); |
|
1153 |
||
1154 |
const address stub_start_addr = __ addr_at(stub_start_offset); |
|
1155 |
||
1156 |
// FIXME: Assert that the trampoline stub can be identified and patched. |
|
1157 |
||
1158 |
// Assert that the encoded destination_toc_offset can be identified and that it is correct. |
|
1159 |
assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), |
|
1160 |
"encoded offset into the constant pool must match"); |
|
1161 |
// Trampoline_stub_size should be good. |
|
1162 |
assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); |
|
1163 |
assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); |
|
1164 |
||
1165 |
// End the stub. |
|
1166 |
__ end_a_stub(); |
|
1167 |
} |
|
1168 |
||
1169 |
// Size of trampoline stub, this doesn't need to be accurate but it must |
|
1170 |
// be larger or equal to the real size of the stub. |
|
1171 |
// Used for optimization in Compile::Shorten_branches. |
|
1172 |
uint size_call_trampoline() {
|
|
1173 |
return trampoline_stub_size; |
|
1174 |
} |
|
1175 |
||
1176 |
// Number of relocation entries needed by trampoline stub. |
|
1177 |
// Used for optimization in Compile::Shorten_branches. |
|
1178 |
uint reloc_call_trampoline() {
|
|
1179 |
return 5; |
|
1180 |
} |
|
1181 |
||
1182 |
//============================================================================= |
|
1183 |
||
1184 |
// Emit an inline branch-and-link call and a related trampoline stub. |
|
1185 |
// |
|
1186 |
// code sequences: |
|
1187 |
// |
|
1188 |
// call-site: |
|
1189 |
// branch-and-link to <destination> or <trampoline stub> |
|
1190 |
// |
|
1191 |
// Related trampoline stub for this call-site in the stub section: |
|
1192 |
// load the call target from the constant pool |
|
1193 |
// branch via CTR (LR/link still points to the call-site above) |
|
1194 |
// |
|
1195 |
||
1196 |
typedef struct {
|
|
1197 |
int insts_call_instruction_offset; |
|
1198 |
int ret_addr_offset; |
|
1199 |
} EmitCallOffsets; |
|
1200 |
||
1201 |
// Emit a branch-and-link instruction that branches to a trampoline. |
|
1202 |
// - Remember the offset of the branch-and-link instruction. |
|
1203 |
// - Add a relocation at the branch-and-link instruction. |
|
1204 |
// - Emit a branch-and-link. |
|
1205 |
// - Remember the return pc offset. |
|
1206 |
EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
|
|
1207 |
EmitCallOffsets offsets = { -1, -1 };
|
|
1208 |
const int start_offset = __ offset(); |
|
1209 |
offsets.insts_call_instruction_offset = __ offset(); |
|
1210 |
||
1211 |
// No entry point given, use the current pc. |
|
1212 |
if (entry_point == NULL) entry_point = __ pc(); |
|
1213 |
||
1214 |
if (!Compile::current()->in_scratch_emit_size()) {
|
|
1215 |
// Put the entry point as a constant into the constant pool. |
|
1216 |
const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
1217 |
const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
1218 |
||
1219 |
// Emit the trampoline stub which will be related to the branch-and-link below. |
|
1220 |
emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); |
|
1221 |
__ relocate(rtype); |
|
1222 |
} |
|
1223 |
||
1224 |
// Note: At this point we do not have the address of the trampoline |
|
1225 |
// stub, and the entry point might be too far away for bl, so __ pc() |
|
1226 |
// serves as dummy and the bl will be patched later. |
|
1227 |
__ bl((address) __ pc()); |
|
1228 |
||
1229 |
offsets.ret_addr_offset = __ offset() - start_offset; |
|
1230 |
||
1231 |
return offsets; |
|
1232 |
} |
|
1233 |
||
1234 |
//============================================================================= |
|
1235 |
||
1236 |
// Factory for creating loadConL* nodes for large/small constant pool. |
|
1237 |
||
1238 |
static inline jlong replicate_immF(float con) {
|
|
1239 |
// Replicate float con 2 times and pack into vector. |
|
1240 |
int val = *((int*)&con); |
|
1241 |
jlong lval = val; |
|
1242 |
lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
|
1243 |
return lval; |
|
1244 |
} |
|
1245 |
||
1246 |
//============================================================================= |
|
1247 |
||
1248 |
const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); |
|
1249 |
int Compile::ConstantTable::calculate_table_base_offset() const {
|
|
1250 |
return 0; // absolute addressing, no offset |
|
1251 |
} |
|
1252 |
||
1253 |
bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
|
|
1254 |
void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
|
|
1255 |
Compile *C = ra_->C; |
|
1256 |
||
1257 |
iRegPdstOper *op_dst = new (C) iRegPdstOper(); |
|
1258 |
MachNode *m1 = new (C) loadToc_hiNode(); |
|
1259 |
MachNode *m2 = new (C) loadToc_loNode(); |
|
1260 |
||
1261 |
m1->add_req(NULL); |
|
1262 |
m2->add_req(NULL, m1); |
|
1263 |
m1->_opnds[0] = op_dst; |
|
1264 |
m2->_opnds[0] = op_dst; |
|
1265 |
m2->_opnds[1] = op_dst; |
|
1266 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
1267 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
1268 |
nodes->push(m1); |
|
1269 |
nodes->push(m2); |
|
1270 |
} |
|
1271 |
||
1272 |
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
|
|
1273 |
// Is postalloc expanded. |
|
1274 |
ShouldNotReachHere(); |
|
1275 |
} |
|
1276 |
||
1277 |
uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
|
|
1278 |
return 0; |
|
1279 |
} |
|
1280 |
||
1281 |
#ifndef PRODUCT |
|
1282 |
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
|
|
1283 |
st->print("-- \t// MachConstantBaseNode (empty encoding)");
|
|
1284 |
} |
|
1285 |
#endif |
|
1286 |
||
1287 |
//============================================================================= |
|
1288 |
||
1289 |
#ifndef PRODUCT |
|
1290 |
void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1291 |
Compile* C = ra_->C; |
|
1292 |
const long framesize = C->frame_slots() << LogBytesPerInt; |
|
1293 |
||
1294 |
st->print("PROLOG\n\t");
|
|
1295 |
if (C->need_stack_bang(framesize)) {
|
|
1296 |
st->print("stack_overflow_check\n\t");
|
|
1297 |
} |
|
1298 |
||
1299 |
if (!false /* TODO: PPC port C->is_frameless_method()*/) {
|
|
1300 |
st->print("save return pc\n\t");
|
|
1301 |
st->print("push frame %d\n\t", -framesize);
|
|
1302 |
} |
|
1303 |
} |
|
1304 |
#endif |
|
1305 |
||
1306 |
// Macro used instead of the common __ to emulate the pipes of PPC. |
|
1307 |
// Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the |
|
1308 |
// micro scheduler to cope with "hand written" assembler like in the prolog. Though |
|
1309 |
// still no scheduling of this code is possible, the micro scheduler is aware of the |
|
1310 |
// code and can update its internal data. The following mechanism is used to achieve this: |
|
1311 |
// The micro scheduler calls size() of each compound node during scheduling. size() does a |
|
1312 |
// dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. |
|
1313 |
#if 0 // TODO: PPC port |
|
1314 |
#define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1315 |
C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ |
|
1316 |
_masm. |
|
1317 |
#define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1318 |
C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) |
|
1319 |
#define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1320 |
C->hb_scheduling()->_pdScheduling->advance_offset |
|
1321 |
#else |
|
1322 |
#define ___(op) if (UsePower6SchedulerPPC64) \ |
|
1323 |
Unimplemented(); \ |
|
1324 |
_masm. |
|
1325 |
#define ___stop if (UsePower6SchedulerPPC64) \ |
|
1326 |
Unimplemented() |
|
1327 |
#define ___advance if (UsePower6SchedulerPPC64) \ |
|
1328 |
Unimplemented() |
|
1329 |
#endif |
|
1330 |
||
1331 |
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1332 |
Compile* C = ra_->C; |
|
1333 |
MacroAssembler _masm(&cbuf); |
|
1334 |
||
1335 |
const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; |
|
1336 |
assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); |
|
1337 |
||
1338 |
const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; |
|
1339 |
||
1340 |
const Register return_pc = R20; // Must match return_addr() in frame section. |
|
1341 |
const Register callers_sp = R21; |
|
1342 |
const Register push_frame_temp = R22; |
|
1343 |
const Register toc_temp = R23; |
|
1344 |
assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); |
|
1345 |
||
1346 |
if (method_is_frameless) {
|
|
1347 |
// Add nop at beginning of all frameless methods to prevent any |
|
1348 |
// oop instructions from getting overwritten by make_not_entrant |
|
1349 |
// (patching attempt would fail). |
|
1350 |
___(nop) nop(); |
|
1351 |
} else {
|
|
1352 |
// Get return pc. |
|
1353 |
___(mflr) mflr(return_pc); |
|
1354 |
} |
|
1355 |
||
1356 |
// Calls to C2R adapters often do not accept exceptional returns. |
|
1357 |
// We require that their callers must bang for them. But be |
|
1358 |
// careful, because some VM calls (such as call site linkage) can |
|
1359 |
// use several kilobytes of stack. But the stack safety zone should |
|
1360 |
// account for that. See bugs 4446381, 4468289, 4497237. |
|
1361 |
if (C->need_stack_bang(framesize) && UseStackBanging) {
|
|
1362 |
// Unfortunately we cannot use the function provided in |
|
1363 |
// assembler.cpp as we have to emulate the pipes. So I had to |
|
1364 |
// insert the code of generate_stack_overflow_check(), see |
|
1365 |
// assembler.cpp for some illuminative comments. |
|
1366 |
const int page_size = os::vm_page_size(); |
|
1367 |
int bang_end = StackShadowPages*page_size; |
|
1368 |
||
1369 |
// This is how far the previous frame's stack banging extended. |
|
1370 |
const int bang_end_safe = bang_end; |
|
1371 |
||
1372 |
if (framesize > page_size) {
|
|
1373 |
bang_end += framesize; |
|
1374 |
} |
|
1375 |
||
1376 |
int bang_offset = bang_end_safe; |
|
1377 |
||
1378 |
while (bang_offset <= bang_end) {
|
|
1379 |
// Need at least one stack bang at end of shadow zone. |
|
1380 |
||
1381 |
// Again I had to copy code, this time from assembler_ppc64.cpp, |
|
1382 |
// bang_stack_with_offset - see there for comments. |
|
1383 |
||
1384 |
// Stack grows down, caller passes positive offset. |
|
1385 |
assert(bang_offset > 0, "must bang with positive offset"); |
|
1386 |
||
1387 |
long stdoffset = -bang_offset; |
|
1388 |
||
1389 |
if (Assembler::is_simm(stdoffset, 16)) {
|
|
1390 |
// Signed 16 bit offset, a simple std is ok. |
|
1391 |
if (UseLoadInstructionsForStackBangingPPC64) {
|
|
1392 |
___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); |
|
1393 |
} else {
|
|
1394 |
___(std) std(R0, (int)(signed short)stdoffset, R1_SP); |
|
1395 |
} |
|
1396 |
} else if (Assembler::is_simm(stdoffset, 31)) {
|
|
1397 |
// Use largeoffset calculations for addis & ld/std. |
|
1398 |
const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); |
|
1399 |
const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); |
|
1400 |
||
1401 |
Register tmp = R11; |
|
1402 |
___(addis) addis(tmp, R1_SP, hi); |
|
1403 |
if (UseLoadInstructionsForStackBangingPPC64) {
|
|
1404 |
___(ld) ld(R0, lo, tmp); |
|
1405 |
} else {
|
|
1406 |
___(std) std(R0, lo, tmp); |
|
1407 |
} |
|
1408 |
} else {
|
|
1409 |
ShouldNotReachHere(); |
|
1410 |
} |
|
1411 |
||
1412 |
bang_offset += page_size; |
|
1413 |
} |
|
1414 |
// R11 trashed |
|
1415 |
} // C->need_stack_bang(framesize) && UseStackBanging |
|
1416 |
||
1417 |
unsigned int bytes = (unsigned int)framesize; |
|
1418 |
long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); |
|
1419 |
ciMethod *currMethod = C -> method(); |
|
1420 |
||
1421 |
// Optimized version for most common case. |
|
1422 |
if (UsePower6SchedulerPPC64 && |
|
| 22867 | 1423 |
!method_is_frameless && Assembler::is_simm((int)(-offset), 16) && |
| 22861 | 1424 |
!(false /* ConstantsALot TODO: PPC port*/)) {
|
1425 |
___(or) mr(callers_sp, R1_SP); |
|
| 22867 | 1426 |
___(std) std(return_pc, _abi(lr), R1_SP); |
1427 |
___(stdu) stdu(R1_SP, -offset, R1_SP); |
|
| 22861 | 1428 |
return; |
1429 |
} |
|
1430 |
||
1431 |
if (!method_is_frameless) {
|
|
1432 |
// Get callers sp. |
|
1433 |
___(or) mr(callers_sp, R1_SP); |
|
1434 |
||
1435 |
// Push method's frame, modifies SP. |
|
1436 |
assert(Assembler::is_uimm(framesize, 32U), "wrong type"); |
|
1437 |
// The ABI is already accounted for in 'framesize' via the |
|
1438 |
// 'out_preserve' area. |
|
1439 |
Register tmp = push_frame_temp; |
|
1440 |
// Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). |
|
1441 |
if (Assembler::is_simm(-offset, 16)) {
|
|
1442 |
___(stdu) stdu(R1_SP, -offset, R1_SP); |
|
1443 |
} else {
|
|
1444 |
long x = -offset; |
|
1445 |
// Had to insert load_const(tmp, -offset). |
|
1446 |
___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); |
|
1447 |
___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); |
|
1448 |
___(rldicr) sldi(tmp, tmp, 32); |
|
1449 |
___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); |
|
1450 |
___(ori) ori( tmp, tmp, (x & 0x0000ffff)); |
|
1451 |
||
1452 |
___(stdux) stdux(R1_SP, R1_SP, tmp); |
|
1453 |
} |
|
1454 |
} |
|
1455 |
#if 0 // TODO: PPC port |
|
1456 |
// For testing large constant pools, emit a lot of constants to constant pool. |
|
1457 |
// "Randomize" const_size. |
|
1458 |
if (ConstantsALot) {
|
|
1459 |
const int num_consts = const_size(); |
|
1460 |
for (int i = 0; i < num_consts; i++) {
|
|
1461 |
__ long_constant(0xB0B5B00BBABE); |
|
1462 |
} |
|
1463 |
} |
|
1464 |
#endif |
|
1465 |
if (!method_is_frameless) {
|
|
1466 |
// Save return pc. |
|
1467 |
___(std) std(return_pc, _abi(lr), callers_sp); |
|
1468 |
} |
|
1469 |
} |
|
1470 |
#undef ___ |
|
1471 |
#undef ___stop |
|
| 22867 | 1472 |
#undef ___advance |
| 22861 | 1473 |
|
1474 |
uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
|
|
1475 |
// Variable size. determine dynamically. |
|
1476 |
return MachNode::size(ra_); |
|
1477 |
} |
|
1478 |
||
1479 |
int MachPrologNode::reloc() const {
|
|
1480 |
// Return number of relocatable values contained in this instruction. |
|
1481 |
return 1; // 1 reloc entry for load_const(toc). |
|
1482 |
} |
|
1483 |
||
1484 |
//============================================================================= |
|
1485 |
||
1486 |
#ifndef PRODUCT |
|
1487 |
void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1488 |
Compile* C = ra_->C; |
|
1489 |
||
1490 |
st->print("EPILOG\n\t");
|
|
1491 |
st->print("restore return pc\n\t");
|
|
1492 |
st->print("pop frame\n\t");
|
|
1493 |
||
1494 |
if (do_polling() && C->is_method_compilation()) {
|
|
1495 |
st->print("touch polling page\n\t");
|
|
1496 |
} |
|
1497 |
} |
|
1498 |
#endif |
|
1499 |
||
1500 |
void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1501 |
Compile* C = ra_->C; |
|
1502 |
MacroAssembler _masm(&cbuf); |
|
1503 |
||
1504 |
const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; |
|
1505 |
assert(framesize >= 0, "negative frame-size?"); |
|
1506 |
||
1507 |
const bool method_needs_polling = do_polling() && C->is_method_compilation(); |
|
1508 |
const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; |
|
1509 |
const Register return_pc = R11; |
|
1510 |
const Register polling_page = R12; |
|
1511 |
||
1512 |
if (!method_is_frameless) {
|
|
1513 |
// Restore return pc relative to callers' sp. |
|
1514 |
__ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); |
|
1515 |
} |
|
1516 |
||
1517 |
if (method_needs_polling) {
|
|
1518 |
if (LoadPollAddressFromThread) {
|
|
1519 |
// TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); |
|
1520 |
Unimplemented(); |
|
1521 |
} else {
|
|
1522 |
__ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() |
|
1523 |
} |
|
1524 |
} |
|
1525 |
||
1526 |
if (!method_is_frameless) {
|
|
1527 |
// Move return pc to LR. |
|
1528 |
__ mtlr(return_pc); |
|
1529 |
// Pop frame (fixed frame-size). |
|
1530 |
__ addi(R1_SP, R1_SP, (int)framesize); |
|
1531 |
} |
|
1532 |
||
1533 |
if (method_needs_polling) {
|
|
1534 |
// We need to mark the code position where the load from the safepoint |
|
1535 |
// polling page was emitted as relocInfo::poll_return_type here. |
|
1536 |
__ relocate(relocInfo::poll_return_type); |
|
1537 |
__ load_from_polling_page(polling_page); |
|
1538 |
} |
|
1539 |
} |
|
1540 |
||
1541 |
uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
|
|
1542 |
// Variable size. Determine dynamically. |
|
1543 |
return MachNode::size(ra_); |
|
1544 |
} |
|
1545 |
||
1546 |
int MachEpilogNode::reloc() const {
|
|
1547 |
// Return number of relocatable values contained in this instruction. |
|
1548 |
return 1; // 1 for load_from_polling_page. |
|
1549 |
} |
|
1550 |
||
1551 |
const Pipeline * MachEpilogNode::pipeline() const {
|
|
1552 |
return MachNode::pipeline_class(); |
|
1553 |
} |
|
1554 |
||
1555 |
// This method seems to be obsolete. It is declared in machnode.hpp |
|
1556 |
// and defined in all *.ad files, but it is never called. Should we |
|
1557 |
// get rid of it? |
|
1558 |
int MachEpilogNode::safepoint_offset() const {
|
|
1559 |
assert(do_polling(), "no return for this epilog node"); |
|
1560 |
return 0; |
|
1561 |
} |
|
1562 |
||
1563 |
#if 0 // TODO: PPC port |
|
1564 |
void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
|
|
1565 |
MacroAssembler _masm(&cbuf); |
|
1566 |
if (LoadPollAddressFromThread) {
|
|
1567 |
_masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); |
|
1568 |
} else {
|
|
1569 |
_masm.nop(); |
|
1570 |
} |
|
1571 |
} |
|
1572 |
||
1573 |
uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
|
|
1574 |
if (LoadPollAddressFromThread) {
|
|
1575 |
return 4; |
|
1576 |
} else {
|
|
1577 |
return 4; |
|
1578 |
} |
|
1579 |
} |
|
1580 |
||
1581 |
#ifndef PRODUCT |
|
1582 |
void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
|
|
1583 |
st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
|
|
1584 |
} |
|
1585 |
#endif |
|
1586 |
||
1587 |
const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
|
|
1588 |
return RSCRATCH1_BITS64_REG_mask(); |
|
1589 |
} |
|
1590 |
#endif // PPC port |
|
1591 |
||
1592 |
// ============================================================================= |
|
1593 |
||
1594 |
// Figure out which register class each belongs in: rc_int, rc_float or |
|
1595 |
// rc_stack. |
|
1596 |
enum RC { rc_bad, rc_int, rc_float, rc_stack };
|
|
1597 |
||
1598 |
static enum RC rc_class(OptoReg::Name reg) {
|
|
1599 |
// Return the register class for the given register. The given register |
|
1600 |
// reg is a <register>_num value, which is an index into the MachRegisterNumbers |
|
1601 |
// enumeration in adGlobals_ppc64.hpp. |
|
1602 |
||
1603 |
if (reg == OptoReg::Bad) return rc_bad; |
|
1604 |
||
1605 |
// We have 64 integer register halves, starting at index 0. |
|
1606 |
if (reg < 64) return rc_int; |
|
1607 |
||
1608 |
// We have 64 floating-point register halves, starting at index 64. |
|
1609 |
if (reg < 64+64) return rc_float; |
|
1610 |
||
1611 |
// Between float regs & stack are the flags regs. |
|
1612 |
assert(OptoReg::is_stack(reg), "blow up if spilling flags"); |
|
1613 |
||
1614 |
return rc_stack; |
|
1615 |
} |
|
1616 |
||
1617 |
static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, |
|
1618 |
bool do_print, Compile* C, outputStream *st) {
|
|
1619 |
||
1620 |
assert(opcode == Assembler::LD_OPCODE || |
|
1621 |
opcode == Assembler::STD_OPCODE || |
|
1622 |
opcode == Assembler::LWZ_OPCODE || |
|
1623 |
opcode == Assembler::STW_OPCODE || |
|
1624 |
opcode == Assembler::LFD_OPCODE || |
|
1625 |
opcode == Assembler::STFD_OPCODE || |
|
1626 |
opcode == Assembler::LFS_OPCODE || |
|
1627 |
opcode == Assembler::STFS_OPCODE, |
|
1628 |
"opcode not supported"); |
|
1629 |
||
1630 |
if (cbuf) {
|
|
1631 |
int d = |
|
1632 |
(Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? |
|
1633 |
Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) |
|
1634 |
: Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. |
|
1635 |
emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); |
|
1636 |
} |
|
1637 |
#ifndef PRODUCT |
|
1638 |
else if (do_print) {
|
|
1639 |
st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
|
|
1640 |
op_str, |
|
1641 |
Matcher::regName[reg], |
|
1642 |
offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); |
|
1643 |
} |
|
1644 |
#endif |
|
1645 |
return 4; // size |
|
1646 |
} |
|
1647 |
||
1648 |
uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
|
|
1649 |
Compile* C = ra_->C; |
|
1650 |
||
1651 |
// Get registers to move. |
|
1652 |
OptoReg::Name src_hi = ra_->get_reg_second(in(1)); |
|
1653 |
OptoReg::Name src_lo = ra_->get_reg_first(in(1)); |
|
1654 |
OptoReg::Name dst_hi = ra_->get_reg_second(this); |
|
1655 |
OptoReg::Name dst_lo = ra_->get_reg_first(this); |
|
1656 |
||
1657 |
enum RC src_hi_rc = rc_class(src_hi); |
|
1658 |
enum RC src_lo_rc = rc_class(src_lo); |
|
1659 |
enum RC dst_hi_rc = rc_class(dst_hi); |
|
1660 |
enum RC dst_lo_rc = rc_class(dst_lo); |
|
1661 |
||
1662 |
assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); |
|
1663 |
if (src_hi != OptoReg::Bad) |
|
1664 |
assert((src_lo&1)==0 && src_lo+1==src_hi && |
|
1665 |
(dst_lo&1)==0 && dst_lo+1==dst_hi, |
|
1666 |
"expected aligned-adjacent pairs"); |
|
1667 |
// Generate spill code! |
|
1668 |
int size = 0; |
|
1669 |
||
1670 |
if (src_lo == dst_lo && src_hi == dst_hi) |
|
1671 |
return size; // Self copy, no move. |
|
1672 |
||
1673 |
// -------------------------------------- |
|
1674 |
// Memory->Memory Spill. Use R0 to hold the value. |
|
1675 |
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
|
|
1676 |
int src_offset = ra_->reg2offset(src_lo); |
|
1677 |
int dst_offset = ra_->reg2offset(dst_lo); |
|
1678 |
if (src_hi != OptoReg::Bad) {
|
|
1679 |
assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, |
|
1680 |
"expected same type of move for high parts"); |
|
1681 |
size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); |
|
1682 |
if (!cbuf && !do_size) st->print("\n\t");
|
|
1683 |
size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); |
|
1684 |
} else {
|
|
1685 |
size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); |
|
1686 |
if (!cbuf && !do_size) st->print("\n\t");
|
|
1687 |
size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); |
|
1688 |
} |
|
1689 |
return size; |
|
1690 |
} |
|
1691 |
||
1692 |
// -------------------------------------- |
|
1693 |
// Check for float->int copy; requires a trip through memory. |
|
1694 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
|
|
1695 |
Unimplemented(); |
|
1696 |
} |
|
1697 |
||
1698 |
// -------------------------------------- |
|
1699 |
// Check for integer reg-reg copy. |
|
1700 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
|
|
1701 |
Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); |
|
1702 |
Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); |
|
1703 |
size = (Rsrc != Rdst) ? 4 : 0; |
|
1704 |
||
1705 |
if (cbuf) {
|
|
1706 |
MacroAssembler _masm(cbuf); |
|
1707 |
if (size) {
|
|
1708 |
__ mr(Rdst, Rsrc); |
|
1709 |
} |
|
1710 |
} |
|
1711 |
#ifndef PRODUCT |
|
1712 |
else if (!do_size) {
|
|
1713 |
if (size) {
|
|
1714 |
st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
|
|
1715 |
} else {
|
|
1716 |
st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
|
|
1717 |
} |
|
1718 |
} |
|
1719 |
#endif |
|
1720 |
return size; |
|
1721 |
} |
|
1722 |
||
1723 |
// Check for integer store. |
|
1724 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
|
|
1725 |
int dst_offset = ra_->reg2offset(dst_lo); |
|
1726 |
if (src_hi != OptoReg::Bad) {
|
|
1727 |
assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, |
|
1728 |
"expected same type of move for high parts"); |
|
1729 |
size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1730 |
} else {
|
|
1731 |
size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1732 |
} |
|
1733 |
return size; |
|
1734 |
} |
|
1735 |
||
1736 |
// Check for integer load. |
|
1737 |
if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
|
|
1738 |
int src_offset = ra_->reg2offset(src_lo); |
|
1739 |
if (src_hi != OptoReg::Bad) {
|
|
1740 |
assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, |
|
1741 |
"expected same type of move for high parts"); |
|
1742 |
size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1743 |
} else {
|
|
1744 |
size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1745 |
} |
|
1746 |
return size; |
|
1747 |
} |
|
1748 |
||
1749 |
// Check for float reg-reg copy. |
|
1750 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
|
|
1751 |
if (cbuf) {
|
|
1752 |
MacroAssembler _masm(cbuf); |
|
1753 |
FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); |
|
1754 |
FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); |
|
1755 |
__ fmr(Rdst, Rsrc); |
|
1756 |
} |
|
1757 |
#ifndef PRODUCT |
|
1758 |
else if (!do_size) {
|
|
1759 |
st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
|
|
1760 |
} |
|
1761 |
#endif |
|
1762 |
return 4; |
|
1763 |
} |
|
1764 |
||
1765 |
// Check for float store. |
|
1766 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
|
|
1767 |
int dst_offset = ra_->reg2offset(dst_lo); |
|
1768 |
if (src_hi != OptoReg::Bad) {
|
|
1769 |
assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, |
|
1770 |
"expected same type of move for high parts"); |
|
1771 |
size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1772 |
} else {
|
|
1773 |
size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1774 |
} |
|
1775 |
return size; |
|
1776 |
} |
|
1777 |
||
1778 |
// Check for float load. |
|
1779 |
if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
|
|
1780 |
int src_offset = ra_->reg2offset(src_lo); |
|
1781 |
if (src_hi != OptoReg::Bad) {
|
|
1782 |
assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, |
|
1783 |
"expected same type of move for high parts"); |
|
1784 |
size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1785 |
} else {
|
|
1786 |
size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1787 |
} |
|
1788 |
return size; |
|
1789 |
} |
|
1790 |
||
1791 |
// -------------------------------------------------------------------- |
|
1792 |
// Check for hi bits still needing moving. Only happens for misaligned |
|
1793 |
// arguments to native calls. |
|
1794 |
if (src_hi == dst_hi) |
|
1795 |
return size; // Self copy; no move. |
|
1796 |
||
1797 |
assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); |
|
1798 |
ShouldNotReachHere(); // Unimplemented |
|
1799 |
return 0; |
|
1800 |
} |
|
1801 |
||
1802 |
#ifndef PRODUCT |
|
1803 |
void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1804 |
if (!ra_) |
|
1805 |
st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
|
|
1806 |
else |
|
1807 |
implementation(NULL, ra_, false, st); |
|
1808 |
} |
|
1809 |
#endif |
|
1810 |
||
1811 |
void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1812 |
implementation(&cbuf, ra_, false, NULL); |
|
1813 |
} |
|
1814 |
||
1815 |
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
|
|
1816 |
return implementation(NULL, ra_, true, NULL); |
|
1817 |
} |
|
1818 |
||
1819 |
#if 0 // TODO: PPC port |
|
1820 |
ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
|
|
1821 |
#ifndef PRODUCT |
|
1822 |
if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; |
|
1823 |
#endif |
|
1824 |
assert(ra_->node_regs_max_index() != 0, ""); |
|
1825 |
||
1826 |
// Get registers to move. |
|
1827 |
OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); |
|
1828 |
OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); |
|
1829 |
OptoReg::Name dst_hi = ra_->get_reg_second(n); |
|
1830 |
OptoReg::Name dst_lo = ra_->get_reg_first(n); |
|
1831 |
||
1832 |
enum RC src_lo_rc = rc_class(src_lo); |
|
1833 |
enum RC dst_lo_rc = rc_class(dst_lo); |
|
1834 |
||
1835 |
if (src_lo == dst_lo && src_hi == dst_hi) |
|
1836 |
return ppc64Opcode_none; // Self copy, no move. |
|
1837 |
||
1838 |
// -------------------------------------- |
|
1839 |
// Memory->Memory Spill. Use R0 to hold the value. |
|
1840 |
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
|
|
1841 |
return ppc64Opcode_compound; |
|
1842 |
} |
|
1843 |
||
1844 |
// -------------------------------------- |
|
1845 |
// Check for float->int copy; requires a trip through memory. |
|
1846 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
|
|
1847 |
Unimplemented(); |
|
1848 |
} |
|
1849 |
||
1850 |
// -------------------------------------- |
|
1851 |
// Check for integer reg-reg copy. |
|
1852 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
|
|
1853 |
Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); |
|
1854 |
Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); |
|
1855 |
if (Rsrc == Rdst) {
|
|
1856 |
return ppc64Opcode_none; |
|
1857 |
} else {
|
|
1858 |
return ppc64Opcode_or; |
|
1859 |
} |
|
1860 |
} |
|
1861 |
||
1862 |
// Check for integer store. |
|
1863 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
|
|
1864 |
if (src_hi != OptoReg::Bad) {
|
|
1865 |
return ppc64Opcode_std; |
|
1866 |
} else {
|
|
1867 |
return ppc64Opcode_stw; |
|
1868 |
} |
|
1869 |
} |
|
1870 |
||
1871 |
// Check for integer load. |
|
1872 |
if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
|
|
1873 |
if (src_hi != OptoReg::Bad) {
|
|
1874 |
return ppc64Opcode_ld; |
|
1875 |
} else {
|
|
1876 |
return ppc64Opcode_lwz; |
|
1877 |
} |
|
1878 |
} |
|
1879 |
||
1880 |
// Check for float reg-reg copy. |
|
1881 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
|
|
1882 |
return ppc64Opcode_fmr; |
|
1883 |
} |
|
1884 |
||
1885 |
// Check for float store. |
|
1886 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
|
|
1887 |
if (src_hi != OptoReg::Bad) {
|
|
1888 |
return ppc64Opcode_stfd; |
|
1889 |
} else {
|
|
1890 |
return ppc64Opcode_stfs; |
|
1891 |
} |
|
1892 |
} |
|
1893 |
||
1894 |
// Check for float load. |
|
1895 |
if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
|
|
1896 |
if (src_hi != OptoReg::Bad) {
|
|
1897 |
return ppc64Opcode_lfd; |
|
1898 |
} else {
|
|
1899 |
return ppc64Opcode_lfs; |
|
1900 |
} |
|
1901 |
} |
|
1902 |
||
1903 |
// -------------------------------------------------------------------- |
|
1904 |
// Check for hi bits still needing moving. Only happens for misaligned |
|
1905 |
// arguments to native calls. |
|
1906 |
if (src_hi == dst_hi) |
|
1907 |
return ppc64Opcode_none; // Self copy; no move. |
|
1908 |
||
1909 |
ShouldNotReachHere(); |
|
1910 |
return ppc64Opcode_undefined; |
|
1911 |
} |
|
1912 |
#endif // PPC port |
|
1913 |
||
1914 |
#ifndef PRODUCT |
|
1915 |
void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1916 |
st->print("NOP \t// %d nops to pad for loops.", _count);
|
|
1917 |
} |
|
1918 |
#endif |
|
1919 |
||
1920 |
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
|
|
1921 |
MacroAssembler _masm(&cbuf); |
|
1922 |
// _count contains the number of nops needed for padding. |
|
1923 |
for (int i = 0; i < _count; i++) {
|
|
1924 |
__ nop(); |
|
1925 |
} |
|
1926 |
} |
|
1927 |
||
1928 |
uint MachNopNode::size(PhaseRegAlloc *ra_) const {
|
|
1929 |
return _count * 4; |
|
1930 |
} |
|
1931 |
||
1932 |
#ifndef PRODUCT |
|
1933 |
void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1934 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1935 |
int reg = ra_->get_reg_first(this); |
|
1936 |
st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
|
|
1937 |
} |
|
1938 |
#endif |
|
1939 |
||
1940 |
void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1941 |
MacroAssembler _masm(&cbuf); |
|
1942 |
||
1943 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1944 |
int reg = ra_->get_encode(this); |
|
1945 |
||
1946 |
if (Assembler::is_simm(offset, 16)) {
|
|
1947 |
__ addi(as_Register(reg), R1, offset); |
|
1948 |
} else {
|
|
1949 |
ShouldNotReachHere(); |
|
1950 |
} |
|
1951 |
} |
|
1952 |
||
1953 |
uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
|
|
1954 |
// BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). |
|
1955 |
return 4; |
|
1956 |
} |
|
1957 |
||
1958 |
#ifndef PRODUCT |
|
1959 |
void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
1960 |
st->print_cr("---- MachUEPNode ----");
|
|
1961 |
st->print_cr("...");
|
|
1962 |
} |
|
1963 |
#endif |
|
1964 |
||
1965 |
void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1966 |
// This is the unverified entry point. |
|
1967 |
MacroAssembler _masm(&cbuf); |
|
1968 |
||
1969 |
// Inline_cache contains a klass. |
|
1970 |
Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); |
|
1971 |
Register receiver_klass = R0; // tmp |
|
1972 |
||
1973 |
assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); |
|
1974 |
assert(R11_scratch1 == R11, "need prologue scratch register"); |
|
1975 |
||
1976 |
// Check for NULL argument if we don't have implicit null checks. |
|
1977 |
if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
|
|
1978 |
if (TrapBasedNullChecks) {
|
|
1979 |
__ trap_null_check(R3_ARG1); |
|
1980 |
} else {
|
|
1981 |
Label valid; |
|
1982 |
__ cmpdi(CCR0, R3_ARG1, 0); |
|
1983 |
__ bne_predict_taken(CCR0, valid); |
|
1984 |
// We have a null argument, branch to ic_miss_stub. |
|
1985 |
__ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), |
|
1986 |
relocInfo::runtime_call_type); |
|
1987 |
__ bind(valid); |
|
1988 |
} |
|
1989 |
} |
|
1990 |
// Assume argument is not NULL, load klass from receiver. |
|
1991 |
__ load_klass(receiver_klass, R3_ARG1); |
|
1992 |
||
1993 |
if (TrapBasedICMissChecks) {
|
|
1994 |
__ trap_ic_miss_check(receiver_klass, ic_klass); |
|
1995 |
} else {
|
|
1996 |
Label valid; |
|
1997 |
__ cmpd(CCR0, receiver_klass, ic_klass); |
|
1998 |
__ beq_predict_taken(CCR0, valid); |
|
1999 |
// We have an unexpected klass, branch to ic_miss_stub. |
|
2000 |
__ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), |
|
2001 |
relocInfo::runtime_call_type); |
|
2002 |
__ bind(valid); |
|
2003 |
} |
|
2004 |
||
2005 |
// Argument is valid and klass is as expected, continue. |
|
2006 |
} |
|
2007 |
||
2008 |
#if 0 // TODO: PPC port |
|
2009 |
// Optimize UEP code on z (save a load_const() call in main path). |
|
2010 |
int MachUEPNode::ep_offset() {
|
|
2011 |
return 0; |
|
2012 |
} |
|
2013 |
#endif |
|
2014 |
||
2015 |
uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
|
|
2016 |
// Variable size. Determine dynamically. |
|
2017 |
return MachNode::size(ra_); |
|
2018 |
} |
|
2019 |
||
2020 |
//============================================================================= |
|
2021 |
||
2022 |
uint size_exception_handler() {
|
|
2023 |
// The exception_handler is a b64_patchable. |
|
2024 |
return MacroAssembler::b64_patchable_size; |
|
2025 |
} |
|
2026 |
||
2027 |
uint size_deopt_handler() {
|
|
2028 |
// The deopt_handler is a bl64_patchable. |
|
2029 |
return MacroAssembler::bl64_patchable_size; |
|
2030 |
} |
|
2031 |
||
2032 |
int emit_exception_handler(CodeBuffer &cbuf) {
|
|
2033 |
MacroAssembler _masm(&cbuf); |
|
2034 |
||
2035 |
address base = __ start_a_stub(size_exception_handler()); |
|
2036 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
2037 |
||
2038 |
int offset = __ offset(); |
|
2039 |
__ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), |
|
2040 |
relocInfo::runtime_call_type); |
|
2041 |
assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); |
|
2042 |
__ end_a_stub(); |
|
2043 |
||
2044 |
return offset; |
|
2045 |
} |
|
2046 |
||
2047 |
// The deopt_handler is like the exception handler, but it calls to |
|
2048 |
// the deoptimization blob instead of jumping to the exception blob. |
|
2049 |
int emit_deopt_handler(CodeBuffer& cbuf) {
|
|
2050 |
MacroAssembler _masm(&cbuf); |
|
2051 |
||
2052 |
address base = __ start_a_stub(size_deopt_handler()); |
|
2053 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
2054 |
||
2055 |
int offset = __ offset(); |
|
2056 |
__ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), |
|
2057 |
relocInfo::runtime_call_type); |
|
2058 |
assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); |
|
2059 |
__ end_a_stub(); |
|
2060 |
||
2061 |
return offset; |
|
2062 |
} |
|
2063 |
||
2064 |
//============================================================================= |
|
2065 |
||
2066 |
// Use a frame slots bias for frameless methods if accessing the stack. |
|
2067 |
static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
|
|
2068 |
if (as_Register(reg_enc) == R1_SP) {
|
|
2069 |
return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); |
|
2070 |
} |
|
2071 |
return 0; |
|
2072 |
} |
|
2073 |
||
2074 |
const bool Matcher::match_rule_supported(int opcode) {
|
|
2075 |
if (!has_match_rule(opcode)) |
|
2076 |
return false; |
|
2077 |
||
2078 |
switch (opcode) {
|
|
|
22879
177361c49b26
8035394: PPC64: Make usage of intrinsic dsqrt depend on processor recognition.
goetz
parents:
22874
diff
changeset
|
2079 |
case Op_SqrtD: |
|
177361c49b26
8035394: PPC64: Make usage of intrinsic dsqrt depend on processor recognition.
goetz
parents:
22874
diff
changeset
|
2080 |
return VM_Version::has_fsqrt(); |
| 22861 | 2081 |
case Op_CountLeadingZerosI: |
2082 |
case Op_CountLeadingZerosL: |
|
2083 |
case Op_CountTrailingZerosI: |
|
2084 |
case Op_CountTrailingZerosL: |
|
2085 |
if (!UseCountLeadingZerosInstructionsPPC64) |
|
2086 |
return false; |
|
2087 |
break; |
|
2088 |
||
2089 |
case Op_PopCountI: |
|
2090 |
case Op_PopCountL: |
|
2091 |
return (UsePopCountInstruction && VM_Version::has_popcntw()); |
|
2092 |
||
2093 |
case Op_StrComp: |
|
2094 |
return SpecialStringCompareTo; |
|
2095 |
case Op_StrEquals: |
|
2096 |
return SpecialStringEquals; |
|
2097 |
case Op_StrIndexOf: |
|
2098 |
return SpecialStringIndexOf; |
|
2099 |
} |
|
2100 |
||
2101 |
return true; // Per default match rules are supported. |
|
2102 |
} |
|
2103 |
||
2104 |
int Matcher::regnum_to_fpu_offset(int regnum) {
|
|
2105 |
// No user for this method? |
|
2106 |
Unimplemented(); |
|
2107 |
return 999; |
|
2108 |
} |
|
2109 |
||
2110 |
const bool Matcher::convL2FSupported(void) {
|
|
2111 |
// fcfids can do the conversion (>= Power7). |
|
2112 |
// fcfid + frsp showed rounding problem when result should be 0x3f800001. |
|
2113 |
return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. |
|
2114 |
} |
|
2115 |
||
2116 |
// Vector width in bytes. |
|
2117 |
const int Matcher::vector_width_in_bytes(BasicType bt) {
|
|
2118 |
assert(MaxVectorSize == 8, ""); |
|
2119 |
return 8; |
|
2120 |
} |
|
2121 |
||
2122 |
// Vector ideal reg. |
|
2123 |
const int Matcher::vector_ideal_reg(int size) {
|
|
2124 |
assert(MaxVectorSize == 8 && size == 8, ""); |
|
2125 |
return Op_RegL; |
|
2126 |
} |
|
2127 |
||
2128 |
const int Matcher::vector_shift_count_ideal_reg(int size) {
|
|
2129 |
fatal("vector shift is not supported");
|
|
2130 |
return Node::NotAMachineReg; |
|
2131 |
} |
|
2132 |
||
2133 |
// Limits on vector size (number of elements) loaded into vector. |
|
2134 |
const int Matcher::max_vector_size(const BasicType bt) {
|
|
2135 |
assert(is_java_primitive(bt), "only primitive type vectors"); |
|
2136 |
return vector_width_in_bytes(bt)/type2aelembytes(bt); |
|
2137 |
} |
|
2138 |
||
2139 |
const int Matcher::min_vector_size(const BasicType bt) {
|
|
2140 |
return max_vector_size(bt); // Same as max. |
|
2141 |
} |
|
2142 |
||
2143 |
// PPC doesn't support misaligned vectors store/load. |
|
2144 |
const bool Matcher::misaligned_vectors_ok() {
|
|
2145 |
return false; |
|
2146 |
} |
|
2147 |
||
|
22874
9918cae8623d
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
goetz
parents:
22867
diff
changeset
|
2148 |
// PPC AES support not yet implemented |
|
9918cae8623d
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
goetz
parents:
22867
diff
changeset
|
2149 |
const bool Matcher::pass_original_key_for_aes() {
|
|
9918cae8623d
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
goetz
parents:
22867
diff
changeset
|
2150 |
return false; |
|
9918cae8623d
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
goetz
parents:
22867
diff
changeset
|
2151 |
} |
|
9918cae8623d
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
goetz
parents:
22867
diff
changeset
|
2152 |
|
| 22861 | 2153 |
// RETURNS: whether this branch offset is short enough that a short |
2154 |
// branch can be used. |
|
2155 |
// |
|
2156 |
// If the platform does not provide any short branch variants, then |
|
2157 |
// this method should return `false' for offset 0. |
|
2158 |
// |
|
2159 |
// `Compile::Fill_buffer' will decide on basis of this information |
|
2160 |
// whether to do the pass `Compile::Shorten_branches' at all. |
|
2161 |
// |
|
2162 |
// And `Compile::Shorten_branches' will decide on basis of this |
|
2163 |
// information whether to replace particular branch sites by short |
|
2164 |
// ones. |
|
2165 |
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
|
|
2166 |
// Is the offset within the range of a ppc64 pc relative branch? |
|
2167 |
bool b; |
|
2168 |
||
2169 |
const int safety_zone = 3 * BytesPerInstWord; |
|
2170 |
b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), |
|
2171 |
29 - 16 + 1 + 2); |
|
2172 |
return b; |
|
2173 |
} |
|
2174 |
||
2175 |
const bool Matcher::isSimpleConstant64(jlong value) {
|
|
2176 |
// Probably always true, even if a temp register is required. |
|
2177 |
return true; |
|
2178 |
} |
|
2179 |
/* TODO: PPC port |
|
2180 |
// Make a new machine dependent decode node (with its operands). |
|
2181 |
MachTypeNode *Matcher::make_decode_node(Compile *C) {
|
|
2182 |
assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, |
|
2183 |
"This method is only implemented for unscaled cOops mode so far"); |
|
2184 |
MachTypeNode *decode = new (C) decodeN_unscaledNode(); |
|
2185 |
decode->set_opnd_array(0, new (C) iRegPdstOper()); |
|
2186 |
decode->set_opnd_array(1, new (C) iRegNsrcOper()); |
|
2187 |
return decode; |
|
2188 |
} |
|
2189 |
*/ |
|
2190 |
// Threshold size for cleararray. |
|
2191 |
const int Matcher::init_array_short_size = 8 * BytesPerLong; |
|
2192 |
||
2193 |
// false => size gets scaled to BytesPerLong, ok. |
|
2194 |
const bool Matcher::init_array_count_is_in_bytes = false; |
|
2195 |
||
2196 |
// Use conditional move (CMOVL) on Power7. |
|
2197 |
const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
|
|
2198 |
||
2199 |
// Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. |
|
2200 |
// fsel doesn't accept a condition register as input, so this would be slightly different. |
|
2201 |
const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
|
|
2202 |
||
2203 |
// Power6 requires postalloc expand (see block.cpp for description of postalloc expand). |
|
2204 |
const bool Matcher::require_postalloc_expand = true; |
|
2205 |
||
2206 |
// Should the Matcher clone shifts on addressing modes, expecting them to |
|
2207 |
// be subsumed into complex addressing expressions or compute them into |
|
2208 |
// registers? True for Intel but false for most RISCs. |
|
2209 |
const bool Matcher::clone_shift_expressions = false; |
|
2210 |
||
2211 |
// Do we need to mask the count passed to shift instructions or does |
|
2212 |
// the cpu only look at the lower 5/6 bits anyway? |
|
2213 |
// Off, as masks are generated in expand rules where required. |
|
2214 |
// Constant shift counts are handled in Ideal phase. |
|
2215 |
const bool Matcher::need_masked_shift_count = false; |
|
2216 |
||
2217 |
// This affects two different things: |
|
2218 |
// - how Decode nodes are matched |
|
2219 |
// - how ImplicitNullCheck opportunities are recognized |
|
2220 |
// If true, the matcher will try to remove all Decodes and match them |
|
2221 |
// (as operands) into nodes. NullChecks are not prepared to deal with |
|
2222 |
// Decodes by final_graph_reshaping(). |
|
2223 |
// If false, final_graph_reshaping() forces the decode behind the Cmp |
|
2224 |
// for a NullCheck. The matcher matches the Decode node into a register. |
|
2225 |
// Implicit_null_check optimization moves the Decode along with the |
|
2226 |
// memory operation back up before the NullCheck. |
|
2227 |
bool Matcher::narrow_oop_use_complex_address() {
|
|
2228 |
// TODO: PPC port if (MatchDecodeNodes) return true; |
|
2229 |
return false; |
|
2230 |
} |
|
2231 |
||
2232 |
bool Matcher::narrow_klass_use_complex_address() {
|
|
2233 |
NOT_LP64(ShouldNotCallThis()); |
|
2234 |
assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
2235 |
// TODO: PPC port if (MatchDecodeNodes) return true; |
|
2236 |
return false; |
|
2237 |
} |
|
2238 |
||
2239 |
// Is it better to copy float constants, or load them directly from memory? |
|
2240 |
// Intel can load a float constant from a direct address, requiring no |
|
2241 |
// extra registers. Most RISCs will have to materialize an address into a |
|
2242 |
// register first, so they would do better to copy the constant from stack. |
|
2243 |
const bool Matcher::rematerialize_float_constants = false; |
|
2244 |
||
2245 |
// If CPU can load and store mis-aligned doubles directly then no fixup is |
|
2246 |
// needed. Else we split the double into 2 integer pieces and move it |
|
2247 |
// piece-by-piece. Only happens when passing doubles into C code as the |
|
2248 |
// Java calling convention forces doubles to be aligned. |
|
2249 |
const bool Matcher::misaligned_doubles_ok = true; |
|
2250 |
||
2251 |
void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
|
|
2252 |
Unimplemented(); |
|
2253 |
} |
|
2254 |
||
2255 |
// Advertise here if the CPU requires explicit rounding operations |
|
2256 |
// to implement the UseStrictFP mode. |
|
2257 |
const bool Matcher::strict_fp_requires_explicit_rounding = false; |
|
2258 |
||
2259 |
// Do floats take an entire double register or just half? |
|
2260 |
// |
|
2261 |
// A float occupies a ppc64 double register. For the allocator, a |
|
2262 |
// ppc64 double register appears as a pair of float registers. |
|
2263 |
bool Matcher::float_in_double() { return true; }
|
|
2264 |
||
2265 |
// Do ints take an entire long register or just half? |
|
2266 |
// The relevant question is how the int is callee-saved: |
|
2267 |
// the whole long is written but de-opt'ing will have to extract |
|
2268 |
// the relevant 32 bits. |
|
2269 |
const bool Matcher::int_in_long = true; |
|
2270 |
||
2271 |
// Constants for c2c and c calling conventions. |
|
2272 |
||
2273 |
const MachRegisterNumbers iarg_reg[8] = {
|
|
2274 |
R3_num, R4_num, R5_num, R6_num, |
|
2275 |
R7_num, R8_num, R9_num, R10_num |
|
2276 |
}; |
|
2277 |
||
2278 |
const MachRegisterNumbers farg_reg[13] = {
|
|
2279 |
F1_num, F2_num, F3_num, F4_num, |
|
2280 |
F5_num, F6_num, F7_num, F8_num, |
|
2281 |
F9_num, F10_num, F11_num, F12_num, |
|
2282 |
F13_num |
|
2283 |
}; |
|
2284 |
||
2285 |
const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); |
|
2286 |
||
2287 |
const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); |
|
2288 |
||
2289 |
// Return whether or not this register is ever used as an argument. This |
|
2290 |
// function is used on startup to build the trampoline stubs in generateOptoStub. |
|
2291 |
// Registers not mentioned will be killed by the VM call in the trampoline, and |
|
2292 |
// arguments in those registers not be available to the callee. |
|
2293 |
bool Matcher::can_be_java_arg(int reg) {
|
|
2294 |
// We return true for all registers contained in iarg_reg[] and |
|
2295 |
// farg_reg[] and their virtual halves. |
|
2296 |
// We must include the virtual halves in order to get STDs and LDs |
|
2297 |
// instead of STWs and LWs in the trampoline stubs. |
|
2298 |
||
2299 |
if ( reg == R3_num || reg == R3_H_num |
|
2300 |
|| reg == R4_num || reg == R4_H_num |
|
2301 |
|| reg == R5_num || reg == R5_H_num |
|
2302 |
|| reg == R6_num || reg == R6_H_num |
|
2303 |
|| reg == R7_num || reg == R7_H_num |
|
2304 |
|| reg == R8_num || reg == R8_H_num |
|
2305 |
|| reg == R9_num || reg == R9_H_num |
|
2306 |
|| reg == R10_num || reg == R10_H_num) |
|
2307 |
return true; |
|
2308 |
||
2309 |
if ( reg == F1_num || reg == F1_H_num |
|
2310 |
|| reg == F2_num || reg == F2_H_num |
|
2311 |
|| reg == F3_num || reg == F3_H_num |
|
2312 |
|| reg == F4_num || reg == F4_H_num |
|
2313 |
|| reg == F5_num || reg == F5_H_num |
|
2314 |
|| reg == F6_num || reg == F6_H_num |
|
2315 |
|| reg == F7_num || reg == F7_H_num |
|
2316 |
|| reg == F8_num || reg == F8_H_num |
|
2317 |
|| reg == F9_num || reg == F9_H_num |
|
2318 |
|| reg == F10_num || reg == F10_H_num |
|
2319 |
|| reg == F11_num || reg == F11_H_num |
|
2320 |
|| reg == F12_num || reg == F12_H_num |
|
2321 |
|| reg == F13_num || reg == F13_H_num) |
|
2322 |
return true; |
|
2323 |
||
2324 |
return false; |
|
2325 |
} |
|
2326 |
||
2327 |
bool Matcher::is_spillable_arg(int reg) {
|
|
2328 |
return can_be_java_arg(reg); |
|
2329 |
} |
|
2330 |
||
2331 |
bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
|
|
2332 |
return false; |
|
2333 |
} |
|
2334 |
||
2335 |
// Register for DIVI projection of divmodI. |
|
2336 |
RegMask Matcher::divI_proj_mask() {
|
|
2337 |
ShouldNotReachHere(); |
|
2338 |
return RegMask(); |
|
2339 |
} |
|
2340 |
||
2341 |
// Register for MODI projection of divmodI. |
|
2342 |
RegMask Matcher::modI_proj_mask() {
|
|
2343 |
ShouldNotReachHere(); |
|
2344 |
return RegMask(); |
|
2345 |
} |
|
2346 |
||
2347 |
// Register for DIVL projection of divmodL. |
|
2348 |
RegMask Matcher::divL_proj_mask() {
|
|
2349 |
ShouldNotReachHere(); |
|
2350 |
return RegMask(); |
|
2351 |
} |
|
2352 |
||
2353 |
// Register for MODL projection of divmodL. |
|
2354 |
RegMask Matcher::modL_proj_mask() {
|
|
2355 |
ShouldNotReachHere(); |
|
2356 |
return RegMask(); |
|
2357 |
} |
|
2358 |
||
2359 |
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
|
|
2360 |
return RegMask(); |
|
2361 |
} |
|
2362 |
||
2363 |
%} |
|
2364 |
||
2365 |
//----------ENCODING BLOCK----------------------------------------------------- |
|
2366 |
// This block specifies the encoding classes used by the compiler to output |
|
2367 |
// byte streams. Encoding classes are parameterized macros used by |
|
2368 |
// Machine Instruction Nodes in order to generate the bit encoding of the |
|
2369 |
// instruction. Operands specify their base encoding interface with the |
|
2370 |
// interface keyword. There are currently supported four interfaces, |
|
2371 |
// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an |
|
2372 |
// operand to generate a function which returns its register number when |
|
2373 |
// queried. CONST_INTER causes an operand to generate a function which |
|
2374 |
// returns the value of the constant when queried. MEMORY_INTER causes an |
|
2375 |
// operand to generate four functions which return the Base Register, the |
|
2376 |
// Index Register, the Scale Value, and the Offset Value of the operand when |
|
2377 |
// queried. COND_INTER causes an operand to generate six functions which |
|
2378 |
// return the encoding code (ie - encoding bits for the instruction) |
|
2379 |
// associated with each basic boolean condition for a conditional instruction. |
|
2380 |
// |
|
2381 |
// Instructions specify two basic values for encoding. Again, a function |
|
2382 |
// is available to check if the constant displacement is an oop. They use the |
|
2383 |
// ins_encode keyword to specify their encoding classes (which must be |
|
2384 |
// a sequence of enc_class names, and their parameters, specified in |
|
2385 |
// the encoding block), and they use the |
|
2386 |
// opcode keyword to specify, in order, their primary, secondary, and |
|
2387 |
// tertiary opcode. Only the opcode sections which a particular instruction |
|
2388 |
// needs for encoding need to be specified. |
|
2389 |
encode %{
|
|
2390 |
enc_class enc_unimplemented %{
|
|
2391 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2392 |
MacroAssembler _masm(&cbuf); |
|
2393 |
__ unimplemented("Unimplemented mach node encoding in AD file.", 13);
|
|
2394 |
%} |
|
2395 |
||
2396 |
enc_class enc_untested %{
|
|
2397 |
#ifdef ASSERT |
|
2398 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2399 |
MacroAssembler _masm(&cbuf); |
|
2400 |
__ untested("Untested mach node encoding in AD file.");
|
|
2401 |
#else |
|
2402 |
// TODO: PPC port $archOpcode(ppc64Opcode_none); |
|
2403 |
#endif |
|
2404 |
%} |
|
2405 |
||
2406 |
enc_class enc_lbz(iRegIdst dst, memory mem) %{
|
|
2407 |
// TODO: PPC port $archOpcode(ppc64Opcode_lbz); |
|
2408 |
MacroAssembler _masm(&cbuf); |
|
2409 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2410 |
__ lbz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2411 |
%} |
|
2412 |
||
2413 |
// Load acquire. |
|
2414 |
enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
|
|
2415 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2416 |
MacroAssembler _masm(&cbuf); |
|
2417 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2418 |
__ lbz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2419 |
__ twi_0($dst$$Register); |
|
2420 |
__ isync(); |
|
2421 |
%} |
|
2422 |
||
2423 |
enc_class enc_lhz(iRegIdst dst, memory mem) %{
|
|
2424 |
// TODO: PPC port $archOpcode(ppc64Opcode_lhz); |
|
2425 |
||
2426 |
MacroAssembler _masm(&cbuf); |
|
2427 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2428 |
__ lhz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2429 |
%} |
|
2430 |
||
2431 |
// Load acquire. |
|
2432 |
enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
|
|
2433 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2434 |
||
2435 |
MacroAssembler _masm(&cbuf); |
|
2436 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2437 |
__ lhz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2438 |
__ twi_0($dst$$Register); |
|
2439 |
__ isync(); |
|
2440 |
%} |
|
2441 |
||
2442 |
enc_class enc_lwz(iRegIdst dst, memory mem) %{
|
|
2443 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwz); |
|
2444 |
||
2445 |
MacroAssembler _masm(&cbuf); |
|
2446 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2447 |
__ lwz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2448 |
%} |
|
2449 |
||
2450 |
// Load acquire. |
|
2451 |
enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
|
|
2452 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2453 |
||
2454 |
MacroAssembler _masm(&cbuf); |
|
2455 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2456 |
__ lwz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2457 |
__ twi_0($dst$$Register); |
|
2458 |
__ isync(); |
|
2459 |
%} |
|
2460 |
||
2461 |
enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
|
|
2462 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2463 |
MacroAssembler _masm(&cbuf); |
|
2464 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2465 |
// Operand 'ds' requires 4-alignment. |
|
2466 |
assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2467 |
__ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
2468 |
%} |
|
2469 |
||
2470 |
// Load acquire. |
|
2471 |
enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
|
|
2472 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2473 |
MacroAssembler _masm(&cbuf); |
|
2474 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2475 |
// Operand 'ds' requires 4-alignment. |
|
2476 |
assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2477 |
__ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
2478 |
__ twi_0($dst$$Register); |
|
2479 |
__ isync(); |
|
2480 |
%} |
|
2481 |
||
2482 |
enc_class enc_lfd(RegF dst, memory mem) %{
|
|
2483 |
// TODO: PPC port $archOpcode(ppc64Opcode_lfd); |
|
2484 |
MacroAssembler _masm(&cbuf); |
|
2485 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2486 |
__ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2487 |
%} |
|
2488 |
||
2489 |
enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
|
|
2490 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2491 |
||
2492 |
MacroAssembler _masm(&cbuf); |
|
2493 |
int toc_offset = 0; |
|
2494 |
||
2495 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
2496 |
address const_toc_addr; |
|
2497 |
// Create a non-oop constant, no relocation needed. |
|
2498 |
// If it is an IC, it has a virtual_call_Relocation. |
|
2499 |
const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2500 |
||
2501 |
// Get the constant's TOC offset. |
|
2502 |
toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2503 |
||
2504 |
// Keep the current instruction offset in mind. |
|
2505 |
((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); |
|
2506 |
} |
|
2507 |
||
2508 |
__ ld($dst$$Register, toc_offset, $toc$$Register); |
|
2509 |
%} |
|
2510 |
||
2511 |
enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
|
|
2512 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
2513 |
||
2514 |
MacroAssembler _masm(&cbuf); |
|
2515 |
||
2516 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
2517 |
address const_toc_addr; |
|
2518 |
// Create a non-oop constant, no relocation needed. |
|
2519 |
// If it is an IC, it has a virtual_call_Relocation. |
|
2520 |
const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2521 |
||
2522 |
// Get the constant's TOC offset. |
|
2523 |
const int toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2524 |
// Store the toc offset of the constant. |
|
2525 |
((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; |
|
2526 |
||
2527 |
// Also keep the current instruction offset in mind. |
|
2528 |
((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); |
|
2529 |
} |
|
2530 |
||
2531 |
__ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); |
|
2532 |
%} |
|
2533 |
||
2534 |
%} // encode |
|
2535 |
||
2536 |
source %{
|
|
2537 |
||
2538 |
typedef struct {
|
|
2539 |
loadConL_hiNode *_large_hi; |
|
2540 |
loadConL_loNode *_large_lo; |
|
2541 |
loadConLNode *_small; |
|
2542 |
MachNode *_last; |
|
2543 |
} loadConLNodesTuple; |
|
2544 |
||
2545 |
loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, |
|
2546 |
OptoReg::Name reg_second, OptoReg::Name reg_first) {
|
|
2547 |
loadConLNodesTuple nodes; |
|
2548 |
||
2549 |
const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2550 |
if (large_constant_pool) {
|
|
2551 |
// Create new nodes. |
|
2552 |
loadConL_hiNode *m1 = new (C) loadConL_hiNode(); |
|
2553 |
loadConL_loNode *m2 = new (C) loadConL_loNode(); |
|
2554 |
||
2555 |
// inputs for new nodes |
|
2556 |
m1->add_req(NULL, toc); |
|
2557 |
m2->add_req(NULL, m1); |
|
2558 |
||
2559 |
// operands for new nodes |
|
2560 |
m1->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2561 |
m1->_opnds[1] = immSrc; // src |
|
2562 |
m1->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2563 |
m2->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2564 |
m2->_opnds[1] = immSrc; // src |
|
2565 |
m2->_opnds[2] = new (C) iRegLdstOper(); // base |
|
2566 |
||
2567 |
// Initialize ins_attrib TOC fields. |
|
2568 |
m1->_const_toc_offset = -1; |
|
2569 |
m2->_const_toc_offset_hi_node = m1; |
|
2570 |
||
2571 |
// Initialize ins_attrib instruction offset. |
|
2572 |
m1->_cbuf_insts_offset = -1; |
|
2573 |
||
2574 |
// register allocation for new nodes |
|
2575 |
ra_->set_pair(m1->_idx, reg_second, reg_first); |
|
2576 |
ra_->set_pair(m2->_idx, reg_second, reg_first); |
|
2577 |
||
2578 |
// Create result. |
|
2579 |
nodes._large_hi = m1; |
|
2580 |
nodes._large_lo = m2; |
|
2581 |
nodes._small = NULL; |
|
2582 |
nodes._last = nodes._large_lo; |
|
2583 |
assert(m2->bottom_type()->isa_long(), "must be long"); |
|
2584 |
} else {
|
|
2585 |
loadConLNode *m2 = new (C) loadConLNode(); |
|
2586 |
||
2587 |
// inputs for new nodes |
|
2588 |
m2->add_req(NULL, toc); |
|
2589 |
||
2590 |
// operands for new nodes |
|
2591 |
m2->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2592 |
m2->_opnds[1] = immSrc; // src |
|
2593 |
m2->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2594 |
||
2595 |
// Initialize ins_attrib instruction offset. |
|
2596 |
m2->_cbuf_insts_offset = -1; |
|
2597 |
||
2598 |
// register allocation for new nodes |
|
2599 |
ra_->set_pair(m2->_idx, reg_second, reg_first); |
|
2600 |
||
2601 |
// Create result. |
|
2602 |
nodes._large_hi = NULL; |
|
2603 |
nodes._large_lo = NULL; |
|
2604 |
nodes._small = m2; |
|
2605 |
nodes._last = nodes._small; |
|
2606 |
assert(m2->bottom_type()->isa_long(), "must be long"); |
|
2607 |
} |
|
2608 |
||
2609 |
return nodes; |
|
2610 |
} |
|
2611 |
||
2612 |
%} // source |
|
2613 |
||
2614 |
encode %{
|
|
2615 |
// Postalloc expand emitter for loading a long constant from the method's TOC. |
|
2616 |
// Enc_class needed as consttanttablebase is not supported by postalloc |
|
2617 |
// expand. |
|
2618 |
enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
|
|
2619 |
// Create new nodes. |
|
2620 |
loadConLNodesTuple loadConLNodes = |
|
2621 |
loadConLNodesTuple_create(C, ra_, n_toc, op_src, |
|
2622 |
ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2623 |
||
2624 |
// Push new nodes. |
|
2625 |
if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); |
|
2626 |
if (loadConLNodes._last) nodes->push(loadConLNodes._last); |
|
2627 |
||
2628 |
// some asserts |
|
2629 |
assert(nodes->length() >= 1, "must have created at least 1 node"); |
|
2630 |
assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); |
|
2631 |
%} |
|
2632 |
||
2633 |
enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
|
|
2634 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2635 |
||
2636 |
MacroAssembler _masm(&cbuf); |
|
2637 |
int toc_offset = 0; |
|
2638 |
||
2639 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
2640 |
intptr_t val = $src$$constant; |
|
2641 |
relocInfo::relocType constant_reloc = $src->constant_reloc(); // src |
|
2642 |
address const_toc_addr; |
|
2643 |
if (constant_reloc == relocInfo::oop_type) {
|
|
2644 |
// Create an oop constant and a corresponding relocation. |
|
2645 |
AddressLiteral a = __ allocate_oop_address((jobject)val); |
|
2646 |
const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2647 |
__ relocate(a.rspec()); |
|
2648 |
} else if (constant_reloc == relocInfo::metadata_type) {
|
|
2649 |
AddressLiteral a = __ allocate_metadata_address((Metadata *)val); |
|
2650 |
const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2651 |
__ relocate(a.rspec()); |
|
2652 |
} else {
|
|
2653 |
// Create a non-oop constant, no relocation needed. |
|
2654 |
const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2655 |
} |
|
2656 |
||
2657 |
// Get the constant's TOC offset. |
|
2658 |
toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2659 |
} |
|
2660 |
||
2661 |
__ ld($dst$$Register, toc_offset, $toc$$Register); |
|
2662 |
%} |
|
2663 |
||
2664 |
enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
|
|
2665 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
2666 |
||
2667 |
MacroAssembler _masm(&cbuf); |
|
2668 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
2669 |
intptr_t val = $src$$constant; |
|
2670 |
relocInfo::relocType constant_reloc = $src->constant_reloc(); // src |
|
2671 |
address const_toc_addr; |
|
2672 |
if (constant_reloc == relocInfo::oop_type) {
|
|
2673 |
// Create an oop constant and a corresponding relocation. |
|
2674 |
AddressLiteral a = __ allocate_oop_address((jobject)val); |
|
2675 |
const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2676 |
__ relocate(a.rspec()); |
|
2677 |
} else if (constant_reloc == relocInfo::metadata_type) {
|
|
2678 |
AddressLiteral a = __ allocate_metadata_address((Metadata *)val); |
|
2679 |
const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2680 |
__ relocate(a.rspec()); |
|
2681 |
} else { // non-oop pointers, e.g. card mark base, heap top
|
|
2682 |
// Create a non-oop constant, no relocation needed. |
|
2683 |
const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2684 |
} |
|
2685 |
||
2686 |
// Get the constant's TOC offset. |
|
2687 |
const int toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2688 |
// Store the toc offset of the constant. |
|
2689 |
((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; |
|
2690 |
} |
|
2691 |
||
2692 |
__ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); |
|
2693 |
%} |
|
2694 |
||
2695 |
// Postalloc expand emitter for loading a ptr constant from the method's TOC. |
|
2696 |
// Enc_class needed as consttanttablebase is not supported by postalloc |
|
2697 |
// expand. |
|
2698 |
enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
|
|
2699 |
const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2700 |
if (large_constant_pool) {
|
|
2701 |
// Create new nodes. |
|
2702 |
loadConP_hiNode *m1 = new (C) loadConP_hiNode(); |
|
2703 |
loadConP_loNode *m2 = new (C) loadConP_loNode(); |
|
2704 |
||
2705 |
// inputs for new nodes |
|
2706 |
m1->add_req(NULL, n_toc); |
|
2707 |
m2->add_req(NULL, m1); |
|
2708 |
||
2709 |
// operands for new nodes |
|
2710 |
m1->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2711 |
m1->_opnds[1] = op_src; // src |
|
2712 |
m1->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2713 |
m2->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2714 |
m2->_opnds[1] = op_src; // src |
|
2715 |
m2->_opnds[2] = new (C) iRegLdstOper(); // base |
|
2716 |
||
2717 |
// Initialize ins_attrib TOC fields. |
|
2718 |
m1->_const_toc_offset = -1; |
|
2719 |
m2->_const_toc_offset_hi_node = m1; |
|
2720 |
||
2721 |
// Register allocation for new nodes. |
|
2722 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2723 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2724 |
||
2725 |
nodes->push(m1); |
|
2726 |
nodes->push(m2); |
|
2727 |
assert(m2->bottom_type()->isa_ptr(), "must be ptr"); |
|
2728 |
} else {
|
|
2729 |
loadConPNode *m2 = new (C) loadConPNode(); |
|
2730 |
||
2731 |
// inputs for new nodes |
|
2732 |
m2->add_req(NULL, n_toc); |
|
2733 |
||
2734 |
// operands for new nodes |
|
2735 |
m2->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2736 |
m2->_opnds[1] = op_src; // src |
|
2737 |
m2->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2738 |
||
2739 |
// Register allocation for new nodes. |
|
2740 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2741 |
||
2742 |
nodes->push(m2); |
|
2743 |
assert(m2->bottom_type()->isa_ptr(), "must be ptr"); |
|
2744 |
} |
|
2745 |
%} |
|
2746 |
||
2747 |
// Enc_class needed as consttanttablebase is not supported by postalloc |
|
2748 |
// expand. |
|
2749 |
enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
|
|
2750 |
bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2751 |
||
2752 |
MachNode *m2; |
|
2753 |
if (large_constant_pool) {
|
|
2754 |
m2 = new (C) loadConFCompNode(); |
|
2755 |
} else {
|
|
2756 |
m2 = new (C) loadConFNode(); |
|
2757 |
} |
|
2758 |
// inputs for new nodes |
|
2759 |
m2->add_req(NULL, n_toc); |
|
2760 |
||
2761 |
// operands for new nodes |
|
2762 |
m2->_opnds[0] = op_dst; |
|
2763 |
m2->_opnds[1] = op_src; |
|
2764 |
m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase |
|
2765 |
||
2766 |
// register allocation for new nodes |
|
2767 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2768 |
nodes->push(m2); |
|
2769 |
%} |
|
2770 |
||
2771 |
// Enc_class needed as consttanttablebase is not supported by postalloc |
|
2772 |
// expand. |
|
2773 |
enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
|
|
2774 |
bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2775 |
||
2776 |
MachNode *m2; |
|
2777 |
if (large_constant_pool) {
|
|
2778 |
m2 = new (C) loadConDCompNode(); |
|
2779 |
} else {
|
|
2780 |
m2 = new (C) loadConDNode(); |
|
2781 |
} |
|
2782 |
// inputs for new nodes |
|
2783 |
m2->add_req(NULL, n_toc); |
|
2784 |
||
2785 |
// operands for new nodes |
|
2786 |
m2->_opnds[0] = op_dst; |
|
2787 |
m2->_opnds[1] = op_src; |
|
2788 |
m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase |
|
2789 |
||
2790 |
// register allocation for new nodes |
|
2791 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2792 |
nodes->push(m2); |
|
2793 |
%} |
|
2794 |
||
2795 |
enc_class enc_stw(iRegIsrc src, memory mem) %{
|
|
2796 |
// TODO: PPC port $archOpcode(ppc64Opcode_stw); |
|
2797 |
MacroAssembler _masm(&cbuf); |
|
2798 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2799 |
__ stw($src$$Register, Idisp, $mem$$base$$Register); |
|
2800 |
%} |
|
2801 |
||
2802 |
enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
|
|
2803 |
// TODO: PPC port $archOpcode(ppc64Opcode_std); |
|
2804 |
MacroAssembler _masm(&cbuf); |
|
2805 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2806 |
// Operand 'ds' requires 4-alignment. |
|
2807 |
assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2808 |
__ std($src$$Register, Idisp, $mem$$base$$Register); |
|
2809 |
%} |
|
2810 |
||
2811 |
enc_class enc_stfs(RegF src, memory mem) %{
|
|
2812 |
// TODO: PPC port $archOpcode(ppc64Opcode_stfs); |
|
2813 |
MacroAssembler _masm(&cbuf); |
|
2814 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2815 |
__ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2816 |
%} |
|
2817 |
||
2818 |
enc_class enc_stfd(RegF src, memory mem) %{
|
|
2819 |
// TODO: PPC port $archOpcode(ppc64Opcode_stfd); |
|
2820 |
MacroAssembler _masm(&cbuf); |
|
2821 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2822 |
__ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2823 |
%} |
|
2824 |
||
2825 |
// Use release_store for card-marking to ensure that previous |
|
2826 |
// oop-stores are visible before the card-mark change. |
|
2827 |
enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
|
|
2828 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2829 |
// FIXME: Implement this as a cmove and use a fixed condition code |
|
2830 |
// register which is written on every transition to compiled code, |
|
2831 |
// e.g. in call-stub and when returning from runtime stubs. |
|
2832 |
// |
|
2833 |
// Proposed code sequence for the cmove implementation: |
|
2834 |
// |
|
2835 |
// Label skip_release; |
|
2836 |
// __ beq(CCRfixed, skip_release); |
|
2837 |
// __ release(); |
|
2838 |
// __ bind(skip_release); |
|
2839 |
// __ stb(card mark); |
|
2840 |
||
2841 |
MacroAssembler _masm(&cbuf); |
|
2842 |
Label skip_storestore; |
|
2843 |
||
2844 |
#if 0 // TODO: PPC port |
|
2845 |
// Check CMSCollectorCardTableModRefBSExt::_requires_release and do the |
|
2846 |
// StoreStore barrier conditionally. |
|
2847 |
__ lwz(R0, 0, $releaseFieldAddr$$Register); |
|
2848 |
__ cmpwi(CCR0, R0, 0); |
|
| 22867 | 2849 |
__ beq_predict_taken(CCR0, skip_storestore); |
| 22861 | 2850 |
#endif |
2851 |
__ li(R0, 0); |
|
2852 |
__ membar(Assembler::StoreStore); |
|
2853 |
#if 0 // TODO: PPC port |
|
2854 |
__ bind(skip_storestore); |
|
2855 |
#endif |
|
2856 |
||
2857 |
// Do the store. |
|
2858 |
if ($mem$$index == 0) {
|
|
2859 |
__ stb(R0, $mem$$disp, $mem$$base$$Register); |
|
2860 |
} else {
|
|
2861 |
assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); |
|
2862 |
__ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); |
|
2863 |
} |
|
2864 |
%} |
|
2865 |
||
2866 |
enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
|
|
2867 |
||
2868 |
if (VM_Version::has_isel()) {
|
|
2869 |
// use isel instruction with Power 7 |
|
2870 |
cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); |
|
2871 |
encodeP_subNode *n_sub_base = new (C) encodeP_subNode(); |
|
2872 |
encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); |
|
2873 |
cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode(); |
|
2874 |
||
2875 |
n_compare->add_req(n_region, n_src); |
|
2876 |
n_compare->_opnds[0] = op_crx; |
|
2877 |
n_compare->_opnds[1] = op_src; |
|
2878 |
n_compare->_opnds[2] = new (C) immL16Oper(0); |
|
2879 |
||
2880 |
n_sub_base->add_req(n_region, n_src); |
|
2881 |
n_sub_base->_opnds[0] = op_dst; |
|
2882 |
n_sub_base->_opnds[1] = op_src; |
|
2883 |
n_sub_base->_bottom_type = _bottom_type; |
|
2884 |
||
2885 |
n_shift->add_req(n_region, n_sub_base); |
|
2886 |
n_shift->_opnds[0] = op_dst; |
|
2887 |
n_shift->_opnds[1] = op_dst; |
|
2888 |
n_shift->_bottom_type = _bottom_type; |
|
2889 |
||
2890 |
n_cond_set->add_req(n_region, n_compare, n_shift); |
|
2891 |
n_cond_set->_opnds[0] = op_dst; |
|
2892 |
n_cond_set->_opnds[1] = op_crx; |
|
2893 |
n_cond_set->_opnds[2] = op_dst; |
|
2894 |
n_cond_set->_bottom_type = _bottom_type; |
|
2895 |
||
2896 |
ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
2897 |
ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2898 |
ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2899 |
ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2900 |
||
2901 |
nodes->push(n_compare); |
|
2902 |
nodes->push(n_sub_base); |
|
2903 |
nodes->push(n_shift); |
|
2904 |
nodes->push(n_cond_set); |
|
2905 |
||
2906 |
} else {
|
|
2907 |
// before Power 7 |
|
2908 |
moveRegNode *n_move = new (C) moveRegNode(); |
|
2909 |
cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); |
|
2910 |
encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); |
|
2911 |
cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode(); |
|
2912 |
||
2913 |
n_move->add_req(n_region, n_src); |
|
2914 |
n_move->_opnds[0] = op_dst; |
|
2915 |
n_move->_opnds[1] = op_src; |
|
2916 |
ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. |
|
2917 |
||
2918 |
n_compare->add_req(n_region, n_src); |
|
2919 |
n_compare->add_prec(n_move); |
|
2920 |
||
2921 |
n_compare->_opnds[0] = op_crx; |
|
2922 |
n_compare->_opnds[1] = op_src; |
|
2923 |
n_compare->_opnds[2] = new (C) immL16Oper(0); |
|
2924 |
||
2925 |
n_sub_base->add_req(n_region, n_compare, n_src); |
|
2926 |
n_sub_base->_opnds[0] = op_dst; |
|
2927 |
n_sub_base->_opnds[1] = op_crx; |
|
2928 |
n_sub_base->_opnds[2] = op_src; |
|
2929 |
n_sub_base->_bottom_type = _bottom_type; |
|
2930 |
||
2931 |
n_shift->add_req(n_region, n_sub_base); |
|
2932 |
n_shift->_opnds[0] = op_dst; |
|
2933 |
n_shift->_opnds[1] = op_dst; |
|
2934 |
n_shift->_bottom_type = _bottom_type; |
|
2935 |
||
2936 |
ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2937 |
ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
2938 |
ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2939 |
ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2940 |
||
2941 |
nodes->push(n_move); |
|
2942 |
nodes->push(n_compare); |
|
2943 |
nodes->push(n_sub_base); |
|
2944 |
nodes->push(n_shift); |
|
2945 |
} |
|
2946 |
||
2947 |
assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. |
|
2948 |
%} |
|
2949 |
||
2950 |
enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
|
|
2951 |
||
2952 |
encodeP_subNode *n1 = new (C) encodeP_subNode(); |
|
2953 |
n1->add_req(n_region, n_src); |
|
2954 |
n1->_opnds[0] = op_dst; |
|
2955 |
n1->_opnds[1] = op_src; |
|
2956 |
n1->_bottom_type = _bottom_type; |
|
2957 |
||
2958 |
encodeP_shiftNode *n2 = new (C) encodeP_shiftNode(); |
|
2959 |
n2->add_req(n_region, n1); |
|
2960 |
n2->_opnds[0] = op_dst; |
|
2961 |
n2->_opnds[1] = op_dst; |
|
2962 |
n2->_bottom_type = _bottom_type; |
|
2963 |
ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2964 |
ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2965 |
||
2966 |
nodes->push(n1); |
|
2967 |
nodes->push(n2); |
|
2968 |
assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. |
|
2969 |
%} |
|
2970 |
||
2971 |
enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
|
|
2972 |
decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode(); |
|
2973 |
cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node(); |
|
2974 |
||
2975 |
n_compare->add_req(n_region, n_src); |
|
2976 |
n_compare->_opnds[0] = op_crx; |
|
2977 |
n_compare->_opnds[1] = op_src; |
|
2978 |
n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR); |
|
2979 |
||
2980 |
n_shift->add_req(n_region, n_src); |
|
2981 |
n_shift->_opnds[0] = op_dst; |
|
2982 |
n_shift->_opnds[1] = op_src; |
|
2983 |
n_shift->_bottom_type = _bottom_type; |
|
2984 |
||
2985 |
if (VM_Version::has_isel()) {
|
|
2986 |
// use isel instruction with Power 7 |
|
2987 |
||
2988 |
decodeN_addNode *n_add_base = new (C) decodeN_addNode(); |
|
2989 |
n_add_base->add_req(n_region, n_shift); |
|
2990 |
n_add_base->_opnds[0] = op_dst; |
|
2991 |
n_add_base->_opnds[1] = op_dst; |
|
2992 |
n_add_base->_bottom_type = _bottom_type; |
|
2993 |
||
2994 |
cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode(); |
|
2995 |
n_cond_set->add_req(n_region, n_compare, n_add_base); |
|
2996 |
n_cond_set->_opnds[0] = op_dst; |
|
2997 |
n_cond_set->_opnds[1] = op_crx; |
|
2998 |
n_cond_set->_opnds[2] = op_dst; |
|
2999 |
n_cond_set->_bottom_type = _bottom_type; |
|
3000 |
||
3001 |
assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3002 |
ra_->set_oop(n_cond_set, true); |
|
3003 |
||
3004 |
ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3005 |
ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
3006 |
ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3007 |
ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3008 |
||
3009 |
nodes->push(n_compare); |
|
3010 |
nodes->push(n_shift); |
|
3011 |
nodes->push(n_add_base); |
|
3012 |
nodes->push(n_cond_set); |
|
3013 |
||
3014 |
} else {
|
|
3015 |
// before Power 7 |
|
3016 |
cond_add_baseNode *n_add_base = new (C) cond_add_baseNode(); |
|
3017 |
||
3018 |
n_add_base->add_req(n_region, n_compare, n_shift); |
|
3019 |
n_add_base->_opnds[0] = op_dst; |
|
3020 |
n_add_base->_opnds[1] = op_crx; |
|
3021 |
n_add_base->_opnds[2] = op_dst; |
|
3022 |
n_add_base->_bottom_type = _bottom_type; |
|
3023 |
||
3024 |
assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3025 |
ra_->set_oop(n_add_base, true); |
|
3026 |
||
3027 |
ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3028 |
ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
3029 |
ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3030 |
||
3031 |
nodes->push(n_compare); |
|
3032 |
nodes->push(n_shift); |
|
3033 |
nodes->push(n_add_base); |
|
3034 |
} |
|
3035 |
%} |
|
3036 |
||
3037 |
enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
|
|
3038 |
decodeN_shiftNode *n1 = new (C) decodeN_shiftNode(); |
|
3039 |
n1->add_req(n_region, n_src); |
|
3040 |
n1->_opnds[0] = op_dst; |
|
3041 |
n1->_opnds[1] = op_src; |
|
3042 |
n1->_bottom_type = _bottom_type; |
|
3043 |
||
3044 |
decodeN_addNode *n2 = new (C) decodeN_addNode(); |
|
3045 |
n2->add_req(n_region, n1); |
|
3046 |
n2->_opnds[0] = op_dst; |
|
3047 |
n2->_opnds[1] = op_dst; |
|
3048 |
n2->_bottom_type = _bottom_type; |
|
3049 |
ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3050 |
ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3051 |
||
3052 |
assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3053 |
ra_->set_oop(n2, true); |
|
3054 |
||
3055 |
nodes->push(n1); |
|
3056 |
nodes->push(n2); |
|
3057 |
%} |
|
3058 |
||
3059 |
enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
|
|
3060 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3061 |
||
3062 |
MacroAssembler _masm(&cbuf); |
|
3063 |
int cc = $cmp$$cmpcode; |
|
3064 |
int flags_reg = $crx$$reg; |
|
3065 |
Label done; |
|
3066 |
assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3067 |
// Branch if not (cmp crx). |
|
3068 |
__ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); |
|
3069 |
__ mr($dst$$Register, $src$$Register); |
|
3070 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3071 |
__ bind(done); |
|
3072 |
%} |
|
3073 |
||
3074 |
enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
|
|
3075 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3076 |
||
3077 |
MacroAssembler _masm(&cbuf); |
|
3078 |
Label done; |
|
3079 |
assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3080 |
// Branch if not (cmp crx). |
|
3081 |
__ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
3082 |
__ li($dst$$Register, $src$$constant); |
|
3083 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3084 |
__ bind(done); |
|
3085 |
%} |
|
3086 |
||
3087 |
// New atomics. |
|
3088 |
enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
|
|
3089 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3090 |
||
3091 |
MacroAssembler _masm(&cbuf); |
|
3092 |
Register Rtmp = R0; |
|
3093 |
Register Rres = $res$$Register; |
|
3094 |
Register Rsrc = $src$$Register; |
|
3095 |
Register Rptr = $mem_ptr$$Register; |
|
3096 |
bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3097 |
Register Rold = RegCollision ? Rtmp : Rres; |
|
3098 |
||
3099 |
Label Lretry; |
|
3100 |
__ bind(Lretry); |
|
3101 |
__ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3102 |
__ add(Rtmp, Rsrc, Rold); |
|
3103 |
__ stwcx_(Rtmp, Rptr); |
|
3104 |
if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
|
|
3105 |
__ bne_predict_not_taken(CCR0, Lretry); |
|
3106 |
} else {
|
|
3107 |
__ bne( CCR0, Lretry); |
|
3108 |
} |
|
3109 |
if (RegCollision) __ subf(Rres, Rsrc, Rtmp); |
|
3110 |
__ fence(); |
|
3111 |
%} |
|
3112 |
||
3113 |
enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
|
|
3114 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3115 |
||
3116 |
MacroAssembler _masm(&cbuf); |
|
3117 |
Register Rtmp = R0; |
|
3118 |
Register Rres = $res$$Register; |
|
3119 |
Register Rsrc = $src$$Register; |
|
3120 |
Register Rptr = $mem_ptr$$Register; |
|
3121 |
bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3122 |
Register Rold = RegCollision ? Rtmp : Rres; |
|
3123 |
||
3124 |
Label Lretry; |
|
3125 |
__ bind(Lretry); |
|
3126 |
__ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3127 |
__ add(Rtmp, Rsrc, Rold); |
|
3128 |
__ stdcx_(Rtmp, Rptr); |
|
3129 |
if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
|
|
3130 |
__ bne_predict_not_taken(CCR0, Lretry); |
|
3131 |
} else {
|
|
3132 |
__ bne( CCR0, Lretry); |
|
3133 |
} |
|
3134 |
if (RegCollision) __ subf(Rres, Rsrc, Rtmp); |
|
3135 |
__ fence(); |
|
3136 |
%} |
|
3137 |
||
3138 |
enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
|
|
3139 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3140 |
||
3141 |
MacroAssembler _masm(&cbuf); |
|
3142 |
Register Rtmp = R0; |
|
3143 |
Register Rres = $res$$Register; |
|
3144 |
Register Rsrc = $src$$Register; |
|
3145 |
Register Rptr = $mem_ptr$$Register; |
|
3146 |
bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3147 |
Register Rold = RegCollision ? Rtmp : Rres; |
|
3148 |
||
3149 |
Label Lretry; |
|
3150 |
__ bind(Lretry); |
|
3151 |
__ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3152 |
__ stwcx_(Rsrc, Rptr); |
|
3153 |
if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
|
|
3154 |
__ bne_predict_not_taken(CCR0, Lretry); |
|
3155 |
} else {
|
|
3156 |
__ bne( CCR0, Lretry); |
|
3157 |
} |
|
3158 |
if (RegCollision) __ mr(Rres, Rtmp); |
|
3159 |
__ fence(); |
|
3160 |
%} |
|
3161 |
||
3162 |
enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
|
|
3163 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3164 |
||
3165 |
MacroAssembler _masm(&cbuf); |
|
3166 |
Register Rtmp = R0; |
|
3167 |
Register Rres = $res$$Register; |
|
3168 |
Register Rsrc = $src$$Register; |
|
3169 |
Register Rptr = $mem_ptr$$Register; |
|
3170 |
bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3171 |
Register Rold = RegCollision ? Rtmp : Rres; |
|
3172 |
||
3173 |
Label Lretry; |
|
3174 |
__ bind(Lretry); |
|
3175 |
__ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3176 |
__ stdcx_(Rsrc, Rptr); |
|
3177 |
if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
|
|
3178 |
__ bne_predict_not_taken(CCR0, Lretry); |
|
3179 |
} else {
|
|
3180 |
__ bne( CCR0, Lretry); |
|
3181 |
} |
|
3182 |
if (RegCollision) __ mr(Rres, Rtmp); |
|
3183 |
__ fence(); |
|
3184 |
%} |
|
3185 |
||
3186 |
// This enc_class is needed so that scheduler gets proper |
|
3187 |
// input mapping for latency computation. |
|
3188 |
enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
3189 |
// TODO: PPC port $archOpcode(ppc64Opcode_andc); |
|
3190 |
MacroAssembler _masm(&cbuf); |
|
3191 |
__ andc($dst$$Register, $src1$$Register, $src2$$Register); |
|
3192 |
%} |
|
3193 |
||
3194 |
enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
|
|
3195 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3196 |
||
3197 |
MacroAssembler _masm(&cbuf); |
|
3198 |
||
3199 |
Label done; |
|
3200 |
__ cmpwi($crx$$CondRegister, $src$$Register, 0); |
|
3201 |
__ li($dst$$Register, $zero$$constant); |
|
3202 |
__ beq($crx$$CondRegister, done); |
|
3203 |
__ li($dst$$Register, $notzero$$constant); |
|
3204 |
__ bind(done); |
|
3205 |
%} |
|
3206 |
||
3207 |
enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
|
|
3208 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3209 |
||
3210 |
MacroAssembler _masm(&cbuf); |
|
3211 |
||
3212 |
Label done; |
|
3213 |
__ cmpdi($crx$$CondRegister, $src$$Register, 0); |
|
3214 |
__ li($dst$$Register, $zero$$constant); |
|
3215 |
__ beq($crx$$CondRegister, done); |
|
3216 |
__ li($dst$$Register, $notzero$$constant); |
|
3217 |
__ bind(done); |
|
3218 |
%} |
|
3219 |
||
3220 |
enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
|
|
3221 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3222 |
||
3223 |
MacroAssembler _masm(&cbuf); |
|
3224 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
3225 |
Label done; |
|
3226 |
__ bso($crx$$CondRegister, done); |
|
3227 |
__ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
3228 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3229 |
__ bind(done); |
|
3230 |
%} |
|
3231 |
||
3232 |
enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
|
|
3233 |
// TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3234 |
||
3235 |
MacroAssembler _masm(&cbuf); |
|
3236 |
Label d; // dummy |
|
3237 |
__ bind(d); |
|
3238 |
Label* p = ($lbl$$label); |
|
3239 |
// `p' is `NULL' when this encoding class is used only to |
|
3240 |
// determine the size of the encoded instruction. |
|
3241 |
Label& l = (NULL == p)? d : *(p); |
|
3242 |
int cc = $cmp$$cmpcode; |
|
3243 |
int flags_reg = $crx$$reg; |
|
3244 |
assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3245 |
int bhint = Assembler::bhintNoHint; |
|
3246 |
||
3247 |
if (UseStaticBranchPredictionForUncommonPathsPPC64) {
|
|
3248 |
if (_prob <= PROB_NEVER) {
|
|
3249 |
bhint = Assembler::bhintIsNotTaken; |
|
3250 |
} else if (_prob >= PROB_ALWAYS) {
|
|
3251 |
bhint = Assembler::bhintIsTaken; |
|
3252 |
} |
|
3253 |
} |
|
3254 |
||
3255 |
__ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3256 |
cc_to_biint(cc, flags_reg), |
|
3257 |
l); |
|
3258 |
%} |
|
3259 |
||
3260 |
enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
|
|
3261 |
// The scheduler doesn't know about branch shortening, so we set the opcode |
|
3262 |
// to ppc64Opcode_bc in order to hide this detail from the scheduler. |
|
3263 |
// TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3264 |
||
3265 |
MacroAssembler _masm(&cbuf); |
|
3266 |
Label d; // dummy |
|
3267 |
__ bind(d); |
|
3268 |
Label* p = ($lbl$$label); |
|
3269 |
// `p' is `NULL' when this encoding class is used only to |
|
3270 |
// determine the size of the encoded instruction. |
|
3271 |
Label& l = (NULL == p)? d : *(p); |
|
3272 |
int cc = $cmp$$cmpcode; |
|
3273 |
int flags_reg = $crx$$reg; |
|
3274 |
int bhint = Assembler::bhintNoHint; |
|
3275 |
||
3276 |
if (UseStaticBranchPredictionForUncommonPathsPPC64) {
|
|
3277 |
if (_prob <= PROB_NEVER) {
|
|
3278 |
bhint = Assembler::bhintIsNotTaken; |
|
3279 |
} else if (_prob >= PROB_ALWAYS) {
|
|
3280 |
bhint = Assembler::bhintIsTaken; |
|
3281 |
} |
|
3282 |
} |
|
3283 |
||
3284 |
// Tell the conditional far branch to optimize itself when being relocated. |
|
3285 |
__ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3286 |
cc_to_biint(cc, flags_reg), |
|
3287 |
l, |
|
3288 |
MacroAssembler::bc_far_optimize_on_relocate); |
|
3289 |
%} |
|
3290 |
||
3291 |
// Branch used with Power6 scheduling (can be shortened without changing the node). |
|
3292 |
enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
|
|
3293 |
// The scheduler doesn't know about branch shortening, so we set the opcode |
|
3294 |
// to ppc64Opcode_bc in order to hide this detail from the scheduler. |
|
3295 |
// TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3296 |
||
3297 |
MacroAssembler _masm(&cbuf); |
|
3298 |
Label d; // dummy |
|
3299 |
__ bind(d); |
|
3300 |
Label* p = ($lbl$$label); |
|
3301 |
// `p' is `NULL' when this encoding class is used only to |
|
3302 |
// determine the size of the encoded instruction. |
|
3303 |
Label& l = (NULL == p)? d : *(p); |
|
3304 |
int cc = $cmp$$cmpcode; |
|
3305 |
int flags_reg = $crx$$reg; |
|
3306 |
int bhint = Assembler::bhintNoHint; |
|
3307 |
||
3308 |
if (UseStaticBranchPredictionForUncommonPathsPPC64) {
|
|
3309 |
if (_prob <= PROB_NEVER) {
|
|
3310 |
bhint = Assembler::bhintIsNotTaken; |
|
3311 |
} else if (_prob >= PROB_ALWAYS) {
|
|
3312 |
bhint = Assembler::bhintIsTaken; |
|
3313 |
} |
|
3314 |
} |
|
3315 |
||
3316 |
#if 0 // TODO: PPC port |
|
3317 |
if (_size == 8) {
|
|
3318 |
// Tell the conditional far branch to optimize itself when being relocated. |
|
3319 |
__ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3320 |
cc_to_biint(cc, flags_reg), |
|
3321 |
l, |
|
3322 |
MacroAssembler::bc_far_optimize_on_relocate); |
|
3323 |
} else {
|
|
3324 |
__ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3325 |
cc_to_biint(cc, flags_reg), |
|
3326 |
l); |
|
3327 |
} |
|
3328 |
#endif |
|
3329 |
Unimplemented(); |
|
3330 |
%} |
|
3331 |
||
3332 |
// Postalloc expand emitter for loading a replicatef float constant from |
|
3333 |
// the method's TOC. |
|
3334 |
// Enc_class needed as consttanttablebase is not supported by postalloc |
|
3335 |
// expand. |
|
3336 |
enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
|
|
3337 |
// Create new nodes. |
|
3338 |
||
3339 |
// Make an operand with the bit pattern to load as float. |
|
3340 |
immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF())); |
|
3341 |
||
3342 |
loadConLNodesTuple loadConLNodes = |
|
3343 |
loadConLNodesTuple_create(C, ra_, n_toc, op_repl, |
|
3344 |
ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3345 |
||
3346 |
// Push new nodes. |
|
3347 |
if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); |
|
3348 |
if (loadConLNodes._last) nodes->push(loadConLNodes._last); |
|
3349 |
||
3350 |
assert(nodes->length() >= 1, "must have created at least 1 node"); |
|
3351 |
assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); |
|
3352 |
%} |
|
3353 |
||
3354 |
// This enc_class is needed so that scheduler gets proper |
|
3355 |
// input mapping for latency computation. |
|
3356 |
enc_class enc_poll(immI dst, iRegLdst poll) %{
|
|
3357 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
3358 |
// Fake operand dst needed for PPC scheduler. |
|
3359 |
assert($dst$$constant == 0x0, "dst must be 0x0"); |
|
3360 |
||
3361 |
MacroAssembler _masm(&cbuf); |
|
3362 |
// Mark the code position where the load from the safepoint |
|
3363 |
// polling page was emitted as relocInfo::poll_type. |
|
3364 |
__ relocate(relocInfo::poll_type); |
|
3365 |
__ load_from_polling_page($poll$$Register); |
|
3366 |
%} |
|
3367 |
||
3368 |
// A Java static call or a runtime call. |
|
3369 |
// |
|
3370 |
// Branch-and-link relative to a trampoline. |
|
3371 |
// The trampoline loads the target address and does a long branch to there. |
|
3372 |
// In case we call java, the trampoline branches to a interpreter_stub |
|
3373 |
// which loads the inline cache and the real call target from the constant pool. |
|
3374 |
// |
|
3375 |
// This basically looks like this: |
|
3376 |
// |
|
3377 |
// >>>> consts -+ -+ |
|
3378 |
// | |- offset1 |
|
3379 |
// [call target1] | <-+ |
|
3380 |
// [IC cache] |- offset2 |
|
3381 |
// [call target2] <--+ |
|
3382 |
// |
|
3383 |
// <<<< consts |
|
3384 |
// >>>> insts |
|
3385 |
// |
|
3386 |
// bl offset16 -+ -+ ??? // How many bits available? |
|
3387 |
// | | |
|
3388 |
// <<<< insts | | |
|
3389 |
// >>>> stubs | | |
|
3390 |
// | |- trampoline_stub_Reloc |
|
3391 |
// trampoline stub: | <-+ |
|
3392 |
// r2 = toc | |
|
3393 |
// r2 = [r2 + offset1] | // Load call target1 from const section |
|
3394 |
// mtctr r2 | |
|
3395 |
// bctr |- static_stub_Reloc |
|
3396 |
// comp_to_interp_stub: <---+ |
|
3397 |
// r1 = toc |
|
3398 |
// ICreg = [r1 + IC_offset] // Load IC from const section |
|
3399 |
// r1 = [r1 + offset2] // Load call target2 from const section |
|
3400 |
// mtctr r1 |
|
3401 |
// bctr |
|
3402 |
// |
|
3403 |
// <<<< stubs |
|
3404 |
// |
|
3405 |
// The call instruction in the code either |
|
3406 |
// - Branches directly to a compiled method if the offset is encodable in instruction. |
|
3407 |
// - Branches to the trampoline stub if the offset to the compiled method is not encodable. |
|
3408 |
// - Branches to the compiled_to_interp stub if the target is interpreted. |
|
3409 |
// |
|
3410 |
// Further there are three relocations from the loads to the constants in |
|
3411 |
// the constant section. |
|
3412 |
// |
|
3413 |
// Usage of r1 and r2 in the stubs allows to distinguish them. |
|
3414 |
enc_class enc_java_static_call(method meth) %{
|
|
3415 |
// TODO: PPC port $archOpcode(ppc64Opcode_bl); |
|
3416 |
||
3417 |
MacroAssembler _masm(&cbuf); |
|
3418 |
address entry_point = (address)$meth$$method; |
|
3419 |
||
3420 |
if (!_method) {
|
|
3421 |
// A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. |
|
3422 |
emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); |
|
3423 |
} else {
|
|
3424 |
// Remember the offset not the address. |
|
3425 |
const int start_offset = __ offset(); |
|
3426 |
// The trampoline stub. |
|
3427 |
if (!Compile::current()->in_scratch_emit_size()) {
|
|
3428 |
// No entry point given, use the current pc. |
|
3429 |
// Make sure branch fits into |
|
3430 |
if (entry_point == 0) entry_point = __ pc(); |
|
3431 |
||
3432 |
// Put the entry point as a constant into the constant pool. |
|
3433 |
const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
3434 |
const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
3435 |
||
3436 |
// Emit the trampoline stub which will be related to the branch-and-link below. |
|
3437 |
emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); |
|
3438 |
__ relocate(_optimized_virtual ? |
|
3439 |
relocInfo::opt_virtual_call_type : relocInfo::static_call_type); |
|
3440 |
} |
|
3441 |
||
3442 |
// The real call. |
|
3443 |
// Note: At this point we do not have the address of the trampoline |
|
3444 |
// stub, and the entry point might be too far away for bl, so __ pc() |
|
3445 |
// serves as dummy and the bl will be patched later. |
|
3446 |
cbuf.set_insts_mark(); |
|
3447 |
__ bl(__ pc()); // Emits a relocation. |
|
3448 |
||
3449 |
// The stub for call to interpreter. |
|
3450 |
CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
3451 |
} |
|
3452 |
%} |
|
3453 |
||
3454 |
// Emit a method handle call. |
|
3455 |
// |
|
3456 |
// Method handle calls from compiled to compiled are going thru a |
|
3457 |
// c2i -> i2c adapter, extending the frame for their arguments. The |
|
3458 |
// caller however, returns directly to the compiled callee, that has |
|
3459 |
// to cope with the extended frame. We restore the original frame by |
|
3460 |
// loading the callers sp and adding the calculated framesize. |
|
3461 |
enc_class enc_java_handle_call(method meth) %{
|
|
3462 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3463 |
||
3464 |
MacroAssembler _masm(&cbuf); |
|
3465 |
address entry_point = (address)$meth$$method; |
|
3466 |
||
3467 |
// Remember the offset not the address. |
|
3468 |
const int start_offset = __ offset(); |
|
3469 |
// The trampoline stub. |
|
3470 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
3471 |
// No entry point given, use the current pc. |
|
3472 |
// Make sure branch fits into |
|
3473 |
if (entry_point == 0) entry_point = __ pc(); |
|
3474 |
||
3475 |
// Put the entry point as a constant into the constant pool. |
|
3476 |
const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
3477 |
const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
3478 |
||
3479 |
// Emit the trampoline stub which will be related to the branch-and-link below. |
|
3480 |
emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); |
|
3481 |
assert(_optimized_virtual, "methodHandle call should be a virtual call"); |
|
3482 |
__ relocate(relocInfo::opt_virtual_call_type); |
|
3483 |
} |
|
3484 |
||
3485 |
// The real call. |
|
3486 |
// Note: At this point we do not have the address of the trampoline |
|
3487 |
// stub, and the entry point might be too far away for bl, so __ pc() |
|
3488 |
// serves as dummy and the bl will be patched later. |
|
3489 |
cbuf.set_insts_mark(); |
|
3490 |
__ bl(__ pc()); // Emits a relocation. |
|
3491 |
||
3492 |
assert(_method, "execute next statement conditionally"); |
|
3493 |
// The stub for call to interpreter. |
|
3494 |
CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
3495 |
||
3496 |
// Restore original sp. |
|
3497 |
__ ld(R11_scratch1, 0, R1_SP); // Load caller sp. |
|
3498 |
const long framesize = ra_->C->frame_slots() << LogBytesPerInt; |
|
3499 |
unsigned int bytes = (unsigned int)framesize; |
|
3500 |
long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); |
|
3501 |
if (Assembler::is_simm(-offset, 16)) {
|
|
3502 |
__ addi(R1_SP, R11_scratch1, -offset); |
|
3503 |
} else {
|
|
3504 |
__ load_const_optimized(R12_scratch2, -offset); |
|
3505 |
__ add(R1_SP, R11_scratch1, R12_scratch2); |
|
3506 |
} |
|
3507 |
#ifdef ASSERT |
|
3508 |
__ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. |
|
3509 |
__ cmpd(CCR0, R11_scratch1, R12_scratch2); |
|
3510 |
__ asm_assert_eq("backlink changed", 0x8000);
|
|
3511 |
#endif |
|
3512 |
// If fails should store backlink before unextending. |
|
3513 |
||
| 22867 | 3514 |
if (ra_->C->env()->failing()) {
|
| 22861 | 3515 |
return; |
| 22867 | 3516 |
} |
| 22861 | 3517 |
%} |
3518 |
||
3519 |
// Second node of expanded dynamic call - the call. |
|
3520 |
enc_class enc_java_dynamic_call_sched(method meth) %{
|
|
3521 |
// TODO: PPC port $archOpcode(ppc64Opcode_bl); |
|
3522 |
||
3523 |
MacroAssembler _masm(&cbuf); |
|
3524 |
||
3525 |
if (!ra_->C->in_scratch_emit_size()) {
|
|
3526 |
// Create a call trampoline stub for the given method. |
|
3527 |
const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; |
|
3528 |
const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); |
|
3529 |
const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); |
|
3530 |
emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); |
|
3531 |
||
3532 |
if (ra_->C->env()->failing()) |
|
3533 |
return; |
|
3534 |
||
3535 |
// Build relocation at call site with ic position as data. |
|
3536 |
assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || |
|
3537 |
(_load_ic_hi_node == NULL && _load_ic_node != NULL), |
|
3538 |
"must have one, but can't have both"); |
|
3539 |
assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || |
|
3540 |
(_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), |
|
3541 |
"must contain instruction offset"); |
|
3542 |
const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL |
|
3543 |
? _load_ic_hi_node->_cbuf_insts_offset |
|
3544 |
: _load_ic_node->_cbuf_insts_offset; |
|
3545 |
const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); |
|
3546 |
assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), |
|
3547 |
"should be load from TOC"); |
|
3548 |
||
3549 |
__ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); |
|
3550 |
} |
|
3551 |
||
3552 |
// At this point I do not have the address of the trampoline stub, |
|
3553 |
// and the entry point might be too far away for bl. Pc() serves |
|
3554 |
// as dummy and bl will be patched later. |
|
3555 |
__ bl((address) __ pc()); |
|
3556 |
%} |
|
3557 |
||
3558 |
// postalloc expand emitter for virtual calls. |
|
3559 |
enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
|
|
3560 |
||
3561 |
// Create the nodes for loading the IC from the TOC. |
|
3562 |
loadConLNodesTuple loadConLNodes_IC = |
|
3563 |
loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()), |
|
3564 |
OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); |
|
3565 |
||
3566 |
// Create the call node. |
|
3567 |
CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode(); |
|
3568 |
call->_method_handle_invoke = _method_handle_invoke; |
|
3569 |
call->_vtable_index = _vtable_index; |
|
3570 |
call->_method = _method; |
|
3571 |
call->_bci = _bci; |
|
3572 |
call->_optimized_virtual = _optimized_virtual; |
|
3573 |
call->_tf = _tf; |
|
3574 |
call->_entry_point = _entry_point; |
|
3575 |
call->_cnt = _cnt; |
|
3576 |
call->_argsize = _argsize; |
|
3577 |
call->_oop_map = _oop_map; |
|
3578 |
call->_jvms = _jvms; |
|
3579 |
call->_jvmadj = _jvmadj; |
|
3580 |
call->_in_rms = _in_rms; |
|
3581 |
call->_nesting = _nesting; |
|
3582 |
||
3583 |
// New call needs all inputs of old call. |
|
3584 |
// Req... |
|
3585 |
for (uint i = 0; i < req(); ++i) {
|
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3586 |
// The expanded node does not need toc any more. |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3587 |
// Add the inline cache constant here instead. This expresses the |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3588 |
// register of the inline cache must be live at the call. |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3589 |
// Else we would have to adapt JVMState by -1. |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3590 |
if (i == mach_constant_base_node_input()) {
|
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3591 |
call->add_req(loadConLNodes_IC._last); |
| 22861 | 3592 |
} else {
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3593 |
call->add_req(in(i)); |
| 22861 | 3594 |
} |
3595 |
} |
|
3596 |
// ...as well as prec |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3597 |
for (uint i = req(); i < len(); ++i) {
|
| 22861 | 3598 |
call->add_prec(in(i)); |
3599 |
} |
|
3600 |
||
3601 |
// Remember nodes loading the inline cache into r19. |
|
3602 |
call->_load_ic_hi_node = loadConLNodes_IC._large_hi; |
|
3603 |
call->_load_ic_node = loadConLNodes_IC._small; |
|
3604 |
||
3605 |
// Operands for new nodes. |
|
3606 |
call->_opnds[0] = _opnds[0]; |
|
3607 |
call->_opnds[1] = _opnds[1]; |
|
3608 |
||
3609 |
// Only the inline cache is associated with a register. |
|
3610 |
assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); |
|
3611 |
||
3612 |
// Push new nodes. |
|
3613 |
if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); |
|
3614 |
if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); |
|
3615 |
nodes->push(call); |
|
3616 |
%} |
|
3617 |
||
3618 |
// Compound version of call dynamic |
|
3619 |
enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
|
|
3620 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3621 |
MacroAssembler _masm(&cbuf); |
|
3622 |
int start_offset = __ offset(); |
|
3623 |
||
3624 |
Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; |
|
3625 |
#if 0 |
|
3626 |
if (_vtable_index < 0) {
|
|
3627 |
// Must be invalid_vtable_index, not nonvirtual_vtable_index. |
|
3628 |
assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
|
3629 |
Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3630 |
AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word()); |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3631 |
|
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3632 |
address virtual_call_meta_addr = __ pc(); |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3633 |
__ load_const_from_method_toc(ic_reg, meta, Rtoc); |
| 22861 | 3634 |
// CALL to fixup routine. Fixup routine uses ScopeDesc info |
3635 |
// to determine who we intended to call. |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3636 |
__ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); |
| 22861 | 3637 |
emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); |
3638 |
assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, |
|
3639 |
"Fix constant in ret_addr_offset()"); |
|
3640 |
} else {
|
|
3641 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
3642 |
// Go thru the vtable. Get receiver klass. Receiver already |
|
3643 |
// checked for non-null. If we'll go thru a C2I adapter, the |
|
3644 |
// interpreter expects method in R19_method. |
|
3645 |
||
3646 |
__ load_klass(R11_scratch1, R3); |
|
3647 |
||
3648 |
int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); |
|
3649 |
int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); |
|
3650 |
__ li(R19_method, v_off); |
|
3651 |
__ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); |
|
3652 |
// NOTE: for vtable dispatches, the vtable entry will never be |
|
3653 |
// null. However it may very well end up in handle_wrong_method |
|
3654 |
// if the method is abstract for the particular class. |
|
3655 |
__ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); |
|
3656 |
// Call target. Either compiled code or C2I adapter. |
|
3657 |
__ mtctr(R11_scratch1); |
|
3658 |
__ bctrl(); |
|
3659 |
if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
|
|
3660 |
tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
|
|
3661 |
} |
|
3662 |
assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, |
|
3663 |
"Fix constant in ret_addr_offset()"); |
|
3664 |
} |
|
3665 |
#endif |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3666 |
guarantee(0, "Fix handling of toc edge: messes up derived/base pairs."); |
| 22861 | 3667 |
Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). |
3668 |
%} |
|
3669 |
||
3670 |
// a runtime call |
|
3671 |
enc_class enc_java_to_runtime_call (method meth) %{
|
|
3672 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3673 |
||
3674 |
MacroAssembler _masm(&cbuf); |
|
3675 |
const address start_pc = __ pc(); |
|
3676 |
||
3677 |
// The function we're going to call. |
|
3678 |
FunctionDescriptor fdtemp; |
|
3679 |
const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; |
|
3680 |
||
3681 |
Register Rtoc = R12_scratch2; |
|
3682 |
// Calculate the method's TOC. |
|
3683 |
__ calculate_address_from_global_toc(Rtoc, __ method_toc()); |
|
3684 |
// Put entry, env, toc into the constant pool, this needs up to 3 constant |
|
3685 |
// pool entries; call_c_using_toc will optimize the call. |
|
3686 |
__ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); |
|
3687 |
||
3688 |
// Check the ret_addr_offset. |
|
3689 |
assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, |
|
3690 |
"Fix constant in ret_addr_offset()"); |
|
3691 |
%} |
|
3692 |
||
3693 |
// Move to ctr for leaf call. |
|
3694 |
// This enc_class is needed so that scheduler gets proper |
|
3695 |
// input mapping for latency computation. |
|
3696 |
enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
|
|
3697 |
// TODO: PPC port $archOpcode(ppc64Opcode_mtctr); |
|
3698 |
MacroAssembler _masm(&cbuf); |
|
3699 |
__ mtctr($src$$Register); |
|
3700 |
%} |
|
3701 |
||
3702 |
// postalloc expand emitter for runtime leaf calls. |
|
3703 |
enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
|
|
3704 |
// Get the struct that describes the function we are about to call. |
|
3705 |
FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); |
|
3706 |
assert(fd, "need fd here"); |
|
3707 |
// new nodes |
|
3708 |
loadConLNodesTuple loadConLNodes_Entry; |
|
3709 |
loadConLNodesTuple loadConLNodes_Env; |
|
3710 |
loadConLNodesTuple loadConLNodes_Toc; |
|
3711 |
MachNode *mtctr = NULL; |
|
3712 |
MachCallLeafNode *call = NULL; |
|
3713 |
||
3714 |
// Create nodes and operands for loading the entry point. |
|
3715 |
loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()), |
|
3716 |
OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); |
|
3717 |
||
3718 |
||
3719 |
// Create nodes and operands for loading the env pointer. |
|
3720 |
if (fd->env() != NULL) {
|
|
3721 |
loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()), |
|
3722 |
OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); |
|
3723 |
} else {
|
|
3724 |
loadConLNodes_Env._large_hi = NULL; |
|
3725 |
loadConLNodes_Env._large_lo = NULL; |
|
3726 |
loadConLNodes_Env._small = NULL; |
|
3727 |
loadConLNodes_Env._last = new (C) loadConL16Node(); |
|
3728 |
loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper(); |
|
3729 |
loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0); |
|
3730 |
ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); |
|
3731 |
} |
|
3732 |
||
3733 |
// Create nodes and operands for loading the Toc point. |
|
3734 |
loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()), |
|
3735 |
OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); |
|
3736 |
// mtctr node |
|
3737 |
mtctr = new (C) CallLeafDirect_mtctrNode(); |
|
3738 |
||
3739 |
assert(loadConLNodes_Entry._last != NULL, "entry must exist"); |
|
3740 |
mtctr->add_req(0, loadConLNodes_Entry._last); |
|
3741 |
||
3742 |
mtctr->_opnds[0] = new (C) iRegLdstOper(); |
|
3743 |
mtctr->_opnds[1] = new (C) iRegLdstOper(); |
|
3744 |
||
3745 |
// call node |
|
3746 |
call = new (C) CallLeafDirectNode(); |
|
3747 |
||
3748 |
call->_opnds[0] = _opnds[0]; |
|
3749 |
call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later |
|
3750 |
||
3751 |
// Make the new call node look like the old one. |
|
3752 |
call->_name = _name; |
|
3753 |
call->_tf = _tf; |
|
3754 |
call->_entry_point = _entry_point; |
|
3755 |
call->_cnt = _cnt; |
|
3756 |
call->_argsize = _argsize; |
|
3757 |
call->_oop_map = _oop_map; |
|
3758 |
guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); |
|
3759 |
call->_jvms = NULL; |
|
3760 |
call->_jvmadj = _jvmadj; |
|
3761 |
call->_in_rms = _in_rms; |
|
3762 |
call->_nesting = _nesting; |
|
3763 |
||
3764 |
||
3765 |
// New call needs all inputs of old call. |
|
3766 |
// Req... |
|
3767 |
for (uint i = 0; i < req(); ++i) {
|
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3768 |
if (i != mach_constant_base_node_input()) {
|
| 22861 | 3769 |
call->add_req(in(i)); |
3770 |
} |
|
3771 |
} |
|
3772 |
||
3773 |
// These must be reqired edges, as the registers are live up to |
|
3774 |
// the call. Else the constants are handled as kills. |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3775 |
call->add_req(mtctr); |
| 22861 | 3776 |
call->add_req(loadConLNodes_Env._last); |
3777 |
call->add_req(loadConLNodes_Toc._last); |
|
3778 |
||
3779 |
// ...as well as prec |
|
3780 |
for (uint i = req(); i < len(); ++i) {
|
|
3781 |
call->add_prec(in(i)); |
|
3782 |
} |
|
3783 |
||
3784 |
// registers |
|
3785 |
ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); |
|
3786 |
||
3787 |
// Insert the new nodes. |
|
3788 |
if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); |
|
3789 |
if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); |
|
3790 |
if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); |
|
3791 |
if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); |
|
3792 |
if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); |
|
3793 |
if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); |
|
3794 |
nodes->push(mtctr); |
|
3795 |
nodes->push(call); |
|
3796 |
%} |
|
3797 |
%} |
|
3798 |
||
3799 |
//----------FRAME-------------------------------------------------------------- |
|
3800 |
// Definition of frame structure and management information. |
|
3801 |
||
3802 |
frame %{
|
|
3803 |
// What direction does stack grow in (assumed to be same for native & Java). |
|
3804 |
stack_direction(TOWARDS_LOW); |
|
3805 |
||
3806 |
// These two registers define part of the calling convention between |
|
3807 |
// compiled code and the interpreter. |
|
3808 |
||
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
3809 |
// Inline Cache Register or method for I2C. |
| 22861 | 3810 |
inline_cache_reg(R19); // R19_method |
3811 |
||
3812 |
// Method Oop Register when calling interpreter. |
|
3813 |
interpreter_method_oop_reg(R19); // R19_method |
|
3814 |
||
3815 |
// Optional: name the operand used by cisc-spilling to access |
|
3816 |
// [stack_pointer + offset]. |
|
3817 |
cisc_spilling_operand_name(indOffset); |
|
3818 |
||
3819 |
// Number of stack slots consumed by a Monitor enter. |
|
3820 |
sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); |
|
3821 |
||
3822 |
// Compiled code's Frame Pointer. |
|
3823 |
frame_pointer(R1); // R1_SP |
|
3824 |
||
3825 |
// Interpreter stores its frame pointer in a register which is |
|
3826 |
// stored to the stack by I2CAdaptors. I2CAdaptors convert from |
|
3827 |
// interpreted java to compiled java. |
|
3828 |
// |
|
3829 |
// R14_state holds pointer to caller's cInterpreter. |
|
3830 |
interpreter_frame_pointer(R14); // R14_state |
|
3831 |
||
3832 |
stack_alignment(frame::alignment_in_bytes); |
|
3833 |
||
3834 |
in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); |
|
3835 |
||
3836 |
// Number of outgoing stack slots killed above the |
|
3837 |
// out_preserve_stack_slots for calls to C. Supports the var-args |
|
3838 |
// backing area for register parms. |
|
3839 |
// |
|
3840 |
varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); |
|
3841 |
||
3842 |
// The after-PROLOG location of the return address. Location of |
|
3843 |
// return address specifies a type (REG or STACK) and a number |
|
3844 |
// representing the register number (i.e. - use a register name) or |
|
3845 |
// stack slot. |
|
3846 |
// |
|
3847 |
// A: Link register is stored in stack slot ... |
|
3848 |
// M: ... but it's in the caller's frame according to PPC-64 ABI. |
|
3849 |
// J: Therefore, we make sure that the link register is also in R11_scratch1 |
|
3850 |
// at the end of the prolog. |
|
3851 |
// B: We use R20, now. |
|
3852 |
//return_addr(REG R20); |
|
3853 |
||
3854 |
// G: After reading the comments made by all the luminaries on their |
|
3855 |
// failure to tell the compiler where the return address really is, |
|
3856 |
// I hardly dare to try myself. However, I'm convinced it's in slot |
|
3857 |
// 4 what apparently works and saves us some spills. |
|
3858 |
return_addr(STACK 4); |
|
3859 |
||
3860 |
// This is the body of the function |
|
3861 |
// |
|
3862 |
// void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs |
|
3863 |
// uint length, // length of array |
|
3864 |
// bool is_outgoing) |
|
3865 |
// |
|
3866 |
// The `sig' array is to be updated. sig[j] represents the location |
|
3867 |
// of the j-th argument, either a register or a stack slot. |
|
3868 |
||
3869 |
// Comment taken from i486.ad: |
|
3870 |
// Body of function which returns an integer array locating |
|
3871 |
// arguments either in registers or in stack slots. Passed an array |
|
3872 |
// of ideal registers called "sig" and a "length" count. Stack-slot |
|
3873 |
// offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
3874 |
// arguments for a CALLEE. Incoming stack arguments are |
|
3875 |
// automatically biased by the preserve_stack_slots field above. |
|
3876 |
calling_convention %{
|
|
3877 |
// No difference between ingoing/outgoing. Just pass false. |
|
3878 |
SharedRuntime::java_calling_convention(sig_bt, regs, length, false); |
|
3879 |
%} |
|
3880 |
||
3881 |
// Comment taken from i486.ad: |
|
3882 |
// Body of function which returns an integer array locating |
|
3883 |
// arguments either in registers or in stack slots. Passed an array |
|
3884 |
// of ideal registers called "sig" and a "length" count. Stack-slot |
|
3885 |
// offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
3886 |
// arguments for a CALLEE. Incoming stack arguments are |
|
3887 |
// automatically biased by the preserve_stack_slots field above. |
|
3888 |
c_calling_convention %{
|
|
3889 |
// This is obviously always outgoing. |
|
3890 |
// C argument in register AND stack slot. |
|
3891 |
(void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
|
3892 |
%} |
|
3893 |
||
3894 |
// Location of native (C/C++) and interpreter return values. This |
|
3895 |
// is specified to be the same as Java. In the 32-bit VM, long |
|
3896 |
// values are actually returned from native calls in O0:O1 and |
|
3897 |
// returned to the interpreter in I0:I1. The copying to and from |
|
3898 |
// the register pairs is done by the appropriate call and epilog |
|
3899 |
// opcodes. This simplifies the register allocator. |
|
3900 |
c_return_value %{
|
|
3901 |
assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || |
|
3902 |
(ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), |
|
3903 |
"only return normal values"); |
|
3904 |
// enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL |
|
3905 |
static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
|
|
3906 |
static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
|
|
3907 |
return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
3908 |
%} |
|
3909 |
||
3910 |
// Location of compiled Java return values. Same as C |
|
3911 |
return_value %{
|
|
3912 |
assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || |
|
3913 |
(ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), |
|
3914 |
"only return normal values"); |
|
3915 |
// enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL |
|
3916 |
static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
|
|
3917 |
static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
|
|
3918 |
return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
3919 |
%} |
|
3920 |
%} |
|
3921 |
||
3922 |
||
3923 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
3924 |
||
3925 |
//----------Operand Attributes------------------------------------------------- |
|
3926 |
op_attrib op_cost(1); // Required cost attribute. |
|
3927 |
||
3928 |
//----------Instruction Attributes--------------------------------------------- |
|
3929 |
||
3930 |
// Cost attribute. required. |
|
3931 |
ins_attrib ins_cost(DEFAULT_COST); |
|
3932 |
||
3933 |
// Is this instruction a non-matching short branch variant of some |
|
3934 |
// long branch? Not required. |
|
3935 |
ins_attrib ins_short_branch(0); |
|
3936 |
||
3937 |
ins_attrib ins_is_TrapBasedCheckNode(true); |
|
3938 |
||
3939 |
// Number of constants. |
|
3940 |
// This instruction uses the given number of constants |
|
3941 |
// (optional attribute). |
|
3942 |
// This is needed to determine in time whether the constant pool will |
|
3943 |
// exceed 4000 entries. Before postalloc_expand the overall number of constants |
|
3944 |
// is determined. It's also used to compute the constant pool size |
|
3945 |
// in Output(). |
|
3946 |
ins_attrib ins_num_consts(0); |
|
3947 |
||
3948 |
// Required alignment attribute (must be a power of 2) specifies the |
|
3949 |
// alignment that some part of the instruction (not necessarily the |
|
3950 |
// start) requires. If > 1, a compute_padding() function must be |
|
3951 |
// provided for the instruction. |
|
3952 |
ins_attrib ins_alignment(1); |
|
3953 |
||
3954 |
// Enforce/prohibit rematerializations. |
|
3955 |
// - If an instruction is attributed with 'ins_cannot_rematerialize(true)' |
|
3956 |
// then rematerialization of that instruction is prohibited and the |
|
3957 |
// instruction's value will be spilled if necessary. |
|
3958 |
// Causes that MachNode::rematerialize() returns false. |
|
3959 |
// - If an instruction is attributed with 'ins_should_rematerialize(true)' |
|
3960 |
// then rematerialization should be enforced and a copy of the instruction |
|
3961 |
// should be inserted if possible; rematerialization is not guaranteed. |
|
3962 |
// Note: this may result in rematerializations in front of every use. |
|
3963 |
// Causes that MachNode::rematerialize() can return true. |
|
3964 |
// (optional attribute) |
|
3965 |
ins_attrib ins_cannot_rematerialize(false); |
|
3966 |
ins_attrib ins_should_rematerialize(false); |
|
3967 |
||
3968 |
// Instruction has variable size depending on alignment. |
|
3969 |
ins_attrib ins_variable_size_depending_on_alignment(false); |
|
3970 |
||
3971 |
// Instruction is a nop. |
|
3972 |
ins_attrib ins_is_nop(false); |
|
3973 |
||
3974 |
// Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). |
|
3975 |
ins_attrib ins_use_mach_if_fast_lock_node(false); |
|
3976 |
||
3977 |
// Field for the toc offset of a constant. |
|
3978 |
// |
|
3979 |
// This is needed if the toc offset is not encodable as an immediate in |
|
3980 |
// the PPC load instruction. If so, the upper (hi) bits of the offset are |
|
3981 |
// added to the toc, and from this a load with immediate is performed. |
|
3982 |
// With postalloc expand, we get two nodes that require the same offset |
|
3983 |
// but which don't know about each other. The offset is only known |
|
3984 |
// when the constant is added to the constant pool during emitting. |
|
3985 |
// It is generated in the 'hi'-node adding the upper bits, and saved |
|
3986 |
// in this node. The 'lo'-node has a link to the 'hi'-node and reads |
|
3987 |
// the offset from there when it gets encoded. |
|
3988 |
ins_attrib ins_field_const_toc_offset(0); |
|
3989 |
ins_attrib ins_field_const_toc_offset_hi_node(0); |
|
3990 |
||
3991 |
// A field that can hold the instructions offset in the code buffer. |
|
3992 |
// Set in the nodes emitter. |
|
3993 |
ins_attrib ins_field_cbuf_insts_offset(-1); |
|
3994 |
||
3995 |
// Fields for referencing a call's load-IC-node. |
|
3996 |
// If the toc offset can not be encoded as an immediate in a load, we |
|
3997 |
// use two nodes. |
|
3998 |
ins_attrib ins_field_load_ic_hi_node(0); |
|
3999 |
ins_attrib ins_field_load_ic_node(0); |
|
4000 |
||
4001 |
//----------OPERANDS----------------------------------------------------------- |
|
4002 |
// Operand definitions must precede instruction definitions for correct |
|
4003 |
// parsing in the ADLC because operands constitute user defined types |
|
4004 |
// which are used in instruction definitions. |
|
4005 |
// |
|
4006 |
// Formats are generated automatically for constants and base registers. |
|
4007 |
||
4008 |
//----------Simple Operands---------------------------------------------------- |
|
4009 |
// Immediate Operands |
|
4010 |
||
4011 |
// Integer Immediate: 32-bit |
|
4012 |
operand immI() %{
|
|
4013 |
match(ConI); |
|
4014 |
op_cost(40); |
|
4015 |
format %{ %}
|
|
4016 |
interface(CONST_INTER); |
|
4017 |
%} |
|
4018 |
||
4019 |
operand immI8() %{
|
|
4020 |
predicate(Assembler::is_simm(n->get_int(), 8)); |
|
4021 |
op_cost(0); |
|
4022 |
match(ConI); |
|
4023 |
format %{ %}
|
|
4024 |
interface(CONST_INTER); |
|
4025 |
%} |
|
4026 |
||
4027 |
// Integer Immediate: 16-bit |
|
4028 |
operand immI16() %{
|
|
4029 |
predicate(Assembler::is_simm(n->get_int(), 16)); |
|
4030 |
op_cost(0); |
|
4031 |
match(ConI); |
|
4032 |
format %{ %}
|
|
4033 |
interface(CONST_INTER); |
|
4034 |
%} |
|
4035 |
||
4036 |
// Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. |
|
4037 |
operand immIhi16() %{
|
|
4038 |
predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); |
|
4039 |
match(ConI); |
|
4040 |
op_cost(0); |
|
4041 |
format %{ %}
|
|
4042 |
interface(CONST_INTER); |
|
4043 |
%} |
|
4044 |
||
4045 |
operand immInegpow2() %{
|
|
4046 |
predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); |
|
4047 |
match(ConI); |
|
4048 |
op_cost(0); |
|
4049 |
format %{ %}
|
|
4050 |
interface(CONST_INTER); |
|
4051 |
%} |
|
4052 |
||
4053 |
operand immIpow2minus1() %{
|
|
4054 |
predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); |
|
4055 |
match(ConI); |
|
4056 |
op_cost(0); |
|
4057 |
format %{ %}
|
|
4058 |
interface(CONST_INTER); |
|
4059 |
%} |
|
4060 |
||
4061 |
operand immIpowerOf2() %{
|
|
4062 |
predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); |
|
4063 |
match(ConI); |
|
4064 |
op_cost(0); |
|
4065 |
format %{ %}
|
|
4066 |
interface(CONST_INTER); |
|
4067 |
%} |
|
4068 |
||
4069 |
// Unsigned Integer Immediate: the values 0-31 |
|
4070 |
operand uimmI5() %{
|
|
4071 |
predicate(Assembler::is_uimm(n->get_int(), 5)); |
|
4072 |
match(ConI); |
|
4073 |
op_cost(0); |
|
4074 |
format %{ %}
|
|
4075 |
interface(CONST_INTER); |
|
4076 |
%} |
|
4077 |
||
4078 |
// Unsigned Integer Immediate: 6-bit |
|
4079 |
operand uimmI6() %{
|
|
4080 |
predicate(Assembler::is_uimm(n->get_int(), 6)); |
|
4081 |
match(ConI); |
|
4082 |
op_cost(0); |
|
4083 |
format %{ %}
|
|
4084 |
interface(CONST_INTER); |
|
4085 |
%} |
|
4086 |
||
4087 |
// Unsigned Integer Immediate: 6-bit int, greater than 32 |
|
4088 |
operand uimmI6_ge32() %{
|
|
4089 |
predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); |
|
4090 |
match(ConI); |
|
4091 |
op_cost(0); |
|
4092 |
format %{ %}
|
|
4093 |
interface(CONST_INTER); |
|
4094 |
%} |
|
4095 |
||
4096 |
// Unsigned Integer Immediate: 15-bit |
|
4097 |
operand uimmI15() %{
|
|
4098 |
predicate(Assembler::is_uimm(n->get_int(), 15)); |
|
4099 |
match(ConI); |
|
4100 |
op_cost(0); |
|
4101 |
format %{ %}
|
|
4102 |
interface(CONST_INTER); |
|
4103 |
%} |
|
4104 |
||
4105 |
// Unsigned Integer Immediate: 16-bit |
|
4106 |
operand uimmI16() %{
|
|
4107 |
predicate(Assembler::is_uimm(n->get_int(), 16)); |
|
4108 |
match(ConI); |
|
4109 |
op_cost(0); |
|
4110 |
format %{ %}
|
|
4111 |
interface(CONST_INTER); |
|
4112 |
%} |
|
4113 |
||
4114 |
// constant 'int 0'. |
|
4115 |
operand immI_0() %{
|
|
4116 |
predicate(n->get_int() == 0); |
|
4117 |
match(ConI); |
|
4118 |
op_cost(0); |
|
4119 |
format %{ %}
|
|
4120 |
interface(CONST_INTER); |
|
4121 |
%} |
|
4122 |
||
4123 |
// constant 'int 1'. |
|
4124 |
operand immI_1() %{
|
|
4125 |
predicate(n->get_int() == 1); |
|
4126 |
match(ConI); |
|
4127 |
op_cost(0); |
|
4128 |
format %{ %}
|
|
4129 |
interface(CONST_INTER); |
|
4130 |
%} |
|
4131 |
||
4132 |
// constant 'int -1'. |
|
4133 |
operand immI_minus1() %{
|
|
4134 |
predicate(n->get_int() == -1); |
|
4135 |
match(ConI); |
|
4136 |
op_cost(0); |
|
4137 |
format %{ %}
|
|
4138 |
interface(CONST_INTER); |
|
4139 |
%} |
|
4140 |
||
4141 |
// int value 16. |
|
4142 |
operand immI_16() %{
|
|
4143 |
predicate(n->get_int() == 16); |
|
4144 |
match(ConI); |
|
4145 |
op_cost(0); |
|
4146 |
format %{ %}
|
|
4147 |
interface(CONST_INTER); |
|
4148 |
%} |
|
4149 |
||
4150 |
// int value 24. |
|
4151 |
operand immI_24() %{
|
|
4152 |
predicate(n->get_int() == 24); |
|
4153 |
match(ConI); |
|
4154 |
op_cost(0); |
|
4155 |
format %{ %}
|
|
4156 |
interface(CONST_INTER); |
|
4157 |
%} |
|
4158 |
||
4159 |
// Compressed oops constants |
|
4160 |
// Pointer Immediate |
|
4161 |
operand immN() %{
|
|
4162 |
match(ConN); |
|
4163 |
||
4164 |
op_cost(10); |
|
4165 |
format %{ %}
|
|
4166 |
interface(CONST_INTER); |
|
4167 |
%} |
|
4168 |
||
4169 |
// NULL Pointer Immediate |
|
4170 |
operand immN_0() %{
|
|
4171 |
predicate(n->get_narrowcon() == 0); |
|
4172 |
match(ConN); |
|
4173 |
||
4174 |
op_cost(0); |
|
4175 |
format %{ %}
|
|
4176 |
interface(CONST_INTER); |
|
4177 |
%} |
|
4178 |
||
4179 |
// Compressed klass constants |
|
4180 |
operand immNKlass() %{
|
|
4181 |
match(ConNKlass); |
|
4182 |
||
4183 |
op_cost(0); |
|
4184 |
format %{ %}
|
|
4185 |
interface(CONST_INTER); |
|
4186 |
%} |
|
4187 |
||
4188 |
// This operand can be used to avoid matching of an instruct |
|
4189 |
// with chain rule. |
|
4190 |
operand immNKlass_NM() %{
|
|
4191 |
match(ConNKlass); |
|
4192 |
predicate(false); |
|
4193 |
op_cost(0); |
|
4194 |
format %{ %}
|
|
4195 |
interface(CONST_INTER); |
|
4196 |
%} |
|
4197 |
||
4198 |
// Pointer Immediate: 64-bit |
|
4199 |
operand immP() %{
|
|
4200 |
match(ConP); |
|
4201 |
op_cost(0); |
|
4202 |
format %{ %}
|
|
4203 |
interface(CONST_INTER); |
|
4204 |
%} |
|
4205 |
||
4206 |
// Operand to avoid match of loadConP. |
|
4207 |
// This operand can be used to avoid matching of an instruct |
|
4208 |
// with chain rule. |
|
4209 |
operand immP_NM() %{
|
|
4210 |
match(ConP); |
|
4211 |
predicate(false); |
|
4212 |
op_cost(0); |
|
4213 |
format %{ %}
|
|
4214 |
interface(CONST_INTER); |
|
4215 |
%} |
|
4216 |
||
4217 |
// costant 'pointer 0'. |
|
4218 |
operand immP_0() %{
|
|
4219 |
predicate(n->get_ptr() == 0); |
|
4220 |
match(ConP); |
|
4221 |
op_cost(0); |
|
4222 |
format %{ %}
|
|
4223 |
interface(CONST_INTER); |
|
4224 |
%} |
|
4225 |
||
4226 |
// pointer 0x0 or 0x1 |
|
4227 |
operand immP_0or1() %{
|
|
4228 |
predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); |
|
4229 |
match(ConP); |
|
4230 |
op_cost(0); |
|
4231 |
format %{ %}
|
|
4232 |
interface(CONST_INTER); |
|
4233 |
%} |
|
4234 |
||
4235 |
operand immL() %{
|
|
4236 |
match(ConL); |
|
4237 |
op_cost(40); |
|
4238 |
format %{ %}
|
|
4239 |
interface(CONST_INTER); |
|
4240 |
%} |
|
4241 |
||
4242 |
// Long Immediate: 16-bit |
|
4243 |
operand immL16() %{
|
|
4244 |
predicate(Assembler::is_simm(n->get_long(), 16)); |
|
4245 |
match(ConL); |
|
4246 |
op_cost(0); |
|
4247 |
format %{ %}
|
|
4248 |
interface(CONST_INTER); |
|
4249 |
%} |
|
4250 |
||
4251 |
// Long Immediate: 16-bit, 4-aligned |
|
4252 |
operand immL16Alg4() %{
|
|
4253 |
predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); |
|
4254 |
match(ConL); |
|
4255 |
op_cost(0); |
|
4256 |
format %{ %}
|
|
4257 |
interface(CONST_INTER); |
|
4258 |
%} |
|
4259 |
||
4260 |
// Long Immediate: 32-bit, where lowest 16 bits are 0x0000. |
|
4261 |
operand immL32hi16() %{
|
|
4262 |
predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); |
|
4263 |
match(ConL); |
|
4264 |
op_cost(0); |
|
4265 |
format %{ %}
|
|
4266 |
interface(CONST_INTER); |
|
4267 |
%} |
|
4268 |
||
4269 |
// Long Immediate: 32-bit |
|
4270 |
operand immL32() %{
|
|
4271 |
predicate(Assembler::is_simm(n->get_long(), 32)); |
|
4272 |
match(ConL); |
|
4273 |
op_cost(0); |
|
4274 |
format %{ %}
|
|
4275 |
interface(CONST_INTER); |
|
4276 |
%} |
|
4277 |
||
4278 |
// Long Immediate: 64-bit, where highest 16 bits are not 0x0000. |
|
4279 |
operand immLhighest16() %{
|
|
4280 |
predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); |
|
4281 |
match(ConL); |
|
4282 |
op_cost(0); |
|
4283 |
format %{ %}
|
|
4284 |
interface(CONST_INTER); |
|
4285 |
%} |
|
4286 |
||
4287 |
operand immLnegpow2() %{
|
|
4288 |
predicate(is_power_of_2_long((jlong)-(n->get_long()))); |
|
4289 |
match(ConL); |
|
4290 |
op_cost(0); |
|
4291 |
format %{ %}
|
|
4292 |
interface(CONST_INTER); |
|
4293 |
%} |
|
4294 |
||
4295 |
operand immLpow2minus1() %{
|
|
4296 |
predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && |
|
4297 |
(n->get_long() != (jlong)0xffffffffffffffffL)); |
|
4298 |
match(ConL); |
|
4299 |
op_cost(0); |
|
4300 |
format %{ %}
|
|
4301 |
interface(CONST_INTER); |
|
4302 |
%} |
|
4303 |
||
4304 |
// constant 'long 0'. |
|
4305 |
operand immL_0() %{
|
|
4306 |
predicate(n->get_long() == 0L); |
|
4307 |
match(ConL); |
|
4308 |
op_cost(0); |
|
4309 |
format %{ %}
|
|
4310 |
interface(CONST_INTER); |
|
4311 |
%} |
|
4312 |
||
4313 |
// constat ' long -1'. |
|
4314 |
operand immL_minus1() %{
|
|
4315 |
predicate(n->get_long() == -1L); |
|
4316 |
match(ConL); |
|
4317 |
op_cost(0); |
|
4318 |
format %{ %}
|
|
4319 |
interface(CONST_INTER); |
|
4320 |
%} |
|
4321 |
||
4322 |
// Long Immediate: low 32-bit mask |
|
4323 |
operand immL_32bits() %{
|
|
4324 |
predicate(n->get_long() == 0xFFFFFFFFL); |
|
4325 |
match(ConL); |
|
4326 |
op_cost(0); |
|
4327 |
format %{ %}
|
|
4328 |
interface(CONST_INTER); |
|
4329 |
%} |
|
4330 |
||
4331 |
// Unsigned Long Immediate: 16-bit |
|
4332 |
operand uimmL16() %{
|
|
4333 |
predicate(Assembler::is_uimm(n->get_long(), 16)); |
|
4334 |
match(ConL); |
|
4335 |
op_cost(0); |
|
4336 |
format %{ %}
|
|
4337 |
interface(CONST_INTER); |
|
4338 |
%} |
|
4339 |
||
4340 |
// Float Immediate |
|
4341 |
operand immF() %{
|
|
4342 |
match(ConF); |
|
4343 |
op_cost(40); |
|
4344 |
format %{ %}
|
|
4345 |
interface(CONST_INTER); |
|
4346 |
%} |
|
4347 |
||
4348 |
// constant 'float +0.0'. |
|
4349 |
operand immF_0() %{
|
|
4350 |
predicate((n->getf() == 0) && |
|
4351 |
(fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); |
|
4352 |
match(ConF); |
|
4353 |
op_cost(0); |
|
4354 |
format %{ %}
|
|
4355 |
interface(CONST_INTER); |
|
4356 |
%} |
|
4357 |
||
4358 |
// Double Immediate |
|
4359 |
operand immD() %{
|
|
4360 |
match(ConD); |
|
4361 |
op_cost(40); |
|
4362 |
format %{ %}
|
|
4363 |
interface(CONST_INTER); |
|
4364 |
%} |
|
4365 |
||
4366 |
// Integer Register Operands |
|
4367 |
// Integer Destination Register |
|
4368 |
// See definition of reg_class bits32_reg_rw. |
|
4369 |
operand iRegIdst() %{
|
|
4370 |
constraint(ALLOC_IN_RC(bits32_reg_rw)); |
|
4371 |
match(RegI); |
|
4372 |
match(rscratch1RegI); |
|
4373 |
match(rscratch2RegI); |
|
4374 |
match(rarg1RegI); |
|
4375 |
match(rarg2RegI); |
|
4376 |
match(rarg3RegI); |
|
4377 |
match(rarg4RegI); |
|
4378 |
format %{ %}
|
|
4379 |
interface(REG_INTER); |
|
4380 |
%} |
|
4381 |
||
4382 |
// Integer Source Register |
|
4383 |
// See definition of reg_class bits32_reg_ro. |
|
4384 |
operand iRegIsrc() %{
|
|
4385 |
constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4386 |
match(RegI); |
|
4387 |
match(rscratch1RegI); |
|
4388 |
match(rscratch2RegI); |
|
4389 |
match(rarg1RegI); |
|
4390 |
match(rarg2RegI); |
|
4391 |
match(rarg3RegI); |
|
4392 |
match(rarg4RegI); |
|
4393 |
format %{ %}
|
|
4394 |
interface(REG_INTER); |
|
4395 |
%} |
|
4396 |
||
4397 |
operand rscratch1RegI() %{
|
|
4398 |
constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); |
|
4399 |
match(iRegIdst); |
|
4400 |
format %{ %}
|
|
4401 |
interface(REG_INTER); |
|
4402 |
%} |
|
4403 |
||
4404 |
operand rscratch2RegI() %{
|
|
4405 |
constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); |
|
4406 |
match(iRegIdst); |
|
4407 |
format %{ %}
|
|
4408 |
interface(REG_INTER); |
|
4409 |
%} |
|
4410 |
||
4411 |
operand rarg1RegI() %{
|
|
4412 |
constraint(ALLOC_IN_RC(rarg1_bits32_reg)); |
|
4413 |
match(iRegIdst); |
|
4414 |
format %{ %}
|
|
4415 |
interface(REG_INTER); |
|
4416 |
%} |
|
4417 |
||
4418 |
operand rarg2RegI() %{
|
|
4419 |
constraint(ALLOC_IN_RC(rarg2_bits32_reg)); |
|
4420 |
match(iRegIdst); |
|
4421 |
format %{ %}
|
|
4422 |
interface(REG_INTER); |
|
4423 |
%} |
|
4424 |
||
4425 |
operand rarg3RegI() %{
|
|
4426 |
constraint(ALLOC_IN_RC(rarg3_bits32_reg)); |
|
4427 |
match(iRegIdst); |
|
4428 |
format %{ %}
|
|
4429 |
interface(REG_INTER); |
|
4430 |
%} |
|
4431 |
||
4432 |
operand rarg4RegI() %{
|
|
4433 |
constraint(ALLOC_IN_RC(rarg4_bits32_reg)); |
|
4434 |
match(iRegIdst); |
|
4435 |
format %{ %}
|
|
4436 |
interface(REG_INTER); |
|
4437 |
%} |
|
4438 |
||
4439 |
operand rarg1RegL() %{
|
|
4440 |
constraint(ALLOC_IN_RC(rarg1_bits64_reg)); |
|
4441 |
match(iRegLdst); |
|
4442 |
format %{ %}
|
|
4443 |
interface(REG_INTER); |
|
4444 |
%} |
|
4445 |
||
4446 |
operand rarg2RegL() %{
|
|
4447 |
constraint(ALLOC_IN_RC(rarg2_bits64_reg)); |
|
4448 |
match(iRegLdst); |
|
4449 |
format %{ %}
|
|
4450 |
interface(REG_INTER); |
|
4451 |
%} |
|
4452 |
||
4453 |
operand rarg3RegL() %{
|
|
4454 |
constraint(ALLOC_IN_RC(rarg3_bits64_reg)); |
|
4455 |
match(iRegLdst); |
|
4456 |
format %{ %}
|
|
4457 |
interface(REG_INTER); |
|
4458 |
%} |
|
4459 |
||
4460 |
operand rarg4RegL() %{
|
|
4461 |
constraint(ALLOC_IN_RC(rarg4_bits64_reg)); |
|
4462 |
match(iRegLdst); |
|
4463 |
format %{ %}
|
|
4464 |
interface(REG_INTER); |
|
4465 |
%} |
|
4466 |
||
4467 |
// Pointer Destination Register |
|
4468 |
// See definition of reg_class bits64_reg_rw. |
|
4469 |
operand iRegPdst() %{
|
|
4470 |
constraint(ALLOC_IN_RC(bits64_reg_rw)); |
|
4471 |
match(RegP); |
|
4472 |
match(rscratch1RegP); |
|
4473 |
match(rscratch2RegP); |
|
4474 |
match(rarg1RegP); |
|
4475 |
match(rarg2RegP); |
|
4476 |
match(rarg3RegP); |
|
4477 |
match(rarg4RegP); |
|
4478 |
format %{ %}
|
|
4479 |
interface(REG_INTER); |
|
4480 |
%} |
|
4481 |
||
4482 |
// Pointer Destination Register |
|
4483 |
// Operand not using r11 and r12 (killed in epilog). |
|
4484 |
operand iRegPdstNoScratch() %{
|
|
4485 |
constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); |
|
4486 |
match(RegP); |
|
4487 |
match(rarg1RegP); |
|
4488 |
match(rarg2RegP); |
|
4489 |
match(rarg3RegP); |
|
4490 |
match(rarg4RegP); |
|
4491 |
format %{ %}
|
|
4492 |
interface(REG_INTER); |
|
4493 |
%} |
|
4494 |
||
4495 |
// Pointer Source Register |
|
4496 |
// See definition of reg_class bits64_reg_ro. |
|
4497 |
operand iRegPsrc() %{
|
|
4498 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4499 |
match(RegP); |
|
4500 |
match(iRegPdst); |
|
4501 |
match(rscratch1RegP); |
|
4502 |
match(rscratch2RegP); |
|
4503 |
match(rarg1RegP); |
|
4504 |
match(rarg2RegP); |
|
4505 |
match(rarg3RegP); |
|
4506 |
match(rarg4RegP); |
|
4507 |
match(threadRegP); |
|
4508 |
format %{ %}
|
|
4509 |
interface(REG_INTER); |
|
4510 |
%} |
|
4511 |
||
4512 |
// Thread operand. |
|
4513 |
operand threadRegP() %{
|
|
4514 |
constraint(ALLOC_IN_RC(thread_bits64_reg)); |
|
4515 |
match(iRegPdst); |
|
4516 |
format %{ "R16" %}
|
|
4517 |
interface(REG_INTER); |
|
4518 |
%} |
|
4519 |
||
4520 |
operand rscratch1RegP() %{
|
|
4521 |
constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); |
|
4522 |
match(iRegPdst); |
|
4523 |
format %{ "R11" %}
|
|
4524 |
interface(REG_INTER); |
|
4525 |
%} |
|
4526 |
||
4527 |
operand rscratch2RegP() %{
|
|
4528 |
constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); |
|
4529 |
match(iRegPdst); |
|
4530 |
format %{ %}
|
|
4531 |
interface(REG_INTER); |
|
4532 |
%} |
|
4533 |
||
4534 |
operand rarg1RegP() %{
|
|
4535 |
constraint(ALLOC_IN_RC(rarg1_bits64_reg)); |
|
4536 |
match(iRegPdst); |
|
4537 |
format %{ %}
|
|
4538 |
interface(REG_INTER); |
|
4539 |
%} |
|
4540 |
||
4541 |
operand rarg2RegP() %{
|
|
4542 |
constraint(ALLOC_IN_RC(rarg2_bits64_reg)); |
|
4543 |
match(iRegPdst); |
|
4544 |
format %{ %}
|
|
4545 |
interface(REG_INTER); |
|
4546 |
%} |
|
4547 |
||
4548 |
operand rarg3RegP() %{
|
|
4549 |
constraint(ALLOC_IN_RC(rarg3_bits64_reg)); |
|
4550 |
match(iRegPdst); |
|
4551 |
format %{ %}
|
|
4552 |
interface(REG_INTER); |
|
4553 |
%} |
|
4554 |
||
4555 |
operand rarg4RegP() %{
|
|
4556 |
constraint(ALLOC_IN_RC(rarg4_bits64_reg)); |
|
4557 |
match(iRegPdst); |
|
4558 |
format %{ %}
|
|
4559 |
interface(REG_INTER); |
|
4560 |
%} |
|
4561 |
||
4562 |
operand iRegNsrc() %{
|
|
4563 |
constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4564 |
match(RegN); |
|
4565 |
match(iRegNdst); |
|
4566 |
||
4567 |
format %{ %}
|
|
4568 |
interface(REG_INTER); |
|
4569 |
%} |
|
4570 |
||
4571 |
operand iRegNdst() %{
|
|
4572 |
constraint(ALLOC_IN_RC(bits32_reg_rw)); |
|
4573 |
match(RegN); |
|
4574 |
||
4575 |
format %{ %}
|
|
4576 |
interface(REG_INTER); |
|
4577 |
%} |
|
4578 |
||
4579 |
// Long Destination Register |
|
4580 |
// See definition of reg_class bits64_reg_rw. |
|
4581 |
operand iRegLdst() %{
|
|
4582 |
constraint(ALLOC_IN_RC(bits64_reg_rw)); |
|
4583 |
match(RegL); |
|
4584 |
match(rscratch1RegL); |
|
4585 |
match(rscratch2RegL); |
|
4586 |
format %{ %}
|
|
4587 |
interface(REG_INTER); |
|
4588 |
%} |
|
4589 |
||
4590 |
// Long Source Register |
|
4591 |
// See definition of reg_class bits64_reg_ro. |
|
4592 |
operand iRegLsrc() %{
|
|
4593 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4594 |
match(RegL); |
|
4595 |
match(iRegLdst); |
|
4596 |
match(rscratch1RegL); |
|
4597 |
match(rscratch2RegL); |
|
4598 |
format %{ %}
|
|
4599 |
interface(REG_INTER); |
|
4600 |
%} |
|
4601 |
||
4602 |
// Special operand for ConvL2I. |
|
4603 |
operand iRegL2Isrc(iRegLsrc reg) %{
|
|
4604 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4605 |
match(ConvL2I reg); |
|
4606 |
format %{ "ConvL2I($reg)" %}
|
|
4607 |
interface(REG_INTER) |
|
4608 |
%} |
|
4609 |
||
4610 |
operand rscratch1RegL() %{
|
|
4611 |
constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); |
|
4612 |
match(RegL); |
|
4613 |
format %{ %}
|
|
4614 |
interface(REG_INTER); |
|
4615 |
%} |
|
4616 |
||
4617 |
operand rscratch2RegL() %{
|
|
4618 |
constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); |
|
4619 |
match(RegL); |
|
4620 |
format %{ %}
|
|
4621 |
interface(REG_INTER); |
|
4622 |
%} |
|
4623 |
||
4624 |
// Condition Code Flag Registers |
|
4625 |
operand flagsReg() %{
|
|
4626 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4627 |
match(RegFlags); |
|
4628 |
format %{ %}
|
|
4629 |
interface(REG_INTER); |
|
4630 |
%} |
|
4631 |
||
4632 |
// Condition Code Flag Register CR0 |
|
4633 |
operand flagsRegCR0() %{
|
|
4634 |
constraint(ALLOC_IN_RC(int_flags_CR0)); |
|
4635 |
match(RegFlags); |
|
4636 |
format %{ "CR0" %}
|
|
4637 |
interface(REG_INTER); |
|
4638 |
%} |
|
4639 |
||
4640 |
operand flagsRegCR1() %{
|
|
4641 |
constraint(ALLOC_IN_RC(int_flags_CR1)); |
|
4642 |
match(RegFlags); |
|
4643 |
format %{ "CR1" %}
|
|
4644 |
interface(REG_INTER); |
|
4645 |
%} |
|
4646 |
||
4647 |
operand flagsRegCR6() %{
|
|
4648 |
constraint(ALLOC_IN_RC(int_flags_CR6)); |
|
4649 |
match(RegFlags); |
|
4650 |
format %{ "CR6" %}
|
|
4651 |
interface(REG_INTER); |
|
4652 |
%} |
|
4653 |
||
4654 |
operand regCTR() %{
|
|
4655 |
constraint(ALLOC_IN_RC(ctr_reg)); |
|
4656 |
// RegFlags should work. Introducing a RegSpecial type would cause a |
|
4657 |
// lot of changes. |
|
4658 |
match(RegFlags); |
|
4659 |
format %{"SR_CTR" %}
|
|
4660 |
interface(REG_INTER); |
|
4661 |
%} |
|
4662 |
||
4663 |
operand regD() %{
|
|
4664 |
constraint(ALLOC_IN_RC(dbl_reg)); |
|
4665 |
match(RegD); |
|
4666 |
format %{ %}
|
|
4667 |
interface(REG_INTER); |
|
4668 |
%} |
|
4669 |
||
4670 |
operand regF() %{
|
|
4671 |
constraint(ALLOC_IN_RC(flt_reg)); |
|
4672 |
match(RegF); |
|
4673 |
format %{ %}
|
|
4674 |
interface(REG_INTER); |
|
4675 |
%} |
|
4676 |
||
4677 |
// Special Registers |
|
4678 |
||
4679 |
// Method Register |
|
4680 |
operand inline_cache_regP(iRegPdst reg) %{
|
|
4681 |
constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg |
|
4682 |
match(reg); |
|
4683 |
format %{ %}
|
|
4684 |
interface(REG_INTER); |
|
4685 |
%} |
|
4686 |
||
4687 |
operand compiler_method_oop_regP(iRegPdst reg) %{
|
|
4688 |
constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg |
|
4689 |
match(reg); |
|
4690 |
format %{ %}
|
|
4691 |
interface(REG_INTER); |
|
4692 |
%} |
|
4693 |
||
4694 |
operand interpreter_method_oop_regP(iRegPdst reg) %{
|
|
4695 |
constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg |
|
4696 |
match(reg); |
|
4697 |
format %{ %}
|
|
4698 |
interface(REG_INTER); |
|
4699 |
%} |
|
4700 |
||
4701 |
// Operands to remove register moves in unscaled mode. |
|
4702 |
// Match read/write registers with an EncodeP node if neither shift nor add are required. |
|
4703 |
operand iRegP2N(iRegPsrc reg) %{
|
|
4704 |
predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); |
|
4705 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4706 |
match(EncodeP reg); |
|
4707 |
format %{ "$reg" %}
|
|
4708 |
interface(REG_INTER) |
|
4709 |
%} |
|
4710 |
||
4711 |
operand iRegN2P(iRegNsrc reg) %{
|
|
4712 |
predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4713 |
constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4714 |
match(DecodeN reg); |
|
4715 |
match(DecodeNKlass reg); |
|
4716 |
format %{ "$reg" %}
|
|
4717 |
interface(REG_INTER) |
|
4718 |
%} |
|
4719 |
||
4720 |
//----------Complex Operands--------------------------------------------------- |
|
4721 |
// Indirect Memory Reference |
|
4722 |
operand indirect(iRegPsrc reg) %{
|
|
4723 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4724 |
match(reg); |
|
4725 |
op_cost(100); |
|
4726 |
format %{ "[$reg]" %}
|
|
4727 |
interface(MEMORY_INTER) %{
|
|
4728 |
base($reg); |
|
4729 |
index(0x0); |
|
4730 |
scale(0x0); |
|
4731 |
disp(0x0); |
|
4732 |
%} |
|
4733 |
%} |
|
4734 |
||
4735 |
// Indirect with Offset |
|
4736 |
operand indOffset16(iRegPsrc reg, immL16 offset) %{
|
|
4737 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4738 |
match(AddP reg offset); |
|
4739 |
op_cost(100); |
|
4740 |
format %{ "[$reg + $offset]" %}
|
|
4741 |
interface(MEMORY_INTER) %{
|
|
4742 |
base($reg); |
|
4743 |
index(0x0); |
|
4744 |
scale(0x0); |
|
4745 |
disp($offset); |
|
4746 |
%} |
|
4747 |
%} |
|
4748 |
||
4749 |
// Indirect with 4-aligned Offset |
|
4750 |
operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
|
|
4751 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4752 |
match(AddP reg offset); |
|
4753 |
op_cost(100); |
|
4754 |
format %{ "[$reg + $offset]" %}
|
|
4755 |
interface(MEMORY_INTER) %{
|
|
4756 |
base($reg); |
|
4757 |
index(0x0); |
|
4758 |
scale(0x0); |
|
4759 |
disp($offset); |
|
4760 |
%} |
|
4761 |
%} |
|
4762 |
||
4763 |
//----------Complex Operands for Compressed OOPs------------------------------- |
|
4764 |
// Compressed OOPs with narrow_oop_shift == 0. |
|
4765 |
||
4766 |
// Indirect Memory Reference, compressed OOP |
|
4767 |
operand indirectNarrow(iRegNsrc reg) %{
|
|
4768 |
predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4769 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4770 |
match(DecodeN reg); |
|
4771 |
match(DecodeNKlass reg); |
|
4772 |
op_cost(100); |
|
4773 |
format %{ "[$reg]" %}
|
|
4774 |
interface(MEMORY_INTER) %{
|
|
4775 |
base($reg); |
|
4776 |
index(0x0); |
|
4777 |
scale(0x0); |
|
4778 |
disp(0x0); |
|
4779 |
%} |
|
4780 |
%} |
|
4781 |
||
4782 |
// Indirect with Offset, compressed OOP |
|
4783 |
operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
|
|
4784 |
predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4785 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4786 |
match(AddP (DecodeN reg) offset); |
|
4787 |
match(AddP (DecodeNKlass reg) offset); |
|
4788 |
op_cost(100); |
|
4789 |
format %{ "[$reg + $offset]" %}
|
|
4790 |
interface(MEMORY_INTER) %{
|
|
4791 |
base($reg); |
|
4792 |
index(0x0); |
|
4793 |
scale(0x0); |
|
4794 |
disp($offset); |
|
4795 |
%} |
|
4796 |
%} |
|
4797 |
||
4798 |
// Indirect with 4-aligned Offset, compressed OOP |
|
4799 |
operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
|
|
4800 |
predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4801 |
constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4802 |
match(AddP (DecodeN reg) offset); |
|
4803 |
match(AddP (DecodeNKlass reg) offset); |
|
4804 |
op_cost(100); |
|
4805 |
format %{ "[$reg + $offset]" %}
|
|
4806 |
interface(MEMORY_INTER) %{
|
|
4807 |
base($reg); |
|
4808 |
index(0x0); |
|
4809 |
scale(0x0); |
|
4810 |
disp($offset); |
|
4811 |
%} |
|
4812 |
%} |
|
4813 |
||
4814 |
//----------Special Memory Operands-------------------------------------------- |
|
4815 |
// Stack Slot Operand |
|
4816 |
// |
|
4817 |
// This operand is used for loading and storing temporary values on |
|
4818 |
// the stack where a match requires a value to flow through memory. |
|
4819 |
operand stackSlotI(sRegI reg) %{
|
|
4820 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4821 |
op_cost(100); |
|
4822 |
//match(RegI); |
|
4823 |
format %{ "[sp+$reg]" %}
|
|
4824 |
interface(MEMORY_INTER) %{
|
|
4825 |
base(0x1); // R1_SP |
|
4826 |
index(0x0); |
|
4827 |
scale(0x0); |
|
4828 |
disp($reg); // Stack Offset |
|
4829 |
%} |
|
4830 |
%} |
|
4831 |
||
4832 |
operand stackSlotL(sRegL reg) %{
|
|
4833 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4834 |
op_cost(100); |
|
4835 |
//match(RegL); |
|
4836 |
format %{ "[sp+$reg]" %}
|
|
4837 |
interface(MEMORY_INTER) %{
|
|
4838 |
base(0x1); // R1_SP |
|
4839 |
index(0x0); |
|
4840 |
scale(0x0); |
|
4841 |
disp($reg); // Stack Offset |
|
4842 |
%} |
|
4843 |
%} |
|
4844 |
||
4845 |
operand stackSlotP(sRegP reg) %{
|
|
4846 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4847 |
op_cost(100); |
|
4848 |
//match(RegP); |
|
4849 |
format %{ "[sp+$reg]" %}
|
|
4850 |
interface(MEMORY_INTER) %{
|
|
4851 |
base(0x1); // R1_SP |
|
4852 |
index(0x0); |
|
4853 |
scale(0x0); |
|
4854 |
disp($reg); // Stack Offset |
|
4855 |
%} |
|
4856 |
%} |
|
4857 |
||
4858 |
operand stackSlotF(sRegF reg) %{
|
|
4859 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4860 |
op_cost(100); |
|
4861 |
//match(RegF); |
|
4862 |
format %{ "[sp+$reg]" %}
|
|
4863 |
interface(MEMORY_INTER) %{
|
|
4864 |
base(0x1); // R1_SP |
|
4865 |
index(0x0); |
|
4866 |
scale(0x0); |
|
4867 |
disp($reg); // Stack Offset |
|
4868 |
%} |
|
4869 |
%} |
|
4870 |
||
4871 |
operand stackSlotD(sRegD reg) %{
|
|
4872 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4873 |
op_cost(100); |
|
4874 |
//match(RegD); |
|
4875 |
format %{ "[sp+$reg]" %}
|
|
4876 |
interface(MEMORY_INTER) %{
|
|
4877 |
base(0x1); // R1_SP |
|
4878 |
index(0x0); |
|
4879 |
scale(0x0); |
|
4880 |
disp($reg); // Stack Offset |
|
4881 |
%} |
|
4882 |
%} |
|
4883 |
||
4884 |
// Operands for expressing Control Flow |
|
4885 |
// NOTE: Label is a predefined operand which should not be redefined in |
|
4886 |
// the AD file. It is generically handled within the ADLC. |
|
4887 |
||
4888 |
//----------Conditional Branch Operands---------------------------------------- |
|
4889 |
// Comparison Op |
|
4890 |
// |
|
4891 |
// This is the operation of the comparison, and is limited to the |
|
4892 |
// following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE |
|
4893 |
// (!=). |
|
4894 |
// |
|
4895 |
// Other attributes of the comparison, such as unsignedness, are specified |
|
4896 |
// by the comparison instruction that sets a condition code flags register. |
|
4897 |
// That result is represented by a flags operand whose subtype is appropriate |
|
4898 |
// to the unsignedness (etc.) of the comparison. |
|
4899 |
// |
|
4900 |
// Later, the instruction which matches both the Comparison Op (a Bool) and |
|
4901 |
// the flags (produced by the Cmp) specifies the coding of the comparison op |
|
4902 |
// by matching a specific subtype of Bool operand below. |
|
4903 |
||
4904 |
// When used for floating point comparisons: unordered same as less. |
|
4905 |
operand cmpOp() %{
|
|
4906 |
match(Bool); |
|
4907 |
format %{ "" %}
|
|
4908 |
interface(COND_INTER) %{
|
|
4909 |
// BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. |
|
4910 |
// BO & BI |
|
4911 |
equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal |
|
4912 |
not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal |
|
4913 |
less(0x8); // 10 00: bcondCRbiIs1 & Condition::less |
|
4914 |
greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less |
|
4915 |
less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater |
|
4916 |
greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater |
|
4917 |
overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow |
|
4918 |
no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow |
|
4919 |
%} |
|
4920 |
%} |
|
4921 |
||
4922 |
//----------OPERAND CLASSES---------------------------------------------------- |
|
4923 |
// Operand Classes are groups of operands that are used to simplify |
|
4924 |
// instruction definitions by not requiring the AD writer to specify |
|
4925 |
// seperate instructions for every form of operand when the |
|
4926 |
// instruction accepts multiple operand types with the same basic |
|
4927 |
// encoding and format. The classic case of this is memory operands. |
|
4928 |
// Indirect is not included since its use is limited to Compare & Swap. |
|
4929 |
||
4930 |
opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); |
|
4931 |
// Memory operand where offsets are 4-aligned. Required for ld, std. |
|
4932 |
opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); |
|
4933 |
opclass indirectMemory(indirect, indirectNarrow); |
|
4934 |
||
4935 |
// Special opclass for I and ConvL2I. |
|
4936 |
opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); |
|
4937 |
||
4938 |
// Operand classes to match encode and decode. iRegN_P2N is only used |
|
4939 |
// for storeN. I have never seen an encode node elsewhere. |
|
4940 |
opclass iRegN_P2N(iRegNsrc, iRegP2N); |
|
4941 |
opclass iRegP_N2P(iRegPsrc, iRegN2P); |
|
4942 |
||
4943 |
//----------PIPELINE----------------------------------------------------------- |
|
4944 |
||
4945 |
pipeline %{
|
|
4946 |
||
4947 |
// See J.M.Tendler et al. "Power4 system microarchitecture", IBM |
|
4948 |
// J. Res. & Dev., No. 1, Jan. 2002. |
|
4949 |
||
4950 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
4951 |
attributes %{
|
|
4952 |
||
4953 |
// Power4 instructions are of fixed length. |
|
4954 |
fixed_size_instructions; |
|
4955 |
||
4956 |
// TODO: if `bundle' means number of instructions fetched |
|
4957 |
// per cycle, this is 8. If `bundle' means Power4 `group', that is |
|
4958 |
// max instructions issued per cycle, this is 5. |
|
4959 |
max_instructions_per_bundle = 8; |
|
4960 |
||
4961 |
// A Power4 instruction is 4 bytes long. |
|
4962 |
instruction_unit_size = 4; |
|
4963 |
||
4964 |
// The Power4 processor fetches 64 bytes... |
|
4965 |
instruction_fetch_unit_size = 64; |
|
4966 |
||
4967 |
// ...in one line |
|
4968 |
instruction_fetch_units = 1 |
|
4969 |
||
4970 |
// Unused, list one so that array generated by adlc is not empty. |
|
4971 |
// Aix compiler chokes if _nop_count = 0. |
|
4972 |
nops(fxNop); |
|
4973 |
%} |
|
4974 |
||
4975 |
//----------RESOURCES---------------------------------------------------------- |
|
4976 |
// Resources are the functional units available to the machine |
|
4977 |
resources( |
|
4978 |
PPC_BR, // branch unit |
|
4979 |
PPC_CR, // condition unit |
|
4980 |
PPC_FX1, // integer arithmetic unit 1 |
|
4981 |
PPC_FX2, // integer arithmetic unit 2 |
|
4982 |
PPC_LDST1, // load/store unit 1 |
|
4983 |
PPC_LDST2, // load/store unit 2 |
|
4984 |
PPC_FP1, // float arithmetic unit 1 |
|
4985 |
PPC_FP2, // float arithmetic unit 2 |
|
4986 |
PPC_LDST = PPC_LDST1 | PPC_LDST2, |
|
4987 |
PPC_FX = PPC_FX1 | PPC_FX2, |
|
4988 |
PPC_FP = PPC_FP1 | PPC_FP2 |
|
4989 |
); |
|
4990 |
||
4991 |
//----------PIPELINE DESCRIPTION----------------------------------------------- |
|
4992 |
// Pipeline Description specifies the stages in the machine's pipeline |
|
4993 |
pipe_desc( |
|
4994 |
// Power4 longest pipeline path |
|
4995 |
PPC_IF, // instruction fetch |
|
4996 |
PPC_IC, |
|
4997 |
//PPC_BP, // branch prediction |
|
4998 |
PPC_D0, // decode |
|
4999 |
PPC_D1, // decode |
|
5000 |
PPC_D2, // decode |
|
5001 |
PPC_D3, // decode |
|
5002 |
PPC_Xfer1, |
|
5003 |
PPC_GD, // group definition |
|
5004 |
PPC_MP, // map |
|
5005 |
PPC_ISS, // issue |
|
5006 |
PPC_RF, // resource fetch |
|
5007 |
PPC_EX1, // execute (all units) |
|
5008 |
PPC_EX2, // execute (FP, LDST) |
|
5009 |
PPC_EX3, // execute (FP, LDST) |
|
5010 |
PPC_EX4, // execute (FP) |
|
5011 |
PPC_EX5, // execute (FP) |
|
5012 |
PPC_EX6, // execute (FP) |
|
5013 |
PPC_WB, // write back |
|
5014 |
PPC_Xfer2, |
|
5015 |
PPC_CP |
|
5016 |
); |
|
5017 |
||
5018 |
//----------PIPELINE CLASSES--------------------------------------------------- |
|
5019 |
// Pipeline Classes describe the stages in which input and output are |
|
5020 |
// referenced by the hardware pipeline. |
|
5021 |
||
5022 |
// Simple pipeline classes. |
|
5023 |
||
5024 |
// Default pipeline class. |
|
5025 |
pipe_class pipe_class_default() %{
|
|
5026 |
single_instruction; |
|
5027 |
fixed_latency(2); |
|
5028 |
%} |
|
5029 |
||
5030 |
// Pipeline class for empty instructions. |
|
5031 |
pipe_class pipe_class_empty() %{
|
|
5032 |
single_instruction; |
|
5033 |
fixed_latency(0); |
|
5034 |
%} |
|
5035 |
||
5036 |
// Pipeline class for compares. |
|
5037 |
pipe_class pipe_class_compare() %{
|
|
5038 |
single_instruction; |
|
5039 |
fixed_latency(16); |
|
5040 |
%} |
|
5041 |
||
5042 |
// Pipeline class for traps. |
|
5043 |
pipe_class pipe_class_trap() %{
|
|
5044 |
single_instruction; |
|
5045 |
fixed_latency(100); |
|
5046 |
%} |
|
5047 |
||
5048 |
// Pipeline class for memory operations. |
|
5049 |
pipe_class pipe_class_memory() %{
|
|
5050 |
single_instruction; |
|
5051 |
fixed_latency(16); |
|
5052 |
%} |
|
5053 |
||
5054 |
// Pipeline class for call. |
|
5055 |
pipe_class pipe_class_call() %{
|
|
5056 |
single_instruction; |
|
5057 |
fixed_latency(100); |
|
5058 |
%} |
|
5059 |
||
5060 |
// Define the class for the Nop node. |
|
5061 |
define %{
|
|
5062 |
MachNop = pipe_class_default; |
|
5063 |
%} |
|
5064 |
||
5065 |
%} |
|
5066 |
||
5067 |
//----------INSTRUCTIONS------------------------------------------------------- |
|
5068 |
||
5069 |
// Naming of instructions: |
|
5070 |
// opA_operB / opA_operB_operC: |
|
5071 |
// Operation 'op' with one or two source operands 'oper'. Result |
|
5072 |
// type is A, source operand types are B and C. |
|
5073 |
// Iff A == B == C, B and C are left out. |
|
5074 |
// |
|
5075 |
// The instructions are ordered according to the following scheme: |
|
5076 |
// - loads |
|
5077 |
// - load constants |
|
5078 |
// - prefetch |
|
5079 |
// - store |
|
5080 |
// - encode/decode |
|
5081 |
// - membar |
|
5082 |
// - conditional moves |
|
5083 |
// - compare & swap |
|
5084 |
// - arithmetic and logic operations |
|
5085 |
// * int: Add, Sub, Mul, Div, Mod |
|
5086 |
// * int: lShift, arShift, urShift, rot |
|
5087 |
// * float: Add, Sub, Mul, Div |
|
5088 |
// * and, or, xor ... |
|
5089 |
// - register moves: float <-> int, reg <-> stack, repl |
|
5090 |
// - cast (high level type cast, XtoP, castPP, castII, not_null etc. |
|
5091 |
// - conv (low level type cast requiring bit changes (sign extend etc) |
|
5092 |
// - compares, range & zero checks. |
|
5093 |
// - branches |
|
5094 |
// - complex operations, intrinsics, min, max, replicate |
|
5095 |
// - lock |
|
5096 |
// - Calls |
|
5097 |
// |
|
5098 |
// If there are similar instructions with different types they are sorted: |
|
5099 |
// int before float |
|
5100 |
// small before big |
|
5101 |
// signed before unsigned |
|
5102 |
// e.g., loadS before loadUS before loadI before loadF. |
|
5103 |
||
5104 |
||
5105 |
//----------Load/Store Instructions-------------------------------------------- |
|
5106 |
||
5107 |
//----------Load Instructions-------------------------------------------------- |
|
5108 |
||
5109 |
// Converts byte to int. |
|
5110 |
// As convB2I_reg, but without match rule. The match rule of convB2I_reg |
|
5111 |
// reuses the 'amount' operand, but adlc expects that operand specification |
|
5112 |
// and operands in match rule are equivalent. |
|
5113 |
instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
|
|
5114 |
effect(DEF dst, USE src); |
|
5115 |
format %{ "EXTSB $dst, $src \t// byte->int" %}
|
|
5116 |
size(4); |
|
5117 |
ins_encode %{
|
|
5118 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsb); |
|
5119 |
__ extsb($dst$$Register, $src$$Register); |
|
5120 |
%} |
|
5121 |
ins_pipe(pipe_class_default); |
|
5122 |
%} |
|
5123 |
||
5124 |
instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
|
|
5125 |
// match-rule, false predicate |
|
5126 |
match(Set dst (LoadB mem)); |
|
5127 |
predicate(false); |
|
5128 |
||
5129 |
format %{ "LBZ $dst, $mem" %}
|
|
5130 |
size(4); |
|
5131 |
ins_encode( enc_lbz(dst, mem) ); |
|
5132 |
ins_pipe(pipe_class_memory); |
|
5133 |
%} |
|
5134 |
||
5135 |
instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
|
|
5136 |
// match-rule, false predicate |
|
5137 |
match(Set dst (LoadB mem)); |
|
5138 |
predicate(false); |
|
5139 |
||
5140 |
format %{ "LBZ $dst, $mem\n\t"
|
|
5141 |
"TWI $dst\n\t" |
|
5142 |
"ISYNC" %} |
|
5143 |
size(12); |
|
5144 |
ins_encode( enc_lbz_ac(dst, mem) ); |
|
5145 |
ins_pipe(pipe_class_memory); |
|
5146 |
%} |
|
5147 |
||
5148 |
// Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. |
|
5149 |
instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
|
|
5150 |
match(Set dst (LoadB mem)); |
|
5151 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5152 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5153 |
expand %{
|
|
5154 |
iRegIdst tmp; |
|
5155 |
loadUB_indirect(tmp, mem); |
|
5156 |
convB2I_reg_2(dst, tmp); |
|
5157 |
%} |
|
5158 |
%} |
|
5159 |
||
5160 |
instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
|
|
5161 |
match(Set dst (LoadB mem)); |
|
5162 |
ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); |
|
5163 |
expand %{
|
|
5164 |
iRegIdst tmp; |
|
5165 |
loadUB_indirect_ac(tmp, mem); |
|
5166 |
convB2I_reg_2(dst, tmp); |
|
5167 |
%} |
|
5168 |
%} |
|
5169 |
||
5170 |
instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
|
|
5171 |
// match-rule, false predicate |
|
5172 |
match(Set dst (LoadB mem)); |
|
5173 |
predicate(false); |
|
5174 |
||
5175 |
format %{ "LBZ $dst, $mem" %}
|
|
5176 |
size(4); |
|
5177 |
ins_encode( enc_lbz(dst, mem) ); |
|
5178 |
ins_pipe(pipe_class_memory); |
|
5179 |
%} |
|
5180 |
||
5181 |
instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
|
|
5182 |
// match-rule, false predicate |
|
5183 |
match(Set dst (LoadB mem)); |
|
5184 |
predicate(false); |
|
5185 |
||
5186 |
format %{ "LBZ $dst, $mem\n\t"
|
|
5187 |
"TWI $dst\n\t" |
|
5188 |
"ISYNC" %} |
|
5189 |
size(12); |
|
5190 |
ins_encode( enc_lbz_ac(dst, mem) ); |
|
5191 |
ins_pipe(pipe_class_memory); |
|
5192 |
%} |
|
5193 |
||
5194 |
// Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. |
|
5195 |
instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
|
|
5196 |
match(Set dst (LoadB mem)); |
|
5197 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5198 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5199 |
||
5200 |
expand %{
|
|
5201 |
iRegIdst tmp; |
|
5202 |
loadUB_indOffset16(tmp, mem); |
|
5203 |
convB2I_reg_2(dst, tmp); |
|
5204 |
%} |
|
5205 |
%} |
|
5206 |
||
5207 |
instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
|
|
5208 |
match(Set dst (LoadB mem)); |
|
5209 |
ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); |
|
5210 |
||
5211 |
expand %{
|
|
5212 |
iRegIdst tmp; |
|
5213 |
loadUB_indOffset16_ac(tmp, mem); |
|
5214 |
convB2I_reg_2(dst, tmp); |
|
5215 |
%} |
|
5216 |
%} |
|
5217 |
||
5218 |
// Load Unsigned Byte (8bit UNsigned) into an int reg. |
|
5219 |
instruct loadUB(iRegIdst dst, memory mem) %{
|
|
5220 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5221 |
match(Set dst (LoadUB mem)); |
|
5222 |
ins_cost(MEMORY_REF_COST); |
|
5223 |
||
5224 |
format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
|
|
5225 |
size(4); |
|
5226 |
ins_encode( enc_lbz(dst, mem) ); |
|
5227 |
ins_pipe(pipe_class_memory); |
|
5228 |
%} |
|
5229 |
||
5230 |
// Load Unsigned Byte (8bit UNsigned) acquire. |
|
5231 |
instruct loadUB_ac(iRegIdst dst, memory mem) %{
|
|
5232 |
match(Set dst (LoadUB mem)); |
|
5233 |
ins_cost(3*MEMORY_REF_COST); |
|
5234 |
||
5235 |
format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
|
|
5236 |
"TWI $dst\n\t" |
|
5237 |
"ISYNC" %} |
|
5238 |
size(12); |
|
5239 |
ins_encode( enc_lbz_ac(dst, mem) ); |
|
5240 |
ins_pipe(pipe_class_memory); |
|
5241 |
%} |
|
5242 |
||
5243 |
// Load Unsigned Byte (8bit UNsigned) into a Long Register. |
|
5244 |
instruct loadUB2L(iRegLdst dst, memory mem) %{
|
|
5245 |
match(Set dst (ConvI2L (LoadUB mem))); |
|
5246 |
predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); |
|
5247 |
ins_cost(MEMORY_REF_COST); |
|
5248 |
||
5249 |
format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
|
|
5250 |
size(4); |
|
5251 |
ins_encode( enc_lbz(dst, mem) ); |
|
5252 |
ins_pipe(pipe_class_memory); |
|
5253 |
%} |
|
5254 |
||
5255 |
instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
|
|
5256 |
match(Set dst (ConvI2L (LoadUB mem))); |
|
5257 |
ins_cost(3*MEMORY_REF_COST); |
|
5258 |
||
5259 |
format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
|
|
5260 |
"TWI $dst\n\t" |
|
5261 |
"ISYNC" %} |
|
5262 |
size(12); |
|
5263 |
ins_encode( enc_lbz_ac(dst, mem) ); |
|
5264 |
ins_pipe(pipe_class_memory); |
|
5265 |
%} |
|
5266 |
||
5267 |
// Load Short (16bit signed) |
|
5268 |
instruct loadS(iRegIdst dst, memory mem) %{
|
|
5269 |
match(Set dst (LoadS mem)); |
|
5270 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5271 |
ins_cost(MEMORY_REF_COST); |
|
5272 |
||
5273 |
format %{ "LHA $dst, $mem" %}
|
|
5274 |
size(4); |
|
5275 |
ins_encode %{
|
|
5276 |
// TODO: PPC port $archOpcode(ppc64Opcode_lha); |
|
5277 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5278 |
__ lha($dst$$Register, Idisp, $mem$$base$$Register); |
|
5279 |
%} |
|
5280 |
ins_pipe(pipe_class_memory); |
|
5281 |
%} |
|
5282 |
||
5283 |
// Load Short (16bit signed) acquire. |
|
5284 |
instruct loadS_ac(iRegIdst dst, memory mem) %{
|
|
5285 |
match(Set dst (LoadS mem)); |
|
5286 |
ins_cost(3*MEMORY_REF_COST); |
|
5287 |
||
5288 |
format %{ "LHA $dst, $mem\t acquire\n\t"
|
|
5289 |
"TWI $dst\n\t" |
|
5290 |
"ISYNC" %} |
|
5291 |
size(12); |
|
5292 |
ins_encode %{
|
|
5293 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5294 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5295 |
__ lha($dst$$Register, Idisp, $mem$$base$$Register); |
|
5296 |
__ twi_0($dst$$Register); |
|
5297 |
__ isync(); |
|
5298 |
%} |
|
5299 |
ins_pipe(pipe_class_memory); |
|
5300 |
%} |
|
5301 |
||
5302 |
// Load Char (16bit unsigned) |
|
5303 |
instruct loadUS(iRegIdst dst, memory mem) %{
|
|
5304 |
match(Set dst (LoadUS mem)); |
|
5305 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5306 |
ins_cost(MEMORY_REF_COST); |
|
5307 |
||
5308 |
format %{ "LHZ $dst, $mem" %}
|
|
5309 |
size(4); |
|
5310 |
ins_encode( enc_lhz(dst, mem) ); |
|
5311 |
ins_pipe(pipe_class_memory); |
|
5312 |
%} |
|
5313 |
||
5314 |
// Load Char (16bit unsigned) acquire. |
|
5315 |
instruct loadUS_ac(iRegIdst dst, memory mem) %{
|
|
5316 |
match(Set dst (LoadUS mem)); |
|
5317 |
ins_cost(3*MEMORY_REF_COST); |
|
5318 |
||
5319 |
format %{ "LHZ $dst, $mem \t// acquire\n\t"
|
|
5320 |
"TWI $dst\n\t" |
|
5321 |
"ISYNC" %} |
|
5322 |
size(12); |
|
5323 |
ins_encode( enc_lhz_ac(dst, mem) ); |
|
5324 |
ins_pipe(pipe_class_memory); |
|
5325 |
%} |
|
5326 |
||
5327 |
// Load Unsigned Short/Char (16bit UNsigned) into a Long Register. |
|
5328 |
instruct loadUS2L(iRegLdst dst, memory mem) %{
|
|
5329 |
match(Set dst (ConvI2L (LoadUS mem))); |
|
5330 |
predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); |
|
5331 |
ins_cost(MEMORY_REF_COST); |
|
5332 |
||
5333 |
format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
|
|
5334 |
size(4); |
|
5335 |
ins_encode( enc_lhz(dst, mem) ); |
|
5336 |
ins_pipe(pipe_class_memory); |
|
5337 |
%} |
|
5338 |
||
5339 |
// Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. |
|
5340 |
instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
|
|
5341 |
match(Set dst (ConvI2L (LoadUS mem))); |
|
5342 |
ins_cost(3*MEMORY_REF_COST); |
|
5343 |
||
5344 |
format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
|
|
5345 |
"TWI $dst\n\t" |
|
5346 |
"ISYNC" %} |
|
5347 |
size(12); |
|
5348 |
ins_encode( enc_lhz_ac(dst, mem) ); |
|
5349 |
ins_pipe(pipe_class_memory); |
|
5350 |
%} |
|
5351 |
||
5352 |
// Load Integer. |
|
5353 |
instruct loadI(iRegIdst dst, memory mem) %{
|
|
5354 |
match(Set dst (LoadI mem)); |
|
5355 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5356 |
ins_cost(MEMORY_REF_COST); |
|
5357 |
||
5358 |
format %{ "LWZ $dst, $mem" %}
|
|
5359 |
size(4); |
|
5360 |
ins_encode( enc_lwz(dst, mem) ); |
|
5361 |
ins_pipe(pipe_class_memory); |
|
5362 |
%} |
|
5363 |
||
5364 |
// Load Integer acquire. |
|
5365 |
instruct loadI_ac(iRegIdst dst, memory mem) %{
|
|
5366 |
match(Set dst (LoadI mem)); |
|
5367 |
ins_cost(3*MEMORY_REF_COST); |
|
5368 |
||
5369 |
format %{ "LWZ $dst, $mem \t// load acquire\n\t"
|
|
5370 |
"TWI $dst\n\t" |
|
5371 |
"ISYNC" %} |
|
5372 |
size(12); |
|
5373 |
ins_encode( enc_lwz_ac(dst, mem) ); |
|
5374 |
ins_pipe(pipe_class_memory); |
|
5375 |
%} |
|
5376 |
||
5377 |
// Match loading integer and casting it to unsigned int in |
|
5378 |
// long register. |
|
5379 |
// LoadI + ConvI2L + AndL 0xffffffff. |
|
5380 |
instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
|
|
5381 |
match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); |
|
5382 |
predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5383 |
ins_cost(MEMORY_REF_COST); |
|
5384 |
||
5385 |
format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
|
|
5386 |
size(4); |
|
5387 |
ins_encode( enc_lwz(dst, mem) ); |
|
5388 |
ins_pipe(pipe_class_memory); |
|
5389 |
%} |
|
5390 |
||
5391 |
// Match loading integer and casting it to long. |
|
5392 |
instruct loadI2L(iRegLdst dst, memory mem) %{
|
|
5393 |
match(Set dst (ConvI2L (LoadI mem))); |
|
5394 |
predicate(_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5395 |
ins_cost(MEMORY_REF_COST); |
|
5396 |
||
5397 |
format %{ "LWA $dst, $mem \t// loadI2L" %}
|
|
5398 |
size(4); |
|
5399 |
ins_encode %{
|
|
5400 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwa); |
|
5401 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5402 |
__ lwa($dst$$Register, Idisp, $mem$$base$$Register); |
|
5403 |
%} |
|
5404 |
ins_pipe(pipe_class_memory); |
|
5405 |
%} |
|
5406 |
||
5407 |
// Match loading integer and casting it to long - acquire. |
|
5408 |
instruct loadI2L_ac(iRegLdst dst, memory mem) %{
|
|
5409 |
match(Set dst (ConvI2L (LoadI mem))); |
|
5410 |
ins_cost(3*MEMORY_REF_COST); |
|
5411 |
||
5412 |
format %{ "LWA $dst, $mem \t// loadI2L acquire"
|
|
5413 |
"TWI $dst\n\t" |
|
5414 |
"ISYNC" %} |
|
5415 |
size(12); |
|
5416 |
ins_encode %{
|
|
5417 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwa); |
|
5418 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5419 |
__ lwa($dst$$Register, Idisp, $mem$$base$$Register); |
|
5420 |
__ twi_0($dst$$Register); |
|
5421 |
__ isync(); |
|
5422 |
%} |
|
5423 |
ins_pipe(pipe_class_memory); |
|
5424 |
%} |
|
5425 |
||
5426 |
// Load Long - aligned |
|
5427 |
instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
|
|
5428 |
match(Set dst (LoadL mem)); |
|
5429 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5430 |
ins_cost(MEMORY_REF_COST); |
|
5431 |
||
5432 |
format %{ "LD $dst, $mem \t// long" %}
|
|
5433 |
size(4); |
|
5434 |
ins_encode( enc_ld(dst, mem) ); |
|
5435 |
ins_pipe(pipe_class_memory); |
|
5436 |
%} |
|
5437 |
||
5438 |
// Load Long - aligned acquire. |
|
5439 |
instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
|
|
5440 |
match(Set dst (LoadL mem)); |
|
5441 |
ins_cost(3*MEMORY_REF_COST); |
|
5442 |
||
5443 |
format %{ "LD $dst, $mem \t// long acquire\n\t"
|
|
5444 |
"TWI $dst\n\t" |
|
5445 |
"ISYNC" %} |
|
5446 |
size(12); |
|
5447 |
ins_encode( enc_ld_ac(dst, mem) ); |
|
5448 |
ins_pipe(pipe_class_memory); |
|
5449 |
%} |
|
5450 |
||
5451 |
// Load Long - UNaligned |
|
5452 |
instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
|
|
5453 |
match(Set dst (LoadL_unaligned mem)); |
|
5454 |
// predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). |
|
5455 |
ins_cost(MEMORY_REF_COST); |
|
5456 |
||
5457 |
format %{ "LD $dst, $mem \t// unaligned long" %}
|
|
5458 |
size(4); |
|
5459 |
ins_encode( enc_ld(dst, mem) ); |
|
5460 |
ins_pipe(pipe_class_memory); |
|
5461 |
%} |
|
5462 |
||
5463 |
// Load nodes for superwords |
|
5464 |
||
5465 |
// Load Aligned Packed Byte |
|
5466 |
instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
|
|
5467 |
predicate(n->as_LoadVector()->memory_size() == 8); |
|
5468 |
match(Set dst (LoadVector mem)); |
|
5469 |
ins_cost(MEMORY_REF_COST); |
|
5470 |
||
5471 |
format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
|
|
5472 |
size(4); |
|
5473 |
ins_encode( enc_ld(dst, mem) ); |
|
5474 |
ins_pipe(pipe_class_memory); |
|
5475 |
%} |
|
5476 |
||
5477 |
// Load Range, range = array length (=jint) |
|
5478 |
instruct loadRange(iRegIdst dst, memory mem) %{
|
|
5479 |
match(Set dst (LoadRange mem)); |
|
5480 |
ins_cost(MEMORY_REF_COST); |
|
5481 |
||
5482 |
format %{ "LWZ $dst, $mem \t// range" %}
|
|
5483 |
size(4); |
|
5484 |
ins_encode( enc_lwz(dst, mem) ); |
|
5485 |
ins_pipe(pipe_class_memory); |
|
5486 |
%} |
|
5487 |
||
5488 |
// Load Compressed Pointer |
|
5489 |
instruct loadN(iRegNdst dst, memory mem) %{
|
|
5490 |
match(Set dst (LoadN mem)); |
|
5491 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5492 |
ins_cost(MEMORY_REF_COST); |
|
5493 |
||
5494 |
format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
|
|
5495 |
size(4); |
|
5496 |
ins_encode( enc_lwz(dst, mem) ); |
|
5497 |
ins_pipe(pipe_class_memory); |
|
5498 |
%} |
|
5499 |
||
5500 |
// Load Compressed Pointer acquire. |
|
5501 |
instruct loadN_ac(iRegNdst dst, memory mem) %{
|
|
5502 |
match(Set dst (LoadN mem)); |
|
5503 |
ins_cost(3*MEMORY_REF_COST); |
|
5504 |
||
5505 |
format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
|
|
5506 |
"TWI $dst\n\t" |
|
5507 |
"ISYNC" %} |
|
5508 |
size(12); |
|
5509 |
ins_encode( enc_lwz_ac(dst, mem) ); |
|
5510 |
ins_pipe(pipe_class_memory); |
|
5511 |
%} |
|
5512 |
||
5513 |
// Load Compressed Pointer and decode it if narrow_oop_shift == 0. |
|
5514 |
instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
|
|
5515 |
match(Set dst (DecodeN (LoadN mem))); |
|
5516 |
predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); |
|
5517 |
ins_cost(MEMORY_REF_COST); |
|
5518 |
||
5519 |
format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
|
|
5520 |
size(4); |
|
5521 |
ins_encode( enc_lwz(dst, mem) ); |
|
5522 |
ins_pipe(pipe_class_memory); |
|
5523 |
%} |
|
5524 |
||
5525 |
// Load Pointer |
|
5526 |
instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
|
|
5527 |
match(Set dst (LoadP mem)); |
|
5528 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5529 |
ins_cost(MEMORY_REF_COST); |
|
5530 |
||
5531 |
format %{ "LD $dst, $mem \t// ptr" %}
|
|
5532 |
size(4); |
|
5533 |
ins_encode( enc_ld(dst, mem) ); |
|
5534 |
ins_pipe(pipe_class_memory); |
|
5535 |
%} |
|
5536 |
||
5537 |
// Load Pointer acquire. |
|
5538 |
instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
|
|
5539 |
match(Set dst (LoadP mem)); |
|
5540 |
ins_cost(3*MEMORY_REF_COST); |
|
5541 |
||
5542 |
format %{ "LD $dst, $mem \t// ptr acquire\n\t"
|
|
5543 |
"TWI $dst\n\t" |
|
5544 |
"ISYNC" %} |
|
5545 |
size(12); |
|
5546 |
ins_encode( enc_ld_ac(dst, mem) ); |
|
5547 |
ins_pipe(pipe_class_memory); |
|
5548 |
%} |
|
5549 |
||
5550 |
// LoadP + CastP2L |
|
5551 |
instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
|
|
5552 |
match(Set dst (CastP2X (LoadP mem))); |
|
5553 |
predicate(_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5554 |
ins_cost(MEMORY_REF_COST); |
|
5555 |
||
5556 |
format %{ "LD $dst, $mem \t// ptr + p2x" %}
|
|
5557 |
size(4); |
|
5558 |
ins_encode( enc_ld(dst, mem) ); |
|
5559 |
ins_pipe(pipe_class_memory); |
|
5560 |
%} |
|
5561 |
||
5562 |
// Load compressed klass pointer. |
|
5563 |
instruct loadNKlass(iRegNdst dst, memory mem) %{
|
|
5564 |
match(Set dst (LoadNKlass mem)); |
|
5565 |
ins_cost(MEMORY_REF_COST); |
|
5566 |
||
5567 |
format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
|
|
5568 |
size(4); |
|
5569 |
ins_encode( enc_lwz(dst, mem) ); |
|
5570 |
ins_pipe(pipe_class_memory); |
|
5571 |
%} |
|
5572 |
||
5573 |
//// Load compressed klass and decode it if narrow_klass_shift == 0. |
|
5574 |
//// TODO: will narrow_klass_shift ever be 0? |
|
5575 |
//instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
|
|
5576 |
// match(Set dst (DecodeNKlass (LoadNKlass mem))); |
|
5577 |
// predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*); |
|
5578 |
// ins_cost(MEMORY_REF_COST); |
|
5579 |
// |
|
5580 |
// format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
|
|
5581 |
// size(4); |
|
5582 |
// ins_encode( enc_lwz(dst, mem) ); |
|
5583 |
// ins_pipe(pipe_class_memory); |
|
5584 |
//%} |
|
5585 |
||
5586 |
// Load Klass Pointer |
|
5587 |
instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
|
|
5588 |
match(Set dst (LoadKlass mem)); |
|
5589 |
ins_cost(MEMORY_REF_COST); |
|
5590 |
||
5591 |
format %{ "LD $dst, $mem \t// klass ptr" %}
|
|
5592 |
size(4); |
|
5593 |
ins_encode( enc_ld(dst, mem) ); |
|
5594 |
ins_pipe(pipe_class_memory); |
|
5595 |
%} |
|
5596 |
||
5597 |
// Load Float |
|
5598 |
instruct loadF(regF dst, memory mem) %{
|
|
5599 |
match(Set dst (LoadF mem)); |
|
5600 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5601 |
ins_cost(MEMORY_REF_COST); |
|
5602 |
||
5603 |
format %{ "LFS $dst, $mem" %}
|
|
5604 |
size(4); |
|
5605 |
ins_encode %{
|
|
5606 |
// TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
5607 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5608 |
__ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5609 |
%} |
|
5610 |
ins_pipe(pipe_class_memory); |
|
5611 |
%} |
|
5612 |
||
5613 |
// Load Float acquire. |
|
5614 |
instruct loadF_ac(regF dst, memory mem) %{
|
|
5615 |
match(Set dst (LoadF mem)); |
|
5616 |
ins_cost(3*MEMORY_REF_COST); |
|
5617 |
||
5618 |
format %{ "LFS $dst, $mem \t// acquire\n\t"
|
|
5619 |
"FCMPU cr0, $dst, $dst\n\t" |
|
5620 |
"BNE cr0, next\n" |
|
5621 |
"next:\n\t" |
|
5622 |
"ISYNC" %} |
|
5623 |
size(16); |
|
5624 |
ins_encode %{
|
|
5625 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5626 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5627 |
Label next; |
|
5628 |
__ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5629 |
__ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); |
|
5630 |
__ bne(CCR0, next); |
|
5631 |
__ bind(next); |
|
5632 |
__ isync(); |
|
5633 |
%} |
|
5634 |
ins_pipe(pipe_class_memory); |
|
5635 |
%} |
|
5636 |
||
5637 |
// Load Double - aligned |
|
5638 |
instruct loadD(regD dst, memory mem) %{
|
|
5639 |
match(Set dst (LoadD mem)); |
|
5640 |
predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5641 |
ins_cost(MEMORY_REF_COST); |
|
5642 |
||
5643 |
format %{ "LFD $dst, $mem" %}
|
|
5644 |
size(4); |
|
5645 |
ins_encode( enc_lfd(dst, mem) ); |
|
5646 |
ins_pipe(pipe_class_memory); |
|
5647 |
%} |
|
5648 |
||
5649 |
// Load Double - aligned acquire. |
|
5650 |
instruct loadD_ac(regD dst, memory mem) %{
|
|
5651 |
match(Set dst (LoadD mem)); |
|
5652 |
ins_cost(3*MEMORY_REF_COST); |
|
5653 |
||
5654 |
format %{ "LFD $dst, $mem \t// acquire\n\t"
|
|
5655 |
"FCMPU cr0, $dst, $dst\n\t" |
|
5656 |
"BNE cr0, next\n" |
|
5657 |
"next:\n\t" |
|
5658 |
"ISYNC" %} |
|
5659 |
size(16); |
|
5660 |
ins_encode %{
|
|
5661 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5662 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5663 |
Label next; |
|
5664 |
__ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5665 |
__ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); |
|
5666 |
__ bne(CCR0, next); |
|
5667 |
__ bind(next); |
|
5668 |
__ isync(); |
|
5669 |
%} |
|
5670 |
ins_pipe(pipe_class_memory); |
|
5671 |
%} |
|
5672 |
||
5673 |
// Load Double - UNaligned |
|
5674 |
instruct loadD_unaligned(regD dst, memory mem) %{
|
|
5675 |
match(Set dst (LoadD_unaligned mem)); |
|
5676 |
// predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). |
|
5677 |
ins_cost(MEMORY_REF_COST); |
|
5678 |
||
5679 |
format %{ "LFD $dst, $mem" %}
|
|
5680 |
size(4); |
|
5681 |
ins_encode( enc_lfd(dst, mem) ); |
|
5682 |
ins_pipe(pipe_class_memory); |
|
5683 |
%} |
|
5684 |
||
5685 |
//----------Constants-------------------------------------------------------- |
|
5686 |
||
5687 |
// Load MachConstantTableBase: add hi offset to global toc. |
|
5688 |
// TODO: Handle hidden register r29 in bundler! |
|
5689 |
instruct loadToc_hi(iRegLdst dst) %{
|
|
5690 |
effect(DEF dst); |
|
5691 |
ins_cost(DEFAULT_COST); |
|
5692 |
||
5693 |
format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
|
|
5694 |
size(4); |
|
5695 |
ins_encode %{
|
|
5696 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5697 |
__ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); |
|
5698 |
%} |
|
5699 |
ins_pipe(pipe_class_default); |
|
5700 |
%} |
|
5701 |
||
5702 |
// Load MachConstantTableBase: add lo offset to global toc. |
|
5703 |
instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
|
|
5704 |
effect(DEF dst, USE src); |
|
5705 |
ins_cost(DEFAULT_COST); |
|
5706 |
||
5707 |
format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
|
|
5708 |
size(4); |
|
5709 |
ins_encode %{
|
|
5710 |
// TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5711 |
__ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); |
|
5712 |
%} |
|
5713 |
ins_pipe(pipe_class_default); |
|
5714 |
%} |
|
5715 |
||
5716 |
// Load 16-bit integer constant 0xssss???? |
|
5717 |
instruct loadConI16(iRegIdst dst, immI16 src) %{
|
|
5718 |
match(Set dst src); |
|
5719 |
||
5720 |
format %{ "LI $dst, $src" %}
|
|
5721 |
size(4); |
|
5722 |
ins_encode %{
|
|
5723 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5724 |
__ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
5725 |
%} |
|
5726 |
ins_pipe(pipe_class_default); |
|
5727 |
%} |
|
5728 |
||
5729 |
// Load integer constant 0x????0000 |
|
5730 |
instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
|
|
5731 |
match(Set dst src); |
|
5732 |
ins_cost(DEFAULT_COST); |
|
5733 |
||
5734 |
format %{ "LIS $dst, $src.hi" %}
|
|
5735 |
size(4); |
|
5736 |
ins_encode %{
|
|
5737 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5738 |
// Lis sign extends 16-bit src then shifts it 16 bit to the left. |
|
5739 |
__ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); |
|
5740 |
%} |
|
5741 |
ins_pipe(pipe_class_default); |
|
5742 |
%} |
|
5743 |
||
5744 |
// Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted |
|
5745 |
// and sign extended), this adds the low 16 bits. |
|
5746 |
instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
|
|
5747 |
// no match-rule, false predicate |
|
5748 |
effect(DEF dst, USE src1, USE src2); |
|
5749 |
predicate(false); |
|
5750 |
||
5751 |
format %{ "ORI $dst, $src1.hi, $src2.lo" %}
|
|
5752 |
size(4); |
|
5753 |
ins_encode %{
|
|
5754 |
// TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5755 |
__ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
5756 |
%} |
|
5757 |
ins_pipe(pipe_class_default); |
|
5758 |
%} |
|
5759 |
||
5760 |
instruct loadConI_Ex(iRegIdst dst, immI src) %{
|
|
5761 |
match(Set dst src); |
|
5762 |
ins_cost(DEFAULT_COST*2); |
|
5763 |
||
5764 |
expand %{
|
|
5765 |
// Would like to use $src$$constant. |
|
5766 |
immI16 srcLo %{ _opnds[1]->constant() %}
|
|
5767 |
// srcHi can be 0000 if srcLo sign-extends to a negative number. |
|
5768 |
immIhi16 srcHi %{ _opnds[1]->constant() %}
|
|
5769 |
iRegIdst tmpI; |
|
5770 |
loadConIhi16(tmpI, srcHi); |
|
5771 |
loadConI32_lo16(dst, tmpI, srcLo); |
|
5772 |
%} |
|
5773 |
%} |
|
5774 |
||
5775 |
// No constant pool entries required. |
|
5776 |
instruct loadConL16(iRegLdst dst, immL16 src) %{
|
|
5777 |
match(Set dst src); |
|
5778 |
||
5779 |
format %{ "LI $dst, $src \t// long" %}
|
|
5780 |
size(4); |
|
5781 |
ins_encode %{
|
|
5782 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5783 |
__ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); |
|
5784 |
%} |
|
5785 |
ins_pipe(pipe_class_default); |
|
5786 |
%} |
|
5787 |
||
5788 |
// Load long constant 0xssssssss????0000 |
|
5789 |
instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
|
|
5790 |
match(Set dst src); |
|
5791 |
ins_cost(DEFAULT_COST); |
|
5792 |
||
5793 |
format %{ "LIS $dst, $src.hi \t// long" %}
|
|
5794 |
size(4); |
|
5795 |
ins_encode %{
|
|
5796 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5797 |
__ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); |
|
5798 |
%} |
|
5799 |
ins_pipe(pipe_class_default); |
|
5800 |
%} |
|
5801 |
||
5802 |
// To load a 32 bit constant: merge lower 16 bits into already loaded |
|
5803 |
// high 16 bits. |
|
5804 |
instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
|
|
5805 |
// no match-rule, false predicate |
|
5806 |
effect(DEF dst, USE src1, USE src2); |
|
5807 |
predicate(false); |
|
5808 |
||
5809 |
format %{ "ORI $dst, $src1, $src2.lo" %}
|
|
5810 |
size(4); |
|
5811 |
ins_encode %{
|
|
5812 |
// TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5813 |
__ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
5814 |
%} |
|
5815 |
ins_pipe(pipe_class_default); |
|
5816 |
%} |
|
5817 |
||
5818 |
// Load 32-bit long constant |
|
5819 |
instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
|
|
5820 |
match(Set dst src); |
|
5821 |
ins_cost(DEFAULT_COST*2); |
|
5822 |
||
5823 |
expand %{
|
|
5824 |
// Would like to use $src$$constant. |
|
5825 |
immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
|
|
5826 |
// srcHi can be 0000 if srcLo sign-extends to a negative number. |
|
5827 |
immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
|
|
5828 |
iRegLdst tmpL; |
|
5829 |
loadConL32hi16(tmpL, srcHi); |
|
5830 |
loadConL32_lo16(dst, tmpL, srcLo); |
|
5831 |
%} |
|
5832 |
%} |
|
5833 |
||
5834 |
// Load long constant 0x????000000000000. |
|
5835 |
instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
|
|
5836 |
match(Set dst src); |
|
5837 |
ins_cost(DEFAULT_COST); |
|
5838 |
||
5839 |
expand %{
|
|
5840 |
immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
|
|
5841 |
immI shift32 %{ 32 %}
|
|
5842 |
iRegLdst tmpL; |
|
5843 |
loadConL32hi16(tmpL, srcHi); |
|
5844 |
lshiftL_regL_immI(dst, tmpL, shift32); |
|
5845 |
%} |
|
5846 |
%} |
|
5847 |
||
5848 |
// Expand node for constant pool load: small offset. |
|
5849 |
instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
|
|
5850 |
effect(DEF dst, USE src, USE toc); |
|
5851 |
ins_cost(MEMORY_REF_COST); |
|
5852 |
||
5853 |
ins_num_consts(1); |
|
5854 |
// Needed so that CallDynamicJavaDirect can compute the address of this |
|
5855 |
// instruction for relocation. |
|
5856 |
ins_field_cbuf_insts_offset(int); |
|
5857 |
||
5858 |
format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
|
|
5859 |
size(4); |
|
5860 |
ins_encode( enc_load_long_constL(dst, src, toc) ); |
|
5861 |
ins_pipe(pipe_class_memory); |
|
5862 |
%} |
|
5863 |
||
5864 |
// Expand node for constant pool load: large offset. |
|
5865 |
instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
|
|
5866 |
effect(DEF dst, USE src, USE toc); |
|
5867 |
predicate(false); |
|
5868 |
||
5869 |
ins_num_consts(1); |
|
5870 |
ins_field_const_toc_offset(int); |
|
5871 |
// Needed so that CallDynamicJavaDirect can compute the address of this |
|
5872 |
// instruction for relocation. |
|
5873 |
ins_field_cbuf_insts_offset(int); |
|
5874 |
||
5875 |
format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
|
|
5876 |
size(4); |
|
5877 |
ins_encode( enc_load_long_constL_hi(dst, toc, src) ); |
|
5878 |
ins_pipe(pipe_class_default); |
|
5879 |
%} |
|
5880 |
||
5881 |
// Expand node for constant pool load: large offset. |
|
5882 |
// No constant pool entries required. |
|
5883 |
instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
|
|
5884 |
effect(DEF dst, USE src, USE base); |
|
5885 |
predicate(false); |
|
5886 |
||
5887 |
ins_field_const_toc_offset_hi_node(loadConL_hiNode*); |
|
5888 |
||
5889 |
format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
|
|
5890 |
size(4); |
|
5891 |
ins_encode %{
|
|
5892 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
5893 |
int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; |
|
5894 |
__ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); |
|
5895 |
%} |
|
5896 |
ins_pipe(pipe_class_memory); |
|
5897 |
%} |
|
5898 |
||
5899 |
// Load long constant from constant table. Expand in case of |
|
5900 |
// offset > 16 bit is needed. |
|
5901 |
// Adlc adds toc node MachConstantTableBase. |
|
5902 |
instruct loadConL_Ex(iRegLdst dst, immL src) %{
|
|
5903 |
match(Set dst src); |
|
5904 |
ins_cost(MEMORY_REF_COST); |
|
5905 |
||
5906 |
format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
|
|
5907 |
// We can not inline the enc_class for the expand as that does not support constanttablebase. |
|
5908 |
postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); |
|
5909 |
%} |
|
5910 |
||
5911 |
// Load NULL as compressed oop. |
|
5912 |
instruct loadConN0(iRegNdst dst, immN_0 src) %{
|
|
5913 |
match(Set dst src); |
|
5914 |
ins_cost(DEFAULT_COST); |
|
5915 |
||
5916 |
format %{ "LI $dst, $src \t// compressed ptr" %}
|
|
5917 |
size(4); |
|
5918 |
ins_encode %{
|
|
5919 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5920 |
__ li($dst$$Register, 0); |
|
5921 |
%} |
|
5922 |
ins_pipe(pipe_class_default); |
|
5923 |
%} |
|
5924 |
||
5925 |
// Load hi part of compressed oop constant. |
|
5926 |
instruct loadConN_hi(iRegNdst dst, immN src) %{
|
|
5927 |
effect(DEF dst, USE src); |
|
5928 |
ins_cost(DEFAULT_COST); |
|
5929 |
||
5930 |
format %{ "LIS $dst, $src \t// narrow oop hi" %}
|
|
5931 |
size(4); |
|
5932 |
ins_encode %{
|
|
5933 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5934 |
__ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); |
|
5935 |
%} |
|
5936 |
ins_pipe(pipe_class_default); |
|
5937 |
%} |
|
5938 |
||
5939 |
// Add lo part of compressed oop constant to already loaded hi part. |
|
5940 |
instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
|
|
5941 |
effect(DEF dst, USE src1, USE src2); |
|
5942 |
ins_cost(DEFAULT_COST); |
|
5943 |
||
5944 |
format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
|
|
5945 |
size(4); |
|
5946 |
ins_encode %{
|
|
5947 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5948 |
assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
5949 |
int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); |
|
5950 |
RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
5951 |
__ relocate(rspec, 1); |
|
5952 |
__ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); |
|
5953 |
%} |
|
5954 |
ins_pipe(pipe_class_default); |
|
5955 |
%} |
|
5956 |
||
5957 |
// Needed to postalloc expand loadConN: ConN is loaded as ConI |
|
5958 |
// leaving the upper 32 bits with sign-extension bits. |
|
5959 |
// This clears these bits: dst = src & 0xFFFFFFFF. |
|
5960 |
// TODO: Eventually call this maskN_regN_FFFFFFFF. |
|
5961 |
instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
|
|
5962 |
effect(DEF dst, USE src); |
|
5963 |
predicate(false); |
|
5964 |
||
5965 |
format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
|
|
5966 |
size(4); |
|
5967 |
ins_encode %{
|
|
5968 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
5969 |
__ clrldi($dst$$Register, $src$$Register, 0x20); |
|
5970 |
%} |
|
5971 |
ins_pipe(pipe_class_default); |
|
5972 |
%} |
|
5973 |
||
5974 |
// Loading ConN must be postalloc expanded so that edges between |
|
5975 |
// the nodes are safe. They may not interfere with a safepoint. |
|
5976 |
// GL TODO: This needs three instructions: better put this into the constant pool. |
|
5977 |
instruct loadConN_Ex(iRegNdst dst, immN src) %{
|
|
5978 |
match(Set dst src); |
|
5979 |
ins_cost(DEFAULT_COST*2); |
|
5980 |
||
5981 |
format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
|
|
5982 |
postalloc_expand %{
|
|
5983 |
MachNode *m1 = new (C) loadConN_hiNode(); |
|
5984 |
MachNode *m2 = new (C) loadConN_loNode(); |
|
5985 |
MachNode *m3 = new (C) clearMs32bNode(); |
|
5986 |
m1->add_req(NULL); |
|
5987 |
m2->add_req(NULL, m1); |
|
5988 |
m3->add_req(NULL, m2); |
|
5989 |
m1->_opnds[0] = op_dst; |
|
5990 |
m1->_opnds[1] = op_src; |
|
5991 |
m2->_opnds[0] = op_dst; |
|
5992 |
m2->_opnds[1] = op_dst; |
|
5993 |
m2->_opnds[2] = op_src; |
|
5994 |
m3->_opnds[0] = op_dst; |
|
5995 |
m3->_opnds[1] = op_dst; |
|
5996 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
5997 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
5998 |
ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
5999 |
nodes->push(m1); |
|
6000 |
nodes->push(m2); |
|
6001 |
nodes->push(m3); |
|
6002 |
%} |
|
6003 |
%} |
|
6004 |
||
6005 |
instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
|
|
6006 |
effect(DEF dst, USE src); |
|
6007 |
ins_cost(DEFAULT_COST); |
|
6008 |
||
6009 |
format %{ "LIS $dst, $src \t// narrow oop hi" %}
|
|
6010 |
size(4); |
|
6011 |
ins_encode %{
|
|
6012 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
6013 |
intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); |
|
6014 |
__ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); |
|
6015 |
%} |
|
6016 |
ins_pipe(pipe_class_default); |
|
6017 |
%} |
|
6018 |
||
6019 |
// This needs a match rule so that build_oop_map knows this is |
|
6020 |
// not a narrow oop. |
|
6021 |
instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
|
|
6022 |
match(Set dst src1); |
|
6023 |
effect(TEMP src2); |
|
6024 |
ins_cost(DEFAULT_COST); |
|
6025 |
||
6026 |
format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
|
|
6027 |
size(4); |
|
6028 |
ins_encode %{
|
|
6029 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
6030 |
intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); |
|
6031 |
assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
6032 |
int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); |
|
6033 |
RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
6034 |
||
6035 |
__ relocate(rspec, 1); |
|
6036 |
__ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); |
|
6037 |
%} |
|
6038 |
ins_pipe(pipe_class_default); |
|
6039 |
%} |
|
6040 |
||
6041 |
// Loading ConNKlass must be postalloc expanded so that edges between |
|
6042 |
// the nodes are safe. They may not interfere with a safepoint. |
|
6043 |
instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
|
|
6044 |
match(Set dst src); |
|
6045 |
ins_cost(DEFAULT_COST*2); |
|
6046 |
||
6047 |
format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
|
|
6048 |
postalloc_expand %{
|
|
6049 |
// Load high bits into register. Sign extended. |
|
6050 |
MachNode *m1 = new (C) loadConNKlass_hiNode(); |
|
6051 |
m1->add_req(NULL); |
|
6052 |
m1->_opnds[0] = op_dst; |
|
6053 |
m1->_opnds[1] = op_src; |
|
6054 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6055 |
nodes->push(m1); |
|
6056 |
||
6057 |
MachNode *m2 = m1; |
|
6058 |
if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
|
|
6059 |
// Value might be 1-extended. Mask out these bits. |
|
6060 |
m2 = new (C) clearMs32bNode(); |
|
6061 |
m2->add_req(NULL, m1); |
|
6062 |
m2->_opnds[0] = op_dst; |
|
6063 |
m2->_opnds[1] = op_dst; |
|
6064 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6065 |
nodes->push(m2); |
|
6066 |
} |
|
6067 |
||
6068 |
MachNode *m3 = new (C) loadConNKlass_loNode(); |
|
6069 |
m3->add_req(NULL, m2); |
|
6070 |
m3->_opnds[0] = op_dst; |
|
6071 |
m3->_opnds[1] = op_src; |
|
6072 |
m3->_opnds[2] = op_dst; |
|
6073 |
ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6074 |
nodes->push(m3); |
|
6075 |
%} |
|
6076 |
%} |
|
6077 |
||
6078 |
// 0x1 is used in object initialization (initial object header). |
|
6079 |
// No constant pool entries required. |
|
6080 |
instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
|
|
6081 |
match(Set dst src); |
|
6082 |
||
6083 |
format %{ "LI $dst, $src \t// ptr" %}
|
|
6084 |
size(4); |
|
6085 |
ins_encode %{
|
|
6086 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
6087 |
__ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
6088 |
%} |
|
6089 |
ins_pipe(pipe_class_default); |
|
6090 |
%} |
|
6091 |
||
6092 |
// Expand node for constant pool load: small offset. |
|
6093 |
// The match rule is needed to generate the correct bottom_type(), |
|
6094 |
// however this node should never match. The use of predicate is not |
|
6095 |
// possible since ADLC forbids predicates for chain rules. The higher |
|
6096 |
// costs do not prevent matching in this case. For that reason the |
|
6097 |
// operand immP_NM with predicate(false) is used. |
|
6098 |
instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
|
|
6099 |
match(Set dst src); |
|
6100 |
effect(TEMP toc); |
|
6101 |
||
6102 |
ins_num_consts(1); |
|
6103 |
||
6104 |
format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
|
|
6105 |
size(4); |
|
6106 |
ins_encode( enc_load_long_constP(dst, src, toc) ); |
|
6107 |
ins_pipe(pipe_class_memory); |
|
6108 |
%} |
|
6109 |
||
6110 |
// Expand node for constant pool load: large offset. |
|
6111 |
instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
|
|
6112 |
effect(DEF dst, USE src, USE toc); |
|
6113 |
predicate(false); |
|
6114 |
||
6115 |
ins_num_consts(1); |
|
6116 |
ins_field_const_toc_offset(int); |
|
6117 |
||
6118 |
format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
|
|
6119 |
size(4); |
|
6120 |
ins_encode( enc_load_long_constP_hi(dst, src, toc) ); |
|
6121 |
ins_pipe(pipe_class_default); |
|
6122 |
%} |
|
6123 |
||
6124 |
// Expand node for constant pool load: large offset. |
|
6125 |
instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
|
|
6126 |
match(Set dst src); |
|
6127 |
effect(TEMP base); |
|
6128 |
||
6129 |
ins_field_const_toc_offset_hi_node(loadConP_hiNode*); |
|
6130 |
||
6131 |
format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
|
|
6132 |
size(4); |
|
6133 |
ins_encode %{
|
|
6134 |
// TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
6135 |
int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; |
|
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
6136 |
__ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); |
| 22861 | 6137 |
%} |
6138 |
ins_pipe(pipe_class_memory); |
|
6139 |
%} |
|
6140 |
||
6141 |
// Load pointer constant from constant table. Expand in case an |
|
6142 |
// offset > 16 bit is needed. |
|
6143 |
// Adlc adds toc node MachConstantTableBase. |
|
6144 |
instruct loadConP_Ex(iRegPdst dst, immP src) %{
|
|
6145 |
match(Set dst src); |
|
6146 |
ins_cost(MEMORY_REF_COST); |
|
6147 |
||
6148 |
// This rule does not use "expand" because then |
|
6149 |
// the result type is not known to be an Oop. An ADLC |
|
6150 |
// enhancement will be needed to make that work - not worth it! |
|
6151 |
||
6152 |
// If this instruction rematerializes, it prolongs the live range |
|
6153 |
// of the toc node, causing illegal graphs. |
|
6154 |
// assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). |
|
6155 |
ins_cannot_rematerialize(true); |
|
6156 |
||
6157 |
format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
|
|
6158 |
postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); |
|
6159 |
%} |
|
6160 |
||
6161 |
// Expand node for constant pool load: small offset. |
|
6162 |
instruct loadConF(regF dst, immF src, iRegLdst toc) %{
|
|
6163 |
effect(DEF dst, USE src, USE toc); |
|
6164 |
ins_cost(MEMORY_REF_COST); |
|
6165 |
||
6166 |
ins_num_consts(1); |
|
6167 |
||
6168 |
format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
|
|
6169 |
size(4); |
|
6170 |
ins_encode %{
|
|
6171 |
// TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
6172 |
address float_address = __ float_constant($src$$constant); |
|
6173 |
__ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); |
|
6174 |
%} |
|
6175 |
ins_pipe(pipe_class_memory); |
|
6176 |
%} |
|
6177 |
||
6178 |
// Expand node for constant pool load: large offset. |
|
6179 |
instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
|
|
6180 |
effect(DEF dst, USE src, USE toc); |
|
6181 |
ins_cost(MEMORY_REF_COST); |
|
6182 |
||
6183 |
ins_num_consts(1); |
|
6184 |
||
6185 |
format %{ "ADDIS $toc, $toc, offset_hi\n\t"
|
|
6186 |
"LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" |
|
6187 |
"ADDIS $toc, $toc, -offset_hi"%} |
|
6188 |
size(12); |
|
6189 |
ins_encode %{
|
|
6190 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6191 |
FloatRegister Rdst = $dst$$FloatRegister; |
|
6192 |
Register Rtoc = $toc$$Register; |
|
6193 |
address float_address = __ float_constant($src$$constant); |
|
6194 |
int offset = __ offset_to_method_toc(float_address); |
|
6195 |
int hi = (offset + (1<<15))>>16; |
|
6196 |
int lo = offset - hi * (1<<16); |
|
6197 |
||
6198 |
__ addis(Rtoc, Rtoc, hi); |
|
6199 |
__ lfs(Rdst, lo, Rtoc); |
|
6200 |
__ addis(Rtoc, Rtoc, -hi); |
|
6201 |
%} |
|
6202 |
ins_pipe(pipe_class_memory); |
|
6203 |
%} |
|
6204 |
||
6205 |
// Adlc adds toc node MachConstantTableBase. |
|
6206 |
instruct loadConF_Ex(regF dst, immF src) %{
|
|
6207 |
match(Set dst src); |
|
6208 |
ins_cost(MEMORY_REF_COST); |
|
6209 |
||
6210 |
// See loadConP. |
|
6211 |
ins_cannot_rematerialize(true); |
|
6212 |
||
6213 |
format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
|
|
6214 |
postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); |
|
6215 |
%} |
|
6216 |
||
6217 |
// Expand node for constant pool load: small offset. |
|
6218 |
instruct loadConD(regD dst, immD src, iRegLdst toc) %{
|
|
6219 |
effect(DEF dst, USE src, USE toc); |
|
6220 |
ins_cost(MEMORY_REF_COST); |
|
6221 |
||
6222 |
ins_num_consts(1); |
|
6223 |
||
6224 |
format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
|
|
6225 |
size(4); |
|
6226 |
ins_encode %{
|
|
6227 |
// TODO: PPC port $archOpcode(ppc64Opcode_lfd); |
|
6228 |
int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); |
|
6229 |
__ lfd($dst$$FloatRegister, offset, $toc$$Register); |
|
6230 |
%} |
|
6231 |
ins_pipe(pipe_class_memory); |
|
6232 |
%} |
|
6233 |
||
6234 |
// Expand node for constant pool load: large offset. |
|
6235 |
instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
|
|
6236 |
effect(DEF dst, USE src, USE toc); |
|
6237 |
ins_cost(MEMORY_REF_COST); |
|
6238 |
||
6239 |
ins_num_consts(1); |
|
6240 |
||
6241 |
format %{ "ADDIS $toc, $toc, offset_hi\n\t"
|
|
6242 |
"LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" |
|
6243 |
"ADDIS $toc, $toc, -offset_hi" %} |
|
6244 |
size(12); |
|
6245 |
ins_encode %{
|
|
6246 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6247 |
FloatRegister Rdst = $dst$$FloatRegister; |
|
6248 |
Register Rtoc = $toc$$Register; |
|
6249 |
address float_address = __ double_constant($src$$constant); |
|
6250 |
int offset = __ offset_to_method_toc(float_address); |
|
6251 |
int hi = (offset + (1<<15))>>16; |
|
6252 |
int lo = offset - hi * (1<<16); |
|
6253 |
||
6254 |
__ addis(Rtoc, Rtoc, hi); |
|
6255 |
__ lfd(Rdst, lo, Rtoc); |
|
6256 |
__ addis(Rtoc, Rtoc, -hi); |
|
6257 |
%} |
|
6258 |
ins_pipe(pipe_class_memory); |
|
6259 |
%} |
|
6260 |
||
6261 |
// Adlc adds toc node MachConstantTableBase. |
|
6262 |
instruct loadConD_Ex(regD dst, immD src) %{
|
|
6263 |
match(Set dst src); |
|
6264 |
ins_cost(MEMORY_REF_COST); |
|
6265 |
||
6266 |
// See loadConP. |
|
6267 |
ins_cannot_rematerialize(true); |
|
6268 |
||
6269 |
format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
|
|
6270 |
postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); |
|
6271 |
%} |
|
6272 |
||
6273 |
// Prefetch instructions. |
|
6274 |
// Must be safe to execute with invalid address (cannot fault). |
|
6275 |
||
6276 |
instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
|
|
6277 |
match(PrefetchRead (AddP mem src)); |
|
6278 |
ins_cost(MEMORY_REF_COST); |
|
6279 |
||
6280 |
format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
|
|
6281 |
size(4); |
|
6282 |
ins_encode %{
|
|
6283 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbt); |
|
6284 |
__ dcbt($src$$Register, $mem$$base$$Register); |
|
6285 |
%} |
|
6286 |
ins_pipe(pipe_class_memory); |
|
6287 |
%} |
|
6288 |
||
6289 |
instruct prefetchr_no_offset(indirectMemory mem) %{
|
|
6290 |
match(PrefetchRead mem); |
|
6291 |
ins_cost(MEMORY_REF_COST); |
|
6292 |
||
6293 |
format %{ "PREFETCH $mem" %}
|
|
6294 |
size(4); |
|
6295 |
ins_encode %{
|
|
6296 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbt); |
|
6297 |
__ dcbt($mem$$base$$Register); |
|
6298 |
%} |
|
6299 |
ins_pipe(pipe_class_memory); |
|
6300 |
%} |
|
6301 |
||
6302 |
instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
|
|
6303 |
match(PrefetchWrite (AddP mem src)); |
|
6304 |
ins_cost(MEMORY_REF_COST); |
|
6305 |
||
6306 |
format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
|
|
6307 |
size(4); |
|
6308 |
ins_encode %{
|
|
6309 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6310 |
__ dcbtst($src$$Register, $mem$$base$$Register); |
|
6311 |
%} |
|
6312 |
ins_pipe(pipe_class_memory); |
|
6313 |
%} |
|
6314 |
||
6315 |
instruct prefetchw_no_offset(indirectMemory mem) %{
|
|
6316 |
match(PrefetchWrite mem); |
|
6317 |
ins_cost(MEMORY_REF_COST); |
|
6318 |
||
6319 |
format %{ "PREFETCH $mem" %}
|
|
6320 |
size(4); |
|
6321 |
ins_encode %{
|
|
6322 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6323 |
__ dcbtst($mem$$base$$Register); |
|
6324 |
%} |
|
6325 |
ins_pipe(pipe_class_memory); |
|
6326 |
%} |
|
6327 |
||
6328 |
// Special prefetch versions which use the dcbz instruction. |
|
6329 |
instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
|
|
6330 |
match(PrefetchAllocation (AddP mem src)); |
|
6331 |
predicate(AllocatePrefetchStyle == 3); |
|
6332 |
ins_cost(MEMORY_REF_COST); |
|
6333 |
||
6334 |
format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
|
|
6335 |
size(4); |
|
6336 |
ins_encode %{
|
|
6337 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6338 |
__ dcbz($src$$Register, $mem$$base$$Register); |
|
6339 |
%} |
|
6340 |
ins_pipe(pipe_class_memory); |
|
6341 |
%} |
|
6342 |
||
6343 |
instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
|
|
6344 |
match(PrefetchAllocation mem); |
|
6345 |
predicate(AllocatePrefetchStyle == 3); |
|
6346 |
ins_cost(MEMORY_REF_COST); |
|
6347 |
||
6348 |
format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
|
|
6349 |
size(4); |
|
6350 |
ins_encode %{
|
|
6351 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6352 |
__ dcbz($mem$$base$$Register); |
|
6353 |
%} |
|
6354 |
ins_pipe(pipe_class_memory); |
|
6355 |
%} |
|
6356 |
||
6357 |
instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
|
|
6358 |
match(PrefetchAllocation (AddP mem src)); |
|
6359 |
predicate(AllocatePrefetchStyle != 3); |
|
6360 |
ins_cost(MEMORY_REF_COST); |
|
6361 |
||
6362 |
format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
|
|
6363 |
size(4); |
|
6364 |
ins_encode %{
|
|
6365 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6366 |
__ dcbtst($src$$Register, $mem$$base$$Register); |
|
6367 |
%} |
|
6368 |
ins_pipe(pipe_class_memory); |
|
6369 |
%} |
|
6370 |
||
6371 |
instruct prefetch_alloc_no_offset(indirectMemory mem) %{
|
|
6372 |
match(PrefetchAllocation mem); |
|
6373 |
predicate(AllocatePrefetchStyle != 3); |
|
6374 |
ins_cost(MEMORY_REF_COST); |
|
6375 |
||
6376 |
format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
|
|
6377 |
size(4); |
|
6378 |
ins_encode %{
|
|
6379 |
// TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6380 |
__ dcbtst($mem$$base$$Register); |
|
6381 |
%} |
|
6382 |
ins_pipe(pipe_class_memory); |
|
6383 |
%} |
|
6384 |
||
6385 |
//----------Store Instructions------------------------------------------------- |
|
6386 |
||
6387 |
// Store Byte |
|
6388 |
instruct storeB(memory mem, iRegIsrc src) %{
|
|
6389 |
match(Set mem (StoreB mem src)); |
|
6390 |
ins_cost(MEMORY_REF_COST); |
|
6391 |
||
6392 |
format %{ "STB $src, $mem \t// byte" %}
|
|
6393 |
size(4); |
|
6394 |
ins_encode %{
|
|
6395 |
// TODO: PPC port $archOpcode(ppc64Opcode_stb); |
|
6396 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
6397 |
__ stb($src$$Register, Idisp, $mem$$base$$Register); |
|
6398 |
%} |
|
6399 |
ins_pipe(pipe_class_memory); |
|
6400 |
%} |
|
6401 |
||
6402 |
// Store Char/Short |
|
6403 |
instruct storeC(memory mem, iRegIsrc src) %{
|
|
6404 |
match(Set mem (StoreC mem src)); |
|
6405 |
ins_cost(MEMORY_REF_COST); |
|
6406 |
||
6407 |
format %{ "STH $src, $mem \t// short" %}
|
|
6408 |
size(4); |
|
6409 |
ins_encode %{
|
|
6410 |
// TODO: PPC port $archOpcode(ppc64Opcode_sth); |
|
6411 |
int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
6412 |
__ sth($src$$Register, Idisp, $mem$$base$$Register); |
|
6413 |
%} |
|
6414 |
ins_pipe(pipe_class_memory); |
|
6415 |
%} |
|
6416 |
||
6417 |
// Store Integer |
|
6418 |
instruct storeI(memory mem, iRegIsrc src) %{
|
|
6419 |
match(Set mem (StoreI mem src)); |
|
6420 |
ins_cost(MEMORY_REF_COST); |
|
6421 |
||
6422 |
format %{ "STW $src, $mem" %}
|
|
6423 |
size(4); |
|
6424 |
ins_encode( enc_stw(src, mem) ); |
|
6425 |
ins_pipe(pipe_class_memory); |
|
6426 |
%} |
|
6427 |
||
6428 |
// ConvL2I + StoreI. |
|
6429 |
instruct storeI_convL2I(memory mem, iRegLsrc src) %{
|
|
6430 |
match(Set mem (StoreI mem (ConvL2I src))); |
|
6431 |
ins_cost(MEMORY_REF_COST); |
|
6432 |
||
6433 |
format %{ "STW l2i($src), $mem" %}
|
|
6434 |
size(4); |
|
6435 |
ins_encode( enc_stw(src, mem) ); |
|
6436 |
ins_pipe(pipe_class_memory); |
|
6437 |
%} |
|
6438 |
||
6439 |
// Store Long |
|
6440 |
instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
|
|
6441 |
match(Set mem (StoreL mem src)); |
|
6442 |
ins_cost(MEMORY_REF_COST); |
|
6443 |
||
6444 |
format %{ "STD $src, $mem \t// long" %}
|
|
6445 |
size(4); |
|
6446 |
ins_encode( enc_std(src, mem) ); |
|
6447 |
ins_pipe(pipe_class_memory); |
|
6448 |
%} |
|
6449 |
||
6450 |
// Store super word nodes. |
|
6451 |
||
6452 |
// Store Aligned Packed Byte long register to memory |
|
6453 |
instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
|
|
6454 |
predicate(n->as_StoreVector()->memory_size() == 8); |
|
6455 |
match(Set mem (StoreVector mem src)); |
|
6456 |
ins_cost(MEMORY_REF_COST); |
|
6457 |
||
6458 |
format %{ "STD $mem, $src \t// packed8B" %}
|
|
6459 |
size(4); |
|
6460 |
ins_encode( enc_std(src, mem) ); |
|
6461 |
ins_pipe(pipe_class_memory); |
|
6462 |
%} |
|
6463 |
||
6464 |
// Store Compressed Oop |
|
6465 |
instruct storeN(memory dst, iRegN_P2N src) %{
|
|
6466 |
match(Set dst (StoreN dst src)); |
|
6467 |
ins_cost(MEMORY_REF_COST); |
|
6468 |
||
6469 |
format %{ "STW $src, $dst \t// compressed oop" %}
|
|
6470 |
size(4); |
|
6471 |
ins_encode( enc_stw(src, dst) ); |
|
6472 |
ins_pipe(pipe_class_memory); |
|
6473 |
%} |
|
6474 |
||
6475 |
// Store Compressed KLass |
|
6476 |
instruct storeNKlass(memory dst, iRegN_P2N src) %{
|
|
6477 |
match(Set dst (StoreNKlass dst src)); |
|
6478 |
ins_cost(MEMORY_REF_COST); |
|
6479 |
||
6480 |
format %{ "STW $src, $dst \t// compressed klass" %}
|
|
6481 |
size(4); |
|
6482 |
ins_encode( enc_stw(src, dst) ); |
|
6483 |
ins_pipe(pipe_class_memory); |
|
6484 |
%} |
|
6485 |
||
6486 |
// Store Pointer |
|
6487 |
instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
|
|
6488 |
match(Set dst (StoreP dst src)); |
|
6489 |
ins_cost(MEMORY_REF_COST); |
|
6490 |
||
6491 |
format %{ "STD $src, $dst \t// ptr" %}
|
|
6492 |
size(4); |
|
6493 |
ins_encode( enc_std(src, dst) ); |
|
6494 |
ins_pipe(pipe_class_memory); |
|
6495 |
%} |
|
6496 |
||
6497 |
// Store Float |
|
6498 |
instruct storeF(memory mem, regF src) %{
|
|
6499 |
match(Set mem (StoreF mem src)); |
|
6500 |
ins_cost(MEMORY_REF_COST); |
|
6501 |
||
6502 |
format %{ "STFS $src, $mem" %}
|
|
6503 |
size(4); |
|
6504 |
ins_encode( enc_stfs(src, mem) ); |
|
6505 |
ins_pipe(pipe_class_memory); |
|
6506 |
%} |
|
6507 |
||
6508 |
// Store Double |
|
6509 |
instruct storeD(memory mem, regD src) %{
|
|
6510 |
match(Set mem (StoreD mem src)); |
|
6511 |
ins_cost(MEMORY_REF_COST); |
|
6512 |
||
6513 |
format %{ "STFD $src, $mem" %}
|
|
6514 |
size(4); |
|
6515 |
ins_encode( enc_stfd(src, mem) ); |
|
6516 |
ins_pipe(pipe_class_memory); |
|
6517 |
%} |
|
6518 |
||
6519 |
//----------Store Instructions With Zeros-------------------------------------- |
|
6520 |
||
6521 |
// Card-mark for CMS garbage collection. |
|
6522 |
// This cardmark does an optimization so that it must not always |
|
6523 |
// do a releasing store. For this, it gets the address of |
|
6524 |
// CMSCollectorCardTableModRefBSExt::_requires_release as input. |
|
6525 |
// (Using releaseFieldAddr in the match rule is a hack.) |
|
6526 |
instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
|
|
6527 |
match(Set mem (StoreCM mem releaseFieldAddr)); |
|
6528 |
predicate(false); |
|
6529 |
ins_cost(MEMORY_REF_COST); |
|
6530 |
||
6531 |
// See loadConP. |
|
6532 |
ins_cannot_rematerialize(true); |
|
6533 |
||
6534 |
format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
|
|
6535 |
ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); |
|
6536 |
ins_pipe(pipe_class_memory); |
|
6537 |
%} |
|
6538 |
||
6539 |
// Card-mark for CMS garbage collection. |
|
6540 |
// This cardmark does an optimization so that it must not always |
|
6541 |
// do a releasing store. For this, it needs the constant address of |
|
6542 |
// CMSCollectorCardTableModRefBSExt::_requires_release. |
|
6543 |
// This constant address is split off here by expand so we can use |
|
6544 |
// adlc / matcher functionality to load it from the constant section. |
|
6545 |
instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
|
|
6546 |
match(Set mem (StoreCM mem zero)); |
|
6547 |
predicate(UseConcMarkSweepGC); |
|
6548 |
||
6549 |
expand %{
|
|
6550 |
immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
|
|
6551 |
iRegLdst releaseFieldAddress; |
|
6552 |
loadConL_Ex(releaseFieldAddress, baseImm); |
|
6553 |
storeCM_CMS(mem, releaseFieldAddress); |
|
6554 |
%} |
|
6555 |
%} |
|
6556 |
||
6557 |
instruct storeCM_G1(memory mem, immI_0 zero) %{
|
|
6558 |
match(Set mem (StoreCM mem zero)); |
|
6559 |
predicate(UseG1GC); |
|
6560 |
ins_cost(MEMORY_REF_COST); |
|
6561 |
||
6562 |
ins_cannot_rematerialize(true); |
|
6563 |
||
6564 |
format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
|
|
6565 |
size(8); |
|
6566 |
ins_encode %{
|
|
6567 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6568 |
__ li(R0, 0); |
|
6569 |
//__ release(); // G1: oops are allowed to get visible after dirty marking |
|
6570 |
guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); |
|
6571 |
__ stb(R0, $mem$$disp, $mem$$base$$Register); |
|
6572 |
%} |
|
6573 |
ins_pipe(pipe_class_memory); |
|
6574 |
%} |
|
6575 |
||
6576 |
// Convert oop pointer into compressed form. |
|
6577 |
||
6578 |
// Nodes for postalloc expand. |
|
6579 |
||
6580 |
// Shift node for expand. |
|
6581 |
instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
|
|
6582 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6583 |
match(Set dst (EncodeP src)); |
|
6584 |
predicate(false); |
|
6585 |
||
6586 |
format %{ "SRDI $dst, $src, 3 \t// encode" %}
|
|
6587 |
size(4); |
|
6588 |
ins_encode %{
|
|
6589 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6590 |
__ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); |
|
6591 |
%} |
|
6592 |
ins_pipe(pipe_class_default); |
|
6593 |
%} |
|
6594 |
||
6595 |
// Add node for expand. |
|
6596 |
instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
|
|
6597 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6598 |
match(Set dst (EncodeP src)); |
|
6599 |
predicate(false); |
|
6600 |
||
6601 |
format %{ "SUB $dst, $src, oop_base \t// encode" %}
|
|
6602 |
size(4); |
|
6603 |
ins_encode %{
|
|
6604 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
6605 |
__ subf($dst$$Register, R30, $src$$Register); |
|
6606 |
%} |
|
6607 |
ins_pipe(pipe_class_default); |
|
6608 |
%} |
|
6609 |
||
6610 |
// Conditional sub base. |
|
6611 |
instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
|
|
6612 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6613 |
match(Set dst (EncodeP (Binary crx src1))); |
|
6614 |
predicate(false); |
|
6615 |
||
6616 |
ins_variable_size_depending_on_alignment(true); |
|
6617 |
||
6618 |
format %{ "BEQ $crx, done\n\t"
|
|
6619 |
"SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" |
|
6620 |
"done:" %} |
|
6621 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
6622 |
ins_encode %{
|
|
6623 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
6624 |
Label done; |
|
6625 |
__ beq($crx$$CondRegister, done); |
|
6626 |
__ subf($dst$$Register, R30, $src1$$Register); |
|
6627 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
6628 |
__ bind(done); |
|
6629 |
%} |
|
6630 |
ins_pipe(pipe_class_default); |
|
6631 |
%} |
|
6632 |
||
6633 |
// Power 7 can use isel instruction |
|
6634 |
instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
|
|
6635 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6636 |
match(Set dst (EncodeP (Binary crx src1))); |
|
6637 |
predicate(false); |
|
6638 |
||
6639 |
format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
|
|
6640 |
size(4); |
|
6641 |
ins_encode %{
|
|
6642 |
// This is a Power7 instruction for which no machine description exists. |
|
6643 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6644 |
__ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); |
|
6645 |
%} |
|
6646 |
ins_pipe(pipe_class_default); |
|
6647 |
%} |
|
6648 |
||
6649 |
// base != 0 |
|
6650 |
// 32G aligned narrow oop base. |
|
6651 |
instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
|
|
6652 |
match(Set dst (EncodeP src)); |
|
6653 |
predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/); |
|
6654 |
||
6655 |
format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
|
|
6656 |
size(4); |
|
6657 |
ins_encode %{
|
|
6658 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6659 |
__ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); |
|
6660 |
%} |
|
6661 |
ins_pipe(pipe_class_default); |
|
6662 |
%} |
|
6663 |
||
6664 |
// shift != 0, base != 0 |
|
6665 |
instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
|
|
6666 |
match(Set dst (EncodeP src)); |
|
6667 |
effect(TEMP crx); |
|
6668 |
predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && |
|
6669 |
Universe::narrow_oop_shift() != 0 && |
|
6670 |
true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); |
|
6671 |
||
6672 |
format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
|
|
6673 |
postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); |
|
6674 |
%} |
|
6675 |
||
6676 |
// shift != 0, base != 0 |
|
6677 |
instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
|
|
6678 |
match(Set dst (EncodeP src)); |
|
6679 |
predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && |
|
6680 |
Universe::narrow_oop_shift() != 0 && |
|
6681 |
true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); |
|
6682 |
||
6683 |
format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
|
|
6684 |
postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); |
|
6685 |
%} |
|
6686 |
||
6687 |
// shift != 0, base == 0 |
|
6688 |
// TODO: This is the same as encodeP_shift. Merge! |
|
6689 |
instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
|
|
6690 |
match(Set dst (EncodeP src)); |
|
6691 |
predicate(Universe::narrow_oop_shift() != 0 && |
|
6692 |
Universe::narrow_oop_base() ==0); |
|
6693 |
||
6694 |
format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
|
|
6695 |
size(4); |
|
6696 |
ins_encode %{
|
|
6697 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6698 |
__ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); |
|
6699 |
%} |
|
6700 |
ins_pipe(pipe_class_default); |
|
6701 |
%} |
|
6702 |
||
6703 |
// Compressed OOPs with narrow_oop_shift == 0. |
|
6704 |
// shift == 0, base == 0 |
|
6705 |
instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
|
|
6706 |
match(Set dst (EncodeP src)); |
|
6707 |
predicate(Universe::narrow_oop_shift() == 0); |
|
6708 |
||
6709 |
format %{ "MR $dst, $src \t// Ptr->Narrow" %}
|
|
6710 |
// variable size, 0 or 4. |
|
6711 |
ins_encode %{
|
|
6712 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6713 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
6714 |
%} |
|
6715 |
ins_pipe(pipe_class_default); |
|
6716 |
%} |
|
6717 |
||
6718 |
// Decode nodes. |
|
6719 |
||
6720 |
// Shift node for expand. |
|
6721 |
instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
|
|
6722 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6723 |
match(Set dst (DecodeN src)); |
|
6724 |
predicate(false); |
|
6725 |
||
6726 |
format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
|
|
6727 |
size(4); |
|
6728 |
ins_encode %{
|
|
6729 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6730 |
__ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); |
|
6731 |
%} |
|
6732 |
ins_pipe(pipe_class_default); |
|
6733 |
%} |
|
6734 |
||
6735 |
// Add node for expand. |
|
6736 |
instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
|
|
6737 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6738 |
match(Set dst (DecodeN src)); |
|
6739 |
predicate(false); |
|
6740 |
||
6741 |
format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
|
|
6742 |
size(4); |
|
6743 |
ins_encode %{
|
|
6744 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
6745 |
__ add($dst$$Register, $src$$Register, R30); |
|
6746 |
%} |
|
6747 |
ins_pipe(pipe_class_default); |
|
6748 |
%} |
|
6749 |
||
6750 |
// conditianal add base for expand |
|
6751 |
instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
|
|
6752 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6753 |
// NOTICE that the rule is nonsense - we just have to make sure that: |
|
6754 |
// - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) |
|
6755 |
// - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. |
|
6756 |
match(Set dst (DecodeN (Binary crx src1))); |
|
6757 |
predicate(false); |
|
6758 |
||
6759 |
ins_variable_size_depending_on_alignment(true); |
|
6760 |
||
6761 |
format %{ "BEQ $crx, done\n\t"
|
|
6762 |
"ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" |
|
6763 |
"done:" %} |
|
6764 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); |
|
6765 |
ins_encode %{
|
|
6766 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
6767 |
Label done; |
|
6768 |
__ beq($crx$$CondRegister, done); |
|
6769 |
__ add($dst$$Register, $src1$$Register, R30); |
|
|
22865
3b8857d7b3cc
8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents:
22861
diff
changeset
|
6770 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
| 22861 | 6771 |
__ bind(done); |
6772 |
%} |
|
6773 |
ins_pipe(pipe_class_default); |
|
6774 |
%} |
|
6775 |
||
6776 |
instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
|
|
6777 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6778 |
// NOTICE that the rule is nonsense - we just have to make sure that: |
|
6779 |
// - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) |
|
6780 |
// - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. |
|
6781 |
match(Set dst (DecodeN (Binary crx src1))); |
|
6782 |
predicate(false); |
|
6783 |
||
6784 |
format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
|
|
6785 |
size(4); |
|
6786 |
ins_encode %{
|
|
6787 |
// This is a Power7 instruction for which no machine description exists. |
|
6788 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6789 |
__ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); |
|
6790 |
%} |
|
6791 |
ins_pipe(pipe_class_default); |
|
6792 |
%} |
|
6793 |
||
6794 |
// shift != 0, base != 0 |
|
6795 |
instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
|
|
6796 |
match(Set dst (DecodeN src)); |
|
6797 |
predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
6798 |
n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && |
|
6799 |
Universe::narrow_oop_shift() != 0 && |
|
6800 |
Universe::narrow_oop_base() != 0); |
|
6801 |
effect(TEMP crx); |
|
6802 |
||
6803 |
format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
|
|
6804 |
postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); |
|
6805 |
%} |
|
6806 |
||
6807 |
// shift != 0, base == 0 |
|
6808 |
instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
|
|
6809 |
match(Set dst (DecodeN src)); |
|
6810 |
predicate(Universe::narrow_oop_shift() != 0 && |
|
6811 |
Universe::narrow_oop_base() == 0); |
|
6812 |
||
6813 |
format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
|
|
6814 |
size(4); |
|
6815 |
ins_encode %{
|
|
6816 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6817 |
__ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); |
|
6818 |
%} |
|
6819 |
ins_pipe(pipe_class_default); |
|
6820 |
%} |
|
6821 |
||
6822 |
// src != 0, shift != 0, base != 0 |
|
6823 |
instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
|
|
6824 |
match(Set dst (DecodeN src)); |
|
6825 |
predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
6826 |
n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && |
|
6827 |
Universe::narrow_oop_shift() != 0 && |
|
6828 |
Universe::narrow_oop_base() != 0); |
|
6829 |
||
6830 |
format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
|
|
6831 |
postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); |
|
6832 |
%} |
|
6833 |
||
6834 |
// Compressed OOPs with narrow_oop_shift == 0. |
|
6835 |
instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
|
|
6836 |
match(Set dst (DecodeN src)); |
|
6837 |
predicate(Universe::narrow_oop_shift() == 0); |
|
6838 |
ins_cost(DEFAULT_COST); |
|
6839 |
||
6840 |
format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
|
|
6841 |
// variable size, 0 or 4. |
|
6842 |
ins_encode %{
|
|
6843 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6844 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
6845 |
%} |
|
6846 |
ins_pipe(pipe_class_default); |
|
6847 |
%} |
|
6848 |
||
6849 |
// Convert compressed oop into int for vectors alignment masking. |
|
6850 |
instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
|
|
6851 |
match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
6852 |
predicate(Universe::narrow_oop_shift() == 0); |
|
6853 |
ins_cost(DEFAULT_COST); |
|
6854 |
||
6855 |
format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
|
|
6856 |
// variable size, 0 or 4. |
|
6857 |
ins_encode %{
|
|
6858 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6859 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
6860 |
%} |
|
6861 |
ins_pipe(pipe_class_default); |
|
6862 |
%} |
|
6863 |
||
6864 |
// Convert klass pointer into compressed form. |
|
6865 |
||
6866 |
// Nodes for postalloc expand. |
|
6867 |
||
6868 |
// Shift node for expand. |
|
6869 |
instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
|
|
6870 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6871 |
match(Set dst (EncodePKlass src)); |
|
6872 |
predicate(false); |
|
6873 |
||
6874 |
format %{ "SRDI $dst, $src, 3 \t// encode" %}
|
|
6875 |
size(4); |
|
6876 |
ins_encode %{
|
|
6877 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6878 |
__ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); |
|
6879 |
%} |
|
6880 |
ins_pipe(pipe_class_default); |
|
6881 |
%} |
|
6882 |
||
6883 |
// Add node for expand. |
|
6884 |
instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
|
|
6885 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6886 |
match(Set dst (EncodePKlass (Binary base src))); |
|
6887 |
predicate(false); |
|
6888 |
||
6889 |
format %{ "SUB $dst, $base, $src \t// encode" %}
|
|
6890 |
size(4); |
|
6891 |
ins_encode %{
|
|
6892 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
6893 |
__ subf($dst$$Register, $base$$Register, $src$$Register); |
|
6894 |
%} |
|
6895 |
ins_pipe(pipe_class_default); |
|
6896 |
%} |
|
6897 |
||
6898 |
// base != 0 |
|
6899 |
// 32G aligned narrow oop base. |
|
6900 |
instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
|
|
6901 |
match(Set dst (EncodePKlass src)); |
|
6902 |
predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); |
|
6903 |
||
6904 |
format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
|
|
6905 |
size(4); |
|
6906 |
ins_encode %{
|
|
6907 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6908 |
__ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); |
|
6909 |
%} |
|
6910 |
ins_pipe(pipe_class_default); |
|
6911 |
%} |
|
6912 |
||
6913 |
// shift != 0, base != 0 |
|
6914 |
instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
|
|
6915 |
match(Set dst (EncodePKlass (Binary base src))); |
|
6916 |
predicate(false); |
|
6917 |
||
6918 |
format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
|
|
6919 |
postalloc_expand %{
|
|
6920 |
encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode(); |
|
6921 |
n1->add_req(n_region, n_base, n_src); |
|
6922 |
n1->_opnds[0] = op_dst; |
|
6923 |
n1->_opnds[1] = op_base; |
|
6924 |
n1->_opnds[2] = op_src; |
|
6925 |
n1->_bottom_type = _bottom_type; |
|
6926 |
||
6927 |
encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode(); |
|
6928 |
n2->add_req(n_region, n1); |
|
6929 |
n2->_opnds[0] = op_dst; |
|
6930 |
n2->_opnds[1] = op_dst; |
|
6931 |
n2->_bottom_type = _bottom_type; |
|
6932 |
ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6933 |
ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6934 |
||
6935 |
nodes->push(n1); |
|
6936 |
nodes->push(n2); |
|
6937 |
%} |
|
6938 |
%} |
|
6939 |
||
6940 |
// shift != 0, base != 0 |
|
6941 |
instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
|
|
6942 |
match(Set dst (EncodePKlass src)); |
|
6943 |
//predicate(Universe::narrow_klass_shift() != 0 && |
|
6944 |
// true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); |
|
6945 |
||
6946 |
//format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
|
|
6947 |
ins_cost(DEFAULT_COST*2); // Don't count constant. |
|
6948 |
expand %{
|
|
6949 |
immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
|
|
6950 |
iRegLdst base; |
|
6951 |
loadConL_Ex(base, baseImm); |
|
6952 |
encodePKlass_not_null_Ex(dst, base, src); |
|
6953 |
%} |
|
6954 |
%} |
|
6955 |
||
6956 |
// Decode nodes. |
|
6957 |
||
6958 |
// Shift node for expand. |
|
6959 |
instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
|
|
6960 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6961 |
match(Set dst (DecodeNKlass src)); |
|
6962 |
predicate(false); |
|
6963 |
||
6964 |
format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
|
|
6965 |
size(4); |
|
6966 |
ins_encode %{
|
|
6967 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6968 |
__ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); |
|
6969 |
%} |
|
6970 |
ins_pipe(pipe_class_default); |
|
6971 |
%} |
|
6972 |
||
6973 |
// Add node for expand. |
|
6974 |
||
6975 |
instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
|
|
6976 |
// The match rule is needed to make it a 'MachTypeNode'! |
|
6977 |
match(Set dst (DecodeNKlass (Binary base src))); |
|
6978 |
predicate(false); |
|
6979 |
||
6980 |
format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
|
|
6981 |
size(4); |
|
6982 |
ins_encode %{
|
|
6983 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
6984 |
__ add($dst$$Register, $base$$Register, $src$$Register); |
|
6985 |
%} |
|
6986 |
ins_pipe(pipe_class_default); |
|
6987 |
%} |
|
6988 |
||
6989 |
// src != 0, shift != 0, base != 0 |
|
6990 |
instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
|
|
6991 |
match(Set dst (DecodeNKlass (Binary base src))); |
|
6992 |
//effect(kill src); // We need a register for the immediate result after shifting. |
|
6993 |
predicate(false); |
|
6994 |
||
6995 |
format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
|
|
6996 |
postalloc_expand %{
|
|
6997 |
decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode(); |
|
6998 |
n1->add_req(n_region, n_base, n_src); |
|
6999 |
n1->_opnds[0] = op_dst; |
|
7000 |
n1->_opnds[1] = op_base; |
|
7001 |
n1->_opnds[2] = op_src; |
|
7002 |
n1->_bottom_type = _bottom_type; |
|
7003 |
||
7004 |
decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode(); |
|
7005 |
n2->add_req(n_region, n2); |
|
7006 |
n2->_opnds[0] = op_dst; |
|
7007 |
n2->_opnds[1] = op_dst; |
|
7008 |
n2->_bottom_type = _bottom_type; |
|
7009 |
||
7010 |
ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
7011 |
ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
7012 |
||
7013 |
nodes->push(n1); |
|
7014 |
nodes->push(n2); |
|
7015 |
%} |
|
7016 |
%} |
|
7017 |
||
7018 |
// src != 0, shift != 0, base != 0 |
|
7019 |
instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
|
|
7020 |
match(Set dst (DecodeNKlass src)); |
|
7021 |
// predicate(Universe::narrow_klass_shift() != 0 && |
|
7022 |
// Universe::narrow_klass_base() != 0); |
|
7023 |
||
7024 |
//format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
|
|
7025 |
||
7026 |
ins_cost(DEFAULT_COST*2); // Don't count constant. |
|
7027 |
expand %{
|
|
7028 |
// We add first, then we shift. Like this, we can get along with one register less. |
|
7029 |
// But we have to load the base pre-shifted. |
|
7030 |
immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
|
|
7031 |
iRegLdst base; |
|
7032 |
loadConL_Ex(base, baseImm); |
|
7033 |
decodeNKlass_notNull_addBase_Ex(dst, base, src); |
|
7034 |
%} |
|
7035 |
%} |
|
7036 |
||
7037 |
//----------MemBar Instructions----------------------------------------------- |
|
7038 |
// Memory barrier flavors |
|
7039 |
||
7040 |
instruct membar_acquire() %{
|
|
7041 |
match(LoadFence); |
|
7042 |
ins_cost(4*MEMORY_REF_COST); |
|
7043 |
||
7044 |
format %{ "MEMBAR-acquire" %}
|
|
7045 |
size(4); |
|
7046 |
ins_encode %{
|
|
7047 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7048 |
__ acquire(); |
|
7049 |
%} |
|
7050 |
ins_pipe(pipe_class_default); |
|
7051 |
%} |
|
7052 |
||
7053 |
instruct unnecessary_membar_acquire() %{
|
|
7054 |
match(MemBarAcquire); |
|
7055 |
ins_cost(0); |
|
7056 |
||
7057 |
format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
|
|
7058 |
size(0); |
|
7059 |
ins_encode( /*empty*/ ); |
|
7060 |
ins_pipe(pipe_class_default); |
|
7061 |
%} |
|
7062 |
||
7063 |
instruct membar_acquire_lock() %{
|
|
7064 |
match(MemBarAcquireLock); |
|
7065 |
ins_cost(0); |
|
7066 |
||
7067 |
format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
|
|
7068 |
size(0); |
|
7069 |
ins_encode( /*empty*/ ); |
|
7070 |
ins_pipe(pipe_class_default); |
|
7071 |
%} |
|
7072 |
||
7073 |
instruct membar_release() %{
|
|
7074 |
match(MemBarRelease); |
|
7075 |
match(StoreFence); |
|
7076 |
ins_cost(4*MEMORY_REF_COST); |
|
7077 |
||
7078 |
format %{ "MEMBAR-release" %}
|
|
7079 |
size(4); |
|
7080 |
ins_encode %{
|
|
7081 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7082 |
__ release(); |
|
7083 |
%} |
|
7084 |
ins_pipe(pipe_class_default); |
|
7085 |
%} |
|
7086 |
||
7087 |
instruct membar_storestore() %{
|
|
7088 |
match(MemBarStoreStore); |
|
7089 |
ins_cost(4*MEMORY_REF_COST); |
|
7090 |
||
7091 |
format %{ "MEMBAR-store-store" %}
|
|
7092 |
size(4); |
|
7093 |
ins_encode %{
|
|
7094 |
// TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7095 |
__ membar(Assembler::StoreStore); |
|
7096 |
%} |
|
7097 |
ins_pipe(pipe_class_default); |
|
7098 |
%} |
|
7099 |
||
7100 |
instruct membar_release_lock() %{
|
|
7101 |
match(MemBarReleaseLock); |
|
7102 |
ins_cost(0); |
|
7103 |
||
7104 |
format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
|
|
7105 |
size(0); |
|
7106 |
ins_encode( /*empty*/ ); |
|
7107 |
ins_pipe(pipe_class_default); |
|
7108 |
%} |
|
7109 |
||
7110 |
instruct membar_volatile() %{
|
|
7111 |
match(MemBarVolatile); |
|
7112 |
ins_cost(4*MEMORY_REF_COST); |
|
7113 |
||
7114 |
format %{ "MEMBAR-volatile" %}
|
|
7115 |
size(4); |
|
7116 |
ins_encode %{
|
|
7117 |
// TODO: PPC port $archOpcode(ppc64Opcode_sync); |
|
7118 |
__ fence(); |
|
7119 |
%} |
|
7120 |
ins_pipe(pipe_class_default); |
|
7121 |
%} |
|
7122 |
||
7123 |
// This optimization is wrong on PPC. The following pattern is not supported: |
|
7124 |
// MemBarVolatile |
|
7125 |
// ^ ^ |
|
7126 |
// | | |
|
7127 |
// CtrlProj MemProj |
|
7128 |
// ^ ^ |
|
7129 |
// | | |
|
7130 |
// | Load |
|
7131 |
// | |
|
7132 |
// MemBarVolatile |
|
7133 |
// |
|
7134 |
// The first MemBarVolatile could get optimized out! According to |
|
7135 |
// Vladimir, this pattern can not occur on Oracle platforms. |
|
7136 |
// However, it does occur on PPC64 (because of membars in |
|
7137 |
// inline_unsafe_load_store). |
|
7138 |
// |
|
7139 |
// Add this node again if we found a good solution for inline_unsafe_load_store(). |
|
7140 |
// Don't forget to look at the implementation of post_store_load_barrier again, |
|
7141 |
// we did other fixes in that method. |
|
7142 |
//instruct unnecessary_membar_volatile() %{
|
|
7143 |
// match(MemBarVolatile); |
|
7144 |
// predicate(Matcher::post_store_load_barrier(n)); |
|
7145 |
// ins_cost(0); |
|
7146 |
// |
|
7147 |
// format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
|
|
7148 |
// size(0); |
|
7149 |
// ins_encode( /*empty*/ ); |
|
7150 |
// ins_pipe(pipe_class_default); |
|
7151 |
//%} |
|
7152 |
||
7153 |
instruct membar_CPUOrder() %{
|
|
7154 |
match(MemBarCPUOrder); |
|
7155 |
ins_cost(0); |
|
7156 |
||
7157 |
format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
|
|
7158 |
size(0); |
|
7159 |
ins_encode( /*empty*/ ); |
|
7160 |
ins_pipe(pipe_class_default); |
|
7161 |
%} |
|
7162 |
||
7163 |
//----------Conditional Move--------------------------------------------------- |
|
7164 |
||
7165 |
// Cmove using isel. |
|
7166 |
instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
|
|
7167 |
match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7168 |
predicate(VM_Version::has_isel()); |
|
7169 |
ins_cost(DEFAULT_COST); |
|
7170 |
||
7171 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7172 |
size(4); |
|
7173 |
ins_encode %{
|
|
7174 |
// This is a Power7 instruction for which no machine description |
|
7175 |
// exists. Anyways, the scheduler should be off on Power7. |
|
7176 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7177 |
int cc = $cmp$$cmpcode; |
|
7178 |
__ isel($dst$$Register, $crx$$CondRegister, |
|
7179 |
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7180 |
%} |
|
7181 |
ins_pipe(pipe_class_default); |
|
7182 |
%} |
|
7183 |
||
7184 |
instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
|
|
7185 |
match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7186 |
predicate(!VM_Version::has_isel()); |
|
7187 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7188 |
||
7189 |
ins_variable_size_depending_on_alignment(true); |
|
7190 |
||
7191 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7192 |
// Worst case is branch + move + stop, no stop without scheduler |
|
7193 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7194 |
ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7195 |
ins_pipe(pipe_class_default); |
|
7196 |
%} |
|
7197 |
||
7198 |
instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
|
|
7199 |
match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7200 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7201 |
||
7202 |
ins_variable_size_depending_on_alignment(true); |
|
7203 |
||
7204 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7205 |
// Worst case is branch + move + stop, no stop without scheduler |
|
7206 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7207 |
ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7208 |
ins_pipe(pipe_class_default); |
|
7209 |
%} |
|
7210 |
||
7211 |
// Cmove using isel. |
|
7212 |
instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
|
|
7213 |
match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7214 |
predicate(VM_Version::has_isel()); |
|
7215 |
ins_cost(DEFAULT_COST); |
|
7216 |
||
7217 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7218 |
size(4); |
|
7219 |
ins_encode %{
|
|
7220 |
// This is a Power7 instruction for which no machine description |
|
7221 |
// exists. Anyways, the scheduler should be off on Power7. |
|
7222 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7223 |
int cc = $cmp$$cmpcode; |
|
7224 |
__ isel($dst$$Register, $crx$$CondRegister, |
|
7225 |
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7226 |
%} |
|
7227 |
ins_pipe(pipe_class_default); |
|
7228 |
%} |
|
7229 |
||
7230 |
instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
|
|
7231 |
match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7232 |
predicate(!VM_Version::has_isel()); |
|
7233 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7234 |
||
7235 |
ins_variable_size_depending_on_alignment(true); |
|
7236 |
||
7237 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7238 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7239 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7240 |
ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7241 |
ins_pipe(pipe_class_default); |
|
7242 |
%} |
|
7243 |
||
7244 |
instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
|
|
7245 |
match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7246 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7247 |
||
7248 |
ins_variable_size_depending_on_alignment(true); |
|
7249 |
||
7250 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7251 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7252 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7253 |
ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7254 |
ins_pipe(pipe_class_default); |
|
7255 |
%} |
|
7256 |
||
7257 |
// Cmove using isel. |
|
7258 |
instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
|
|
7259 |
match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7260 |
predicate(VM_Version::has_isel()); |
|
7261 |
ins_cost(DEFAULT_COST); |
|
7262 |
||
7263 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7264 |
size(4); |
|
7265 |
ins_encode %{
|
|
7266 |
// This is a Power7 instruction for which no machine description |
|
7267 |
// exists. Anyways, the scheduler should be off on Power7. |
|
7268 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7269 |
int cc = $cmp$$cmpcode; |
|
7270 |
__ isel($dst$$Register, $crx$$CondRegister, |
|
7271 |
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7272 |
%} |
|
7273 |
ins_pipe(pipe_class_default); |
|
7274 |
%} |
|
7275 |
||
7276 |
// Conditional move for RegN. Only cmov(reg, reg). |
|
7277 |
instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
|
|
7278 |
match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7279 |
predicate(!VM_Version::has_isel()); |
|
7280 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7281 |
||
7282 |
ins_variable_size_depending_on_alignment(true); |
|
7283 |
||
7284 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7285 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7286 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7287 |
ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7288 |
ins_pipe(pipe_class_default); |
|
7289 |
%} |
|
7290 |
||
7291 |
instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
|
|
7292 |
match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7293 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7294 |
||
7295 |
ins_variable_size_depending_on_alignment(true); |
|
7296 |
||
7297 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7298 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7299 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7300 |
ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7301 |
ins_pipe(pipe_class_default); |
|
7302 |
%} |
|
7303 |
||
7304 |
// Cmove using isel. |
|
7305 |
instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
|
|
7306 |
match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7307 |
predicate(VM_Version::has_isel()); |
|
7308 |
ins_cost(DEFAULT_COST); |
|
7309 |
||
7310 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7311 |
size(4); |
|
7312 |
ins_encode %{
|
|
7313 |
// This is a Power7 instruction for which no machine description |
|
7314 |
// exists. Anyways, the scheduler should be off on Power7. |
|
7315 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7316 |
int cc = $cmp$$cmpcode; |
|
7317 |
__ isel($dst$$Register, $crx$$CondRegister, |
|
7318 |
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7319 |
%} |
|
7320 |
ins_pipe(pipe_class_default); |
|
7321 |
%} |
|
7322 |
||
7323 |
instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
|
|
7324 |
match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7325 |
predicate(!VM_Version::has_isel()); |
|
7326 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7327 |
||
7328 |
ins_variable_size_depending_on_alignment(true); |
|
7329 |
||
7330 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7331 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7332 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7333 |
ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7334 |
ins_pipe(pipe_class_default); |
|
7335 |
%} |
|
7336 |
||
7337 |
instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
|
|
7338 |
match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7339 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7340 |
||
7341 |
ins_variable_size_depending_on_alignment(true); |
|
7342 |
||
7343 |
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
|
7344 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7345 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7346 |
ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7347 |
ins_pipe(pipe_class_default); |
|
7348 |
%} |
|
7349 |
||
7350 |
instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
|
|
7351 |
match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); |
|
7352 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7353 |
||
7354 |
ins_variable_size_depending_on_alignment(true); |
|
7355 |
||
7356 |
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
|
|
7357 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7358 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
7359 |
ins_encode %{
|
|
7360 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef); |
|
7361 |
Label done; |
|
7362 |
assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
7363 |
// Branch if not (cmp crx). |
|
7364 |
__ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
7365 |
__ fmr($dst$$FloatRegister, $src$$FloatRegister); |
|
7366 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
7367 |
__ bind(done); |
|
7368 |
%} |
|
7369 |
ins_pipe(pipe_class_default); |
|
7370 |
%} |
|
7371 |
||
7372 |
instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
|
|
7373 |
match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); |
|
7374 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7375 |
||
7376 |
ins_variable_size_depending_on_alignment(true); |
|
7377 |
||
7378 |
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
|
|
7379 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
7380 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
7381 |
ins_encode %{
|
|
7382 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef); |
|
7383 |
Label done; |
|
7384 |
assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
7385 |
// Branch if not (cmp crx). |
|
7386 |
__ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
7387 |
__ fmr($dst$$FloatRegister, $src$$FloatRegister); |
|
7388 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
7389 |
__ bind(done); |
|
7390 |
%} |
|
7391 |
ins_pipe(pipe_class_default); |
|
7392 |
%} |
|
7393 |
||
7394 |
//----------Conditional_store-------------------------------------------------- |
|
7395 |
// Conditional-store of the updated heap-top. |
|
7396 |
// Used during allocation of the shared heap. |
|
7397 |
// Sets flags (EQ) on success. Implemented with a CASA on Sparc. |
|
7398 |
||
7399 |
// As compareAndSwapL, but return flag register instead of boolean value in |
|
7400 |
// int register. |
|
7401 |
// Used by sun/misc/AtomicLongCSImpl.java. |
|
7402 |
// Mem_ptr must be a memory operand, else this node does not get |
|
7403 |
// Flag_needs_anti_dependence_check set by adlc. If this is not set this node |
|
7404 |
// can be rematerialized which leads to errors. |
|
7405 |
instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
|
|
7406 |
match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); |
|
7407 |
format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
|
|
7408 |
ins_encode %{
|
|
7409 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7410 |
__ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, |
|
7411 |
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7412 |
noreg, NULL, true); |
|
7413 |
%} |
|
7414 |
ins_pipe(pipe_class_default); |
|
7415 |
%} |
|
7416 |
||
7417 |
// As compareAndSwapP, but return flag register instead of boolean value in |
|
7418 |
// int register. |
|
7419 |
// This instruction is matched if UseTLAB is off. |
|
7420 |
// Mem_ptr must be a memory operand, else this node does not get |
|
7421 |
// Flag_needs_anti_dependence_check set by adlc. If this is not set this node |
|
7422 |
// can be rematerialized which leads to errors. |
|
7423 |
instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
|
|
7424 |
match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); |
|
7425 |
format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
|
|
7426 |
ins_encode %{
|
|
7427 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7428 |
__ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, |
|
7429 |
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7430 |
noreg, NULL, true); |
|
7431 |
%} |
|
7432 |
ins_pipe(pipe_class_default); |
|
7433 |
%} |
|
7434 |
||
7435 |
// Implement LoadPLocked. Must be ordered against changes of the memory location |
|
7436 |
// by storePConditional. |
|
7437 |
// Don't know whether this is ever used. |
|
7438 |
instruct loadPLocked(iRegPdst dst, memory mem) %{
|
|
7439 |
match(Set dst (LoadPLocked mem)); |
|
7440 |
ins_cost(MEMORY_REF_COST); |
|
7441 |
||
7442 |
format %{ "LD $dst, $mem \t// loadPLocked\n\t"
|
|
7443 |
"TWI $dst\n\t" |
|
7444 |
"ISYNC" %} |
|
7445 |
size(12); |
|
7446 |
ins_encode( enc_ld_ac(dst, mem) ); |
|
7447 |
ins_pipe(pipe_class_memory); |
|
7448 |
%} |
|
7449 |
||
7450 |
//----------Compare-And-Swap--------------------------------------------------- |
|
7451 |
||
7452 |
// CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
|
|
7453 |
// (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be |
|
7454 |
// matched. |
|
7455 |
||
7456 |
instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
|
|
7457 |
match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); |
|
7458 |
format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
|
|
7459 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7460 |
ins_encode %{
|
|
7461 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7462 |
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7463 |
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7464 |
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7465 |
$res$$Register, true); |
|
7466 |
%} |
|
7467 |
ins_pipe(pipe_class_default); |
|
7468 |
%} |
|
7469 |
||
7470 |
instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
|
|
7471 |
match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); |
|
7472 |
format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
|
|
7473 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7474 |
ins_encode %{
|
|
7475 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7476 |
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7477 |
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7478 |
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7479 |
$res$$Register, true); |
|
7480 |
%} |
|
7481 |
ins_pipe(pipe_class_default); |
|
7482 |
%} |
|
7483 |
||
7484 |
instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
|
|
7485 |
match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); |
|
7486 |
format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
|
|
7487 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7488 |
ins_encode %{
|
|
7489 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7490 |
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7491 |
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7492 |
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7493 |
$res$$Register, NULL, true); |
|
7494 |
%} |
|
7495 |
ins_pipe(pipe_class_default); |
|
7496 |
%} |
|
7497 |
||
7498 |
instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
|
|
7499 |
match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); |
|
7500 |
format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
|
|
7501 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7502 |
ins_encode %{
|
|
7503 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7504 |
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7505 |
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7506 |
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7507 |
$res$$Register, NULL, true); |
|
7508 |
%} |
|
7509 |
ins_pipe(pipe_class_default); |
|
7510 |
%} |
|
7511 |
||
7512 |
instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
|
|
7513 |
match(Set res (GetAndAddI mem_ptr src)); |
|
7514 |
format %{ "GetAndAddI $res, $mem_ptr, $src" %}
|
|
7515 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7516 |
ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); |
|
7517 |
ins_pipe(pipe_class_default); |
|
7518 |
%} |
|
7519 |
||
7520 |
instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
|
|
7521 |
match(Set res (GetAndAddL mem_ptr src)); |
|
7522 |
format %{ "GetAndAddL $res, $mem_ptr, $src" %}
|
|
7523 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7524 |
ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); |
|
7525 |
ins_pipe(pipe_class_default); |
|
7526 |
%} |
|
7527 |
||
7528 |
instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
|
|
7529 |
match(Set res (GetAndSetI mem_ptr src)); |
|
7530 |
format %{ "GetAndSetI $res, $mem_ptr, $src" %}
|
|
7531 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7532 |
ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); |
|
7533 |
ins_pipe(pipe_class_default); |
|
7534 |
%} |
|
7535 |
||
7536 |
instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
|
|
7537 |
match(Set res (GetAndSetL mem_ptr src)); |
|
7538 |
format %{ "GetAndSetL $res, $mem_ptr, $src" %}
|
|
7539 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7540 |
ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); |
|
7541 |
ins_pipe(pipe_class_default); |
|
7542 |
%} |
|
7543 |
||
7544 |
instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
|
|
7545 |
match(Set res (GetAndSetP mem_ptr src)); |
|
7546 |
format %{ "GetAndSetP $res, $mem_ptr, $src" %}
|
|
7547 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7548 |
ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); |
|
7549 |
ins_pipe(pipe_class_default); |
|
7550 |
%} |
|
7551 |
||
7552 |
instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
|
|
7553 |
match(Set res (GetAndSetN mem_ptr src)); |
|
7554 |
format %{ "GetAndSetN $res, $mem_ptr, $src" %}
|
|
7555 |
// Variable size: instruction count smaller if regs are disjoint. |
|
7556 |
ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); |
|
7557 |
ins_pipe(pipe_class_default); |
|
7558 |
%} |
|
7559 |
||
7560 |
//----------Arithmetic Instructions-------------------------------------------- |
|
7561 |
// Addition Instructions |
|
7562 |
||
7563 |
// Register Addition |
|
7564 |
instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
|
|
7565 |
match(Set dst (AddI src1 src2)); |
|
7566 |
format %{ "ADD $dst, $src1, $src2" %}
|
|
7567 |
size(4); |
|
7568 |
ins_encode %{
|
|
7569 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7570 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7571 |
%} |
|
7572 |
ins_pipe(pipe_class_default); |
|
7573 |
%} |
|
7574 |
||
7575 |
// Expand does not work with above instruct. (??) |
|
7576 |
instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
7577 |
// no match-rule |
|
7578 |
effect(DEF dst, USE src1, USE src2); |
|
7579 |
format %{ "ADD $dst, $src1, $src2" %}
|
|
7580 |
size(4); |
|
7581 |
ins_encode %{
|
|
7582 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7583 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7584 |
%} |
|
7585 |
ins_pipe(pipe_class_default); |
|
7586 |
%} |
|
7587 |
||
7588 |
instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
|
|
7589 |
match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); |
|
7590 |
ins_cost(DEFAULT_COST*3); |
|
7591 |
||
7592 |
expand %{
|
|
7593 |
// FIXME: we should do this in the ideal world. |
|
7594 |
iRegIdst tmp1; |
|
7595 |
iRegIdst tmp2; |
|
7596 |
addI_reg_reg(tmp1, src1, src2); |
|
7597 |
addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. |
|
7598 |
addI_reg_reg(dst, tmp1, tmp2); |
|
7599 |
%} |
|
7600 |
%} |
|
7601 |
||
7602 |
// Immediate Addition |
|
7603 |
instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
|
|
7604 |
match(Set dst (AddI src1 src2)); |
|
7605 |
format %{ "ADDI $dst, $src1, $src2" %}
|
|
7606 |
size(4); |
|
7607 |
ins_encode %{
|
|
7608 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7609 |
__ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7610 |
%} |
|
7611 |
ins_pipe(pipe_class_default); |
|
7612 |
%} |
|
7613 |
||
7614 |
// Immediate Addition with 16-bit shifted operand |
|
7615 |
instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
|
|
7616 |
match(Set dst (AddI src1 src2)); |
|
7617 |
format %{ "ADDIS $dst, $src1, $src2" %}
|
|
7618 |
size(4); |
|
7619 |
ins_encode %{
|
|
7620 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7621 |
__ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7622 |
%} |
|
7623 |
ins_pipe(pipe_class_default); |
|
7624 |
%} |
|
7625 |
||
7626 |
// Long Addition |
|
7627 |
instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7628 |
match(Set dst (AddL src1 src2)); |
|
7629 |
format %{ "ADD $dst, $src1, $src2 \t// long" %}
|
|
7630 |
size(4); |
|
7631 |
ins_encode %{
|
|
7632 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7633 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7634 |
%} |
|
7635 |
ins_pipe(pipe_class_default); |
|
7636 |
%} |
|
7637 |
||
7638 |
// Expand does not work with above instruct. (??) |
|
7639 |
instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7640 |
// no match-rule |
|
7641 |
effect(DEF dst, USE src1, USE src2); |
|
7642 |
format %{ "ADD $dst, $src1, $src2 \t// long" %}
|
|
7643 |
size(4); |
|
7644 |
ins_encode %{
|
|
7645 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7646 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7647 |
%} |
|
7648 |
ins_pipe(pipe_class_default); |
|
7649 |
%} |
|
7650 |
||
7651 |
instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
|
|
7652 |
match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); |
|
7653 |
ins_cost(DEFAULT_COST*3); |
|
7654 |
||
7655 |
expand %{
|
|
7656 |
// FIXME: we should do this in the ideal world. |
|
7657 |
iRegLdst tmp1; |
|
7658 |
iRegLdst tmp2; |
|
7659 |
addL_reg_reg(tmp1, src1, src2); |
|
7660 |
addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. |
|
7661 |
addL_reg_reg(dst, tmp1, tmp2); |
|
7662 |
%} |
|
7663 |
%} |
|
7664 |
||
7665 |
// AddL + ConvL2I. |
|
7666 |
instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7667 |
match(Set dst (ConvL2I (AddL src1 src2))); |
|
7668 |
||
7669 |
format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
|
|
7670 |
size(4); |
|
7671 |
ins_encode %{
|
|
7672 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7673 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7674 |
%} |
|
7675 |
ins_pipe(pipe_class_default); |
|
7676 |
%} |
|
7677 |
||
7678 |
// No constant pool entries required. |
|
7679 |
instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
|
|
7680 |
match(Set dst (AddL src1 src2)); |
|
7681 |
||
7682 |
format %{ "ADDI $dst, $src1, $src2" %}
|
|
7683 |
size(4); |
|
7684 |
ins_encode %{
|
|
7685 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7686 |
__ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7687 |
%} |
|
7688 |
ins_pipe(pipe_class_default); |
|
7689 |
%} |
|
7690 |
||
7691 |
// Long Immediate Addition with 16-bit shifted operand. |
|
7692 |
// No constant pool entries required. |
|
7693 |
instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
|
|
7694 |
match(Set dst (AddL src1 src2)); |
|
7695 |
||
7696 |
format %{ "ADDIS $dst, $src1, $src2" %}
|
|
7697 |
size(4); |
|
7698 |
ins_encode %{
|
|
7699 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7700 |
__ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7701 |
%} |
|
7702 |
ins_pipe(pipe_class_default); |
|
7703 |
%} |
|
7704 |
||
7705 |
// Pointer Register Addition |
|
7706 |
instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
|
|
7707 |
match(Set dst (AddP src1 src2)); |
|
7708 |
format %{ "ADD $dst, $src1, $src2" %}
|
|
7709 |
size(4); |
|
7710 |
ins_encode %{
|
|
7711 |
// TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7712 |
__ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7713 |
%} |
|
7714 |
ins_pipe(pipe_class_default); |
|
7715 |
%} |
|
7716 |
||
7717 |
// Pointer Immediate Addition |
|
7718 |
// No constant pool entries required. |
|
7719 |
instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
|
|
7720 |
match(Set dst (AddP src1 src2)); |
|
7721 |
||
7722 |
format %{ "ADDI $dst, $src1, $src2" %}
|
|
7723 |
size(4); |
|
7724 |
ins_encode %{
|
|
7725 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7726 |
__ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7727 |
%} |
|
7728 |
ins_pipe(pipe_class_default); |
|
7729 |
%} |
|
7730 |
||
7731 |
// Pointer Immediate Addition with 16-bit shifted operand. |
|
7732 |
// No constant pool entries required. |
|
7733 |
instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
|
|
7734 |
match(Set dst (AddP src1 src2)); |
|
7735 |
||
7736 |
format %{ "ADDIS $dst, $src1, $src2" %}
|
|
7737 |
size(4); |
|
7738 |
ins_encode %{
|
|
7739 |
// TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7740 |
__ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7741 |
%} |
|
7742 |
ins_pipe(pipe_class_default); |
|
7743 |
%} |
|
7744 |
||
7745 |
//--------------------- |
|
7746 |
// Subtraction Instructions |
|
7747 |
||
7748 |
// Register Subtraction |
|
7749 |
instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
7750 |
match(Set dst (SubI src1 src2)); |
|
7751 |
format %{ "SUBF $dst, $src2, $src1" %}
|
|
7752 |
size(4); |
|
7753 |
ins_encode %{
|
|
7754 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7755 |
__ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7756 |
%} |
|
7757 |
ins_pipe(pipe_class_default); |
|
7758 |
%} |
|
7759 |
||
7760 |
// Immediate Subtraction |
|
7761 |
// The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), |
|
7762 |
// so this rule seems to be unused. |
|
7763 |
instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
|
|
7764 |
match(Set dst (SubI src1 src2)); |
|
7765 |
format %{ "SUBI $dst, $src1, $src2" %}
|
|
7766 |
size(4); |
|
7767 |
ins_encode %{
|
|
7768 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7769 |
__ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); |
|
7770 |
%} |
|
7771 |
ins_pipe(pipe_class_default); |
|
7772 |
%} |
|
7773 |
||
7774 |
// SubI from constant (using subfic). |
|
7775 |
instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
|
|
7776 |
match(Set dst (SubI src1 src2)); |
|
7777 |
format %{ "SUBI $dst, $src1, $src2" %}
|
|
7778 |
||
7779 |
size(4); |
|
7780 |
ins_encode %{
|
|
7781 |
// TODO: PPC port $archOpcode(ppc64Opcode_subfic); |
|
7782 |
__ subfic($dst$$Register, $src2$$Register, $src1$$constant); |
|
7783 |
%} |
|
7784 |
ins_pipe(pipe_class_default); |
|
7785 |
%} |
|
7786 |
||
7787 |
// Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for |
|
7788 |
// positive integers and 0xF...F for negative ones. |
|
7789 |
instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
|
|
7790 |
// no match-rule, false predicate |
|
7791 |
effect(DEF dst, USE src); |
|
7792 |
predicate(false); |
|
7793 |
||
7794 |
format %{ "SRAWI $dst, $src, #31" %}
|
|
7795 |
size(4); |
|
7796 |
ins_encode %{
|
|
7797 |
// TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
7798 |
__ srawi($dst$$Register, $src$$Register, 0x1f); |
|
7799 |
%} |
|
7800 |
ins_pipe(pipe_class_default); |
|
7801 |
%} |
|
7802 |
||
7803 |
instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
|
|
7804 |
match(Set dst (AbsI src)); |
|
7805 |
ins_cost(DEFAULT_COST*3); |
|
7806 |
||
7807 |
expand %{
|
|
7808 |
iRegIdst tmp1; |
|
7809 |
iRegIdst tmp2; |
|
7810 |
signmask32I_regI(tmp1, src); |
|
7811 |
xorI_reg_reg(tmp2, tmp1, src); |
|
7812 |
subI_reg_reg(dst, tmp2, tmp1); |
|
7813 |
%} |
|
7814 |
%} |
|
7815 |
||
7816 |
instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
|
|
7817 |
match(Set dst (SubI zero src2)); |
|
7818 |
format %{ "NEG $dst, $src2" %}
|
|
7819 |
size(4); |
|
7820 |
ins_encode %{
|
|
7821 |
// TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7822 |
__ neg($dst$$Register, $src2$$Register); |
|
7823 |
%} |
|
7824 |
ins_pipe(pipe_class_default); |
|
7825 |
%} |
|
7826 |
||
7827 |
// Long subtraction |
|
7828 |
instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7829 |
match(Set dst (SubL src1 src2)); |
|
7830 |
format %{ "SUBF $dst, $src2, $src1 \t// long" %}
|
|
7831 |
size(4); |
|
7832 |
ins_encode %{
|
|
7833 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7834 |
__ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7835 |
%} |
|
7836 |
ins_pipe(pipe_class_default); |
|
7837 |
%} |
|
7838 |
||
7839 |
// SubL + convL2I. |
|
7840 |
instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7841 |
match(Set dst (ConvL2I (SubL src1 src2))); |
|
7842 |
||
7843 |
format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
|
|
7844 |
size(4); |
|
7845 |
ins_encode %{
|
|
7846 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7847 |
__ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7848 |
%} |
|
7849 |
ins_pipe(pipe_class_default); |
|
7850 |
%} |
|
7851 |
||
7852 |
// Immediate Subtraction |
|
7853 |
// The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), |
|
7854 |
// so this rule seems to be unused. |
|
7855 |
// No constant pool entries required. |
|
7856 |
instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
|
|
7857 |
match(Set dst (SubL src1 src2)); |
|
7858 |
||
7859 |
format %{ "SUBI $dst, $src1, $src2 \t// long" %}
|
|
7860 |
size(4); |
|
7861 |
ins_encode %{
|
|
7862 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7863 |
__ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); |
|
7864 |
%} |
|
7865 |
ins_pipe(pipe_class_default); |
|
7866 |
%} |
|
7867 |
||
7868 |
// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for |
|
7869 |
// positive longs and 0xF...F for negative ones. |
|
7870 |
instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
|
|
7871 |
// no match-rule, false predicate |
|
7872 |
effect(DEF dst, USE src); |
|
7873 |
predicate(false); |
|
7874 |
||
7875 |
format %{ "SRADI $dst, $src, #63" %}
|
|
7876 |
size(4); |
|
7877 |
ins_encode %{
|
|
7878 |
// TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
7879 |
__ sradi($dst$$Register, $src$$Register, 0x3f); |
|
7880 |
%} |
|
7881 |
ins_pipe(pipe_class_default); |
|
7882 |
%} |
|
7883 |
||
7884 |
// Long negation |
|
7885 |
instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
|
|
7886 |
match(Set dst (SubL zero src2)); |
|
7887 |
format %{ "NEG $dst, $src2 \t// long" %}
|
|
7888 |
size(4); |
|
7889 |
ins_encode %{
|
|
7890 |
// TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7891 |
__ neg($dst$$Register, $src2$$Register); |
|
7892 |
%} |
|
7893 |
ins_pipe(pipe_class_default); |
|
7894 |
%} |
|
7895 |
||
7896 |
// NegL + ConvL2I. |
|
7897 |
instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
|
|
7898 |
match(Set dst (ConvL2I (SubL zero src2))); |
|
7899 |
||
7900 |
format %{ "NEG $dst, $src2 \t// long + l2i" %}
|
|
7901 |
size(4); |
|
7902 |
ins_encode %{
|
|
7903 |
// TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7904 |
__ neg($dst$$Register, $src2$$Register); |
|
7905 |
%} |
|
7906 |
ins_pipe(pipe_class_default); |
|
7907 |
%} |
|
7908 |
||
7909 |
// Multiplication Instructions |
|
7910 |
// Integer Multiplication |
|
7911 |
||
7912 |
// Register Multiplication |
|
7913 |
instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
7914 |
match(Set dst (MulI src1 src2)); |
|
7915 |
ins_cost(DEFAULT_COST); |
|
7916 |
||
7917 |
format %{ "MULLW $dst, $src1, $src2" %}
|
|
7918 |
size(4); |
|
7919 |
ins_encode %{
|
|
7920 |
// TODO: PPC port $archOpcode(ppc64Opcode_mullw); |
|
7921 |
__ mullw($dst$$Register, $src1$$Register, $src2$$Register); |
|
7922 |
%} |
|
7923 |
ins_pipe(pipe_class_default); |
|
7924 |
%} |
|
7925 |
||
7926 |
// Immediate Multiplication |
|
7927 |
instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
|
|
7928 |
match(Set dst (MulI src1 src2)); |
|
7929 |
ins_cost(DEFAULT_COST); |
|
7930 |
||
7931 |
format %{ "MULLI $dst, $src1, $src2" %}
|
|
7932 |
size(4); |
|
7933 |
ins_encode %{
|
|
7934 |
// TODO: PPC port $archOpcode(ppc64Opcode_mulli); |
|
7935 |
__ mulli($dst$$Register, $src1$$Register, $src2$$constant); |
|
7936 |
%} |
|
7937 |
ins_pipe(pipe_class_default); |
|
7938 |
%} |
|
7939 |
||
7940 |
instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7941 |
match(Set dst (MulL src1 src2)); |
|
7942 |
ins_cost(DEFAULT_COST); |
|
7943 |
||
7944 |
format %{ "MULLD $dst $src1, $src2 \t// long" %}
|
|
7945 |
size(4); |
|
7946 |
ins_encode %{
|
|
7947 |
// TODO: PPC port $archOpcode(ppc64Opcode_mulld); |
|
7948 |
__ mulld($dst$$Register, $src1$$Register, $src2$$Register); |
|
7949 |
%} |
|
7950 |
ins_pipe(pipe_class_default); |
|
7951 |
%} |
|
7952 |
||
7953 |
// Multiply high for optimized long division by constant. |
|
7954 |
instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
7955 |
match(Set dst (MulHiL src1 src2)); |
|
7956 |
ins_cost(DEFAULT_COST); |
|
7957 |
||
7958 |
format %{ "MULHD $dst $src1, $src2 \t// long" %}
|
|
7959 |
size(4); |
|
7960 |
ins_encode %{
|
|
7961 |
// TODO: PPC port $archOpcode(ppc64Opcode_mulhd); |
|
7962 |
__ mulhd($dst$$Register, $src1$$Register, $src2$$Register); |
|
7963 |
%} |
|
7964 |
ins_pipe(pipe_class_default); |
|
7965 |
%} |
|
7966 |
||
7967 |
// Immediate Multiplication |
|
7968 |
instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
|
|
7969 |
match(Set dst (MulL src1 src2)); |
|
7970 |
ins_cost(DEFAULT_COST); |
|
7971 |
||
7972 |
format %{ "MULLI $dst, $src1, $src2" %}
|
|
7973 |
size(4); |
|
7974 |
ins_encode %{
|
|
7975 |
// TODO: PPC port $archOpcode(ppc64Opcode_mulli); |
|
7976 |
__ mulli($dst$$Register, $src1$$Register, $src2$$constant); |
|
7977 |
%} |
|
7978 |
ins_pipe(pipe_class_default); |
|
7979 |
%} |
|
7980 |
||
7981 |
// Integer Division with Immediate -1: Negate. |
|
7982 |
instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
|
|
7983 |
match(Set dst (DivI src1 src2)); |
|
7984 |
ins_cost(DEFAULT_COST); |
|
7985 |
||
7986 |
format %{ "NEG $dst, $src1 \t// /-1" %}
|
|
7987 |
size(4); |
|
7988 |
ins_encode %{
|
|
7989 |
// TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7990 |
__ neg($dst$$Register, $src1$$Register); |
|
7991 |
%} |
|
7992 |
ins_pipe(pipe_class_default); |
|
7993 |
%} |
|
7994 |
||
7995 |
// Integer Division with constant, but not -1. |
|
7996 |
// We should be able to improve this by checking the type of src2. |
|
7997 |
// It might well be that src2 is known to be positive. |
|
7998 |
instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
7999 |
match(Set dst (DivI src1 src2)); |
|
8000 |
predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 |
|
8001 |
ins_cost(2*DEFAULT_COST); |
|
8002 |
||
8003 |
format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
|
|
8004 |
size(4); |
|
8005 |
ins_encode %{
|
|
8006 |
// TODO: PPC port $archOpcode(ppc64Opcode_divw); |
|
8007 |
__ divw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8008 |
%} |
|
8009 |
ins_pipe(pipe_class_default); |
|
8010 |
%} |
|
8011 |
||
8012 |
instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
|
|
8013 |
effect(USE_DEF dst, USE src1, USE crx); |
|
8014 |
predicate(false); |
|
8015 |
||
8016 |
ins_variable_size_depending_on_alignment(true); |
|
8017 |
||
8018 |
format %{ "CMOVE $dst, neg($src1), $crx" %}
|
|
8019 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
8020 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
8021 |
ins_encode %{
|
|
8022 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
8023 |
Label done; |
|
8024 |
__ bne($crx$$CondRegister, done); |
|
8025 |
__ neg($dst$$Register, $src1$$Register); |
|
8026 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
8027 |
__ bind(done); |
|
8028 |
%} |
|
8029 |
ins_pipe(pipe_class_default); |
|
8030 |
%} |
|
8031 |
||
8032 |
// Integer Division with Registers not containing constants. |
|
8033 |
instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8034 |
match(Set dst (DivI src1 src2)); |
|
8035 |
ins_cost(10*DEFAULT_COST); |
|
8036 |
||
8037 |
expand %{
|
|
8038 |
immI16 imm %{ (int)-1 %}
|
|
8039 |
flagsReg tmp1; |
|
8040 |
cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8041 |
divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 |
|
8042 |
cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 |
|
8043 |
%} |
|
8044 |
%} |
|
8045 |
||
8046 |
// Long Division with Immediate -1: Negate. |
|
8047 |
instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
|
|
8048 |
match(Set dst (DivL src1 src2)); |
|
8049 |
ins_cost(DEFAULT_COST); |
|
8050 |
||
8051 |
format %{ "NEG $dst, $src1 \t// /-1, long" %}
|
|
8052 |
size(4); |
|
8053 |
ins_encode %{
|
|
8054 |
// TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
8055 |
__ neg($dst$$Register, $src1$$Register); |
|
8056 |
%} |
|
8057 |
ins_pipe(pipe_class_default); |
|
8058 |
%} |
|
8059 |
||
8060 |
// Long Division with constant, but not -1. |
|
8061 |
instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
8062 |
match(Set dst (DivL src1 src2)); |
|
8063 |
predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. |
|
8064 |
ins_cost(2*DEFAULT_COST); |
|
8065 |
||
8066 |
format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
|
|
8067 |
size(4); |
|
8068 |
ins_encode %{
|
|
8069 |
// TODO: PPC port $archOpcode(ppc64Opcode_divd); |
|
8070 |
__ divd($dst$$Register, $src1$$Register, $src2$$Register); |
|
8071 |
%} |
|
8072 |
ins_pipe(pipe_class_default); |
|
8073 |
%} |
|
8074 |
||
8075 |
instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
|
|
8076 |
effect(USE_DEF dst, USE src1, USE crx); |
|
8077 |
predicate(false); |
|
8078 |
||
8079 |
ins_variable_size_depending_on_alignment(true); |
|
8080 |
||
8081 |
format %{ "CMOVE $dst, neg($src1), $crx" %}
|
|
8082 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
8083 |
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
8084 |
ins_encode %{
|
|
8085 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
8086 |
Label done; |
|
8087 |
__ bne($crx$$CondRegister, done); |
|
8088 |
__ neg($dst$$Register, $src1$$Register); |
|
8089 |
// TODO PPC port __ endgroup_if_needed(_size == 12); |
|
8090 |
__ bind(done); |
|
8091 |
%} |
|
8092 |
ins_pipe(pipe_class_default); |
|
8093 |
%} |
|
8094 |
||
8095 |
// Long Division with Registers not containing constants. |
|
8096 |
instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
8097 |
match(Set dst (DivL src1 src2)); |
|
8098 |
ins_cost(10*DEFAULT_COST); |
|
8099 |
||
8100 |
expand %{
|
|
8101 |
immL16 imm %{ (int)-1 %}
|
|
8102 |
flagsReg tmp1; |
|
8103 |
cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8104 |
divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 |
|
8105 |
cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 |
|
8106 |
%} |
|
8107 |
%} |
|
8108 |
||
8109 |
// Integer Remainder with registers. |
|
8110 |
instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8111 |
match(Set dst (ModI src1 src2)); |
|
8112 |
ins_cost(10*DEFAULT_COST); |
|
8113 |
||
8114 |
expand %{
|
|
8115 |
immI16 imm %{ (int)-1 %}
|
|
8116 |
flagsReg tmp1; |
|
8117 |
iRegIdst tmp2; |
|
8118 |
iRegIdst tmp3; |
|
8119 |
cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8120 |
divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 |
|
8121 |
cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 |
|
8122 |
mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 |
|
8123 |
subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 |
|
8124 |
%} |
|
8125 |
%} |
|
8126 |
||
8127 |
// Long Remainder with registers |
|
8128 |
instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
|
|
8129 |
match(Set dst (ModL src1 src2)); |
|
8130 |
ins_cost(10*DEFAULT_COST); |
|
8131 |
||
8132 |
expand %{
|
|
8133 |
immL16 imm %{ (int)-1 %}
|
|
8134 |
flagsReg tmp1; |
|
8135 |
iRegLdst tmp2; |
|
8136 |
iRegLdst tmp3; |
|
8137 |
cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8138 |
divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 |
|
8139 |
cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 |
|
8140 |
mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 |
|
8141 |
subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 |
|
8142 |
%} |
|
8143 |
%} |
|
8144 |
||
8145 |
// Integer Shift Instructions |
|
8146 |
||
8147 |
// Register Shift Left |
|
8148 |
||
8149 |
// Clear all but the lowest #mask bits. |
|
8150 |
// Used to normalize shift amounts in registers. |
|
8151 |
instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
|
|
8152 |
// no match-rule, false predicate |
|
8153 |
effect(DEF dst, USE src, USE mask); |
|
8154 |
predicate(false); |
|
8155 |
||
8156 |
format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
|
|
8157 |
size(4); |
|
8158 |
ins_encode %{
|
|
8159 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8160 |
__ clrldi($dst$$Register, $src$$Register, $mask$$constant); |
|
8161 |
%} |
|
8162 |
ins_pipe(pipe_class_default); |
|
8163 |
%} |
|
8164 |
||
8165 |
instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8166 |
// no match-rule, false predicate |
|
8167 |
effect(DEF dst, USE src1, USE src2); |
|
8168 |
predicate(false); |
|
8169 |
||
8170 |
format %{ "SLW $dst, $src1, $src2" %}
|
|
8171 |
size(4); |
|
8172 |
ins_encode %{
|
|
8173 |
// TODO: PPC port $archOpcode(ppc64Opcode_slw); |
|
8174 |
__ slw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8175 |
%} |
|
8176 |
ins_pipe(pipe_class_default); |
|
8177 |
%} |
|
8178 |
||
8179 |
instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8180 |
match(Set dst (LShiftI src1 src2)); |
|
8181 |
ins_cost(DEFAULT_COST*2); |
|
8182 |
expand %{
|
|
8183 |
uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
|
|
8184 |
iRegIdst tmpI; |
|
8185 |
maskI_reg_imm(tmpI, src2, mask); |
|
8186 |
lShiftI_reg_reg(dst, src1, tmpI); |
|
8187 |
%} |
|
8188 |
%} |
|
8189 |
||
8190 |
// Register Shift Left Immediate |
|
8191 |
instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
|
|
8192 |
match(Set dst (LShiftI src1 src2)); |
|
8193 |
||
8194 |
format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
|
|
8195 |
size(4); |
|
8196 |
ins_encode %{
|
|
8197 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8198 |
__ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8199 |
%} |
|
8200 |
ins_pipe(pipe_class_default); |
|
8201 |
%} |
|
8202 |
||
8203 |
// AndI with negpow2-constant + LShiftI |
|
8204 |
instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
|
|
8205 |
match(Set dst (LShiftI (AndI src1 src2) src3)); |
|
8206 |
predicate(UseRotateAndMaskInstructionsPPC64); |
|
8207 |
||
8208 |
format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
|
|
8209 |
size(4); |
|
8210 |
ins_encode %{
|
|
8211 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi |
|
8212 |
long src2 = $src2$$constant; |
|
8213 |
long src3 = $src3$$constant; |
|
8214 |
long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); |
|
8215 |
if (maskbits >= 32) {
|
|
8216 |
__ li($dst$$Register, 0); // addi |
|
8217 |
} else {
|
|
8218 |
__ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); |
|
8219 |
} |
|
8220 |
%} |
|
8221 |
ins_pipe(pipe_class_default); |
|
8222 |
%} |
|
8223 |
||
8224 |
// RShiftI + AndI with negpow2-constant + LShiftI |
|
8225 |
instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
|
|
8226 |
match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); |
|
8227 |
predicate(UseRotateAndMaskInstructionsPPC64); |
|
8228 |
||
8229 |
format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
|
|
8230 |
size(4); |
|
8231 |
ins_encode %{
|
|
8232 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi |
|
8233 |
long src2 = $src2$$constant; |
|
8234 |
long src3 = $src3$$constant; |
|
8235 |
long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); |
|
8236 |
if (maskbits >= 32) {
|
|
8237 |
__ li($dst$$Register, 0); // addi |
|
8238 |
} else {
|
|
8239 |
__ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); |
|
8240 |
} |
|
8241 |
%} |
|
8242 |
ins_pipe(pipe_class_default); |
|
8243 |
%} |
|
8244 |
||
8245 |
instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8246 |
// no match-rule, false predicate |
|
8247 |
effect(DEF dst, USE src1, USE src2); |
|
8248 |
predicate(false); |
|
8249 |
||
8250 |
format %{ "SLD $dst, $src1, $src2" %}
|
|
8251 |
size(4); |
|
8252 |
ins_encode %{
|
|
8253 |
// TODO: PPC port $archOpcode(ppc64Opcode_sld); |
|
8254 |
__ sld($dst$$Register, $src1$$Register, $src2$$Register); |
|
8255 |
%} |
|
8256 |
ins_pipe(pipe_class_default); |
|
8257 |
%} |
|
8258 |
||
8259 |
// Register Shift Left |
|
8260 |
instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8261 |
match(Set dst (LShiftL src1 src2)); |
|
8262 |
ins_cost(DEFAULT_COST*2); |
|
8263 |
expand %{
|
|
8264 |
uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
|
|
8265 |
iRegIdst tmpI; |
|
8266 |
maskI_reg_imm(tmpI, src2, mask); |
|
8267 |
lShiftL_regL_regI(dst, src1, tmpI); |
|
8268 |
%} |
|
8269 |
%} |
|
8270 |
||
8271 |
// Register Shift Left Immediate |
|
8272 |
instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
|
|
8273 |
match(Set dst (LShiftL src1 src2)); |
|
8274 |
format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
|
|
8275 |
size(4); |
|
8276 |
ins_encode %{
|
|
8277 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8278 |
__ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8279 |
%} |
|
8280 |
ins_pipe(pipe_class_default); |
|
8281 |
%} |
|
8282 |
||
8283 |
// If we shift more than 32 bits, we need not convert I2L. |
|
8284 |
instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
|
|
8285 |
match(Set dst (LShiftL (ConvI2L src1) src2)); |
|
8286 |
ins_cost(DEFAULT_COST); |
|
8287 |
||
8288 |
size(4); |
|
8289 |
format %{ "SLDI $dst, i2l($src1), $src2" %}
|
|
8290 |
ins_encode %{
|
|
8291 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8292 |
__ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8293 |
%} |
|
8294 |
ins_pipe(pipe_class_default); |
|
8295 |
%} |
|
8296 |
||
8297 |
// Shift a postivie int to the left. |
|
8298 |
// Clrlsldi clears the upper 32 bits and shifts. |
|
8299 |
instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
|
|
8300 |
match(Set dst (LShiftL (ConvI2L src1) src2)); |
|
8301 |
predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); |
|
8302 |
||
8303 |
format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
|
|
8304 |
size(4); |
|
8305 |
ins_encode %{
|
|
8306 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldic); |
|
8307 |
__ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); |
|
8308 |
%} |
|
8309 |
ins_pipe(pipe_class_default); |
|
8310 |
%} |
|
8311 |
||
8312 |
instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8313 |
// no match-rule, false predicate |
|
8314 |
effect(DEF dst, USE src1, USE src2); |
|
8315 |
predicate(false); |
|
8316 |
||
8317 |
format %{ "SRAW $dst, $src1, $src2" %}
|
|
8318 |
size(4); |
|
8319 |
ins_encode %{
|
|
8320 |
// TODO: PPC port $archOpcode(ppc64Opcode_sraw); |
|
8321 |
__ sraw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8322 |
%} |
|
8323 |
ins_pipe(pipe_class_default); |
|
8324 |
%} |
|
8325 |
||
8326 |
// Register Arithmetic Shift Right |
|
8327 |
instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8328 |
match(Set dst (RShiftI src1 src2)); |
|
8329 |
ins_cost(DEFAULT_COST*2); |
|
8330 |
expand %{
|
|
8331 |
uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
|
|
8332 |
iRegIdst tmpI; |
|
8333 |
maskI_reg_imm(tmpI, src2, mask); |
|
8334 |
arShiftI_reg_reg(dst, src1, tmpI); |
|
8335 |
%} |
|
8336 |
%} |
|
8337 |
||
8338 |
// Register Arithmetic Shift Right Immediate |
|
8339 |
instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
|
|
8340 |
match(Set dst (RShiftI src1 src2)); |
|
8341 |
||
8342 |
format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
|
|
8343 |
size(4); |
|
8344 |
ins_encode %{
|
|
8345 |
// TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
8346 |
__ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8347 |
%} |
|
8348 |
ins_pipe(pipe_class_default); |
|
8349 |
%} |
|
8350 |
||
8351 |
instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8352 |
// no match-rule, false predicate |
|
8353 |
effect(DEF dst, USE src1, USE src2); |
|
8354 |
predicate(false); |
|
8355 |
||
8356 |
format %{ "SRAD $dst, $src1, $src2" %}
|
|
8357 |
size(4); |
|
8358 |
ins_encode %{
|
|
8359 |
// TODO: PPC port $archOpcode(ppc64Opcode_srad); |
|
8360 |
__ srad($dst$$Register, $src1$$Register, $src2$$Register); |
|
8361 |
%} |
|
8362 |
ins_pipe(pipe_class_default); |
|
8363 |
%} |
|
8364 |
||
8365 |
// Register Shift Right Arithmetic Long |
|
8366 |
instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8367 |
match(Set dst (RShiftL src1 src2)); |
|
8368 |
ins_cost(DEFAULT_COST*2); |
|
8369 |
||
8370 |
expand %{
|
|
8371 |
uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
|
|
8372 |
iRegIdst tmpI; |
|
8373 |
maskI_reg_imm(tmpI, src2, mask); |
|
8374 |
arShiftL_regL_regI(dst, src1, tmpI); |
|
8375 |
%} |
|
8376 |
%} |
|
8377 |
||
8378 |
// Register Shift Right Immediate |
|
8379 |
instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
|
|
8380 |
match(Set dst (RShiftL src1 src2)); |
|
8381 |
||
8382 |
format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
|
|
8383 |
size(4); |
|
8384 |
ins_encode %{
|
|
8385 |
// TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
8386 |
__ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8387 |
%} |
|
8388 |
ins_pipe(pipe_class_default); |
|
8389 |
%} |
|
8390 |
||
8391 |
// RShiftL + ConvL2I |
|
8392 |
instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
|
|
8393 |
match(Set dst (ConvL2I (RShiftL src1 src2))); |
|
8394 |
||
8395 |
format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
|
|
8396 |
size(4); |
|
8397 |
ins_encode %{
|
|
8398 |
// TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
8399 |
__ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8400 |
%} |
|
8401 |
ins_pipe(pipe_class_default); |
|
8402 |
%} |
|
8403 |
||
8404 |
instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8405 |
// no match-rule, false predicate |
|
8406 |
effect(DEF dst, USE src1, USE src2); |
|
8407 |
predicate(false); |
|
8408 |
||
8409 |
format %{ "SRW $dst, $src1, $src2" %}
|
|
8410 |
size(4); |
|
8411 |
ins_encode %{
|
|
8412 |
// TODO: PPC port $archOpcode(ppc64Opcode_srw); |
|
8413 |
__ srw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8414 |
%} |
|
8415 |
ins_pipe(pipe_class_default); |
|
8416 |
%} |
|
8417 |
||
8418 |
// Register Shift Right |
|
8419 |
instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8420 |
match(Set dst (URShiftI src1 src2)); |
|
8421 |
ins_cost(DEFAULT_COST*2); |
|
8422 |
||
8423 |
expand %{
|
|
8424 |
uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
|
|
8425 |
iRegIdst tmpI; |
|
8426 |
maskI_reg_imm(tmpI, src2, mask); |
|
8427 |
urShiftI_reg_reg(dst, src1, tmpI); |
|
8428 |
%} |
|
8429 |
%} |
|
8430 |
||
8431 |
// Register Shift Right Immediate |
|
8432 |
instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
|
|
8433 |
match(Set dst (URShiftI src1 src2)); |
|
8434 |
||
8435 |
format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
|
|
8436 |
size(4); |
|
8437 |
ins_encode %{
|
|
8438 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8439 |
__ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8440 |
%} |
|
8441 |
ins_pipe(pipe_class_default); |
|
8442 |
%} |
|
8443 |
||
8444 |
instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8445 |
// no match-rule, false predicate |
|
8446 |
effect(DEF dst, USE src1, USE src2); |
|
8447 |
predicate(false); |
|
8448 |
||
8449 |
format %{ "SRD $dst, $src1, $src2" %}
|
|
8450 |
size(4); |
|
8451 |
ins_encode %{
|
|
8452 |
// TODO: PPC port $archOpcode(ppc64Opcode_srd); |
|
8453 |
__ srd($dst$$Register, $src1$$Register, $src2$$Register); |
|
8454 |
%} |
|
8455 |
ins_pipe(pipe_class_default); |
|
8456 |
%} |
|
8457 |
||
8458 |
// Register Shift Right |
|
8459 |
instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
|
|
8460 |
match(Set dst (URShiftL src1 src2)); |
|
8461 |
ins_cost(DEFAULT_COST*2); |
|
8462 |
||
8463 |
expand %{
|
|
8464 |
uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
|
|
8465 |
iRegIdst tmpI; |
|
8466 |
maskI_reg_imm(tmpI, src2, mask); |
|
8467 |
urShiftL_regL_regI(dst, src1, tmpI); |
|
8468 |
%} |
|
8469 |
%} |
|
8470 |
||
8471 |
// Register Shift Right Immediate |
|
8472 |
instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
|
|
8473 |
match(Set dst (URShiftL src1 src2)); |
|
8474 |
||
8475 |
format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
|
|
8476 |
size(4); |
|
8477 |
ins_encode %{
|
|
8478 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8479 |
__ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8480 |
%} |
|
8481 |
ins_pipe(pipe_class_default); |
|
8482 |
%} |
|
8483 |
||
8484 |
// URShiftL + ConvL2I. |
|
8485 |
instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
|
|
8486 |
match(Set dst (ConvL2I (URShiftL src1 src2))); |
|
8487 |
||
8488 |
format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
|
|
8489 |
size(4); |
|
8490 |
ins_encode %{
|
|
8491 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8492 |
__ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8493 |
%} |
|
8494 |
ins_pipe(pipe_class_default); |
|
8495 |
%} |
|
8496 |
||
8497 |
// Register Shift Right Immediate with a CastP2X |
|
8498 |
instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
|
|
8499 |
match(Set dst (URShiftL (CastP2X src1) src2)); |
|
8500 |
||
8501 |
format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
|
|
8502 |
size(4); |
|
8503 |
ins_encode %{
|
|
8504 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8505 |
__ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8506 |
%} |
|
8507 |
ins_pipe(pipe_class_default); |
|
8508 |
%} |
|
8509 |
||
8510 |
instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
|
|
8511 |
match(Set dst (ConvL2I (ConvI2L src))); |
|
8512 |
||
8513 |
format %{ "EXTSW $dst, $src \t// int->int" %}
|
|
8514 |
size(4); |
|
8515 |
ins_encode %{
|
|
8516 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
8517 |
__ extsw($dst$$Register, $src$$Register); |
|
8518 |
%} |
|
8519 |
ins_pipe(pipe_class_default); |
|
8520 |
%} |
|
8521 |
||
8522 |
//----------Rotate Instructions------------------------------------------------ |
|
8523 |
||
8524 |
// Rotate Left by 8-bit immediate |
|
8525 |
instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
|
|
8526 |
match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); |
|
8527 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8528 |
||
8529 |
format %{ "ROTLWI $dst, $src, $lshift" %}
|
|
8530 |
size(4); |
|
8531 |
ins_encode %{
|
|
8532 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8533 |
__ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); |
|
8534 |
%} |
|
8535 |
ins_pipe(pipe_class_default); |
|
8536 |
%} |
|
8537 |
||
8538 |
// Rotate Right by 8-bit immediate |
|
8539 |
instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
|
|
8540 |
match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); |
|
8541 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8542 |
||
8543 |
format %{ "ROTRWI $dst, $rshift" %}
|
|
8544 |
size(4); |
|
8545 |
ins_encode %{
|
|
8546 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8547 |
__ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); |
|
8548 |
%} |
|
8549 |
ins_pipe(pipe_class_default); |
|
8550 |
%} |
|
8551 |
||
8552 |
//----------Floating Point Arithmetic Instructions----------------------------- |
|
8553 |
||
8554 |
// Add float single precision |
|
8555 |
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
8556 |
match(Set dst (AddF src1 src2)); |
|
8557 |
||
8558 |
format %{ "FADDS $dst, $src1, $src2" %}
|
|
8559 |
size(4); |
|
8560 |
ins_encode %{
|
|
8561 |
// TODO: PPC port $archOpcode(ppc64Opcode_fadds); |
|
8562 |
__ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8563 |
%} |
|
8564 |
ins_pipe(pipe_class_default); |
|
8565 |
%} |
|
8566 |
||
8567 |
// Add float double precision |
|
8568 |
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
8569 |
match(Set dst (AddD src1 src2)); |
|
8570 |
||
8571 |
format %{ "FADD $dst, $src1, $src2" %}
|
|
8572 |
size(4); |
|
8573 |
ins_encode %{
|
|
8574 |
// TODO: PPC port $archOpcode(ppc64Opcode_fadd); |
|
8575 |
__ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8576 |
%} |
|
8577 |
ins_pipe(pipe_class_default); |
|
8578 |
%} |
|
8579 |
||
8580 |
// Sub float single precision |
|
8581 |
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
8582 |
match(Set dst (SubF src1 src2)); |
|
8583 |
||
8584 |
format %{ "FSUBS $dst, $src1, $src2" %}
|
|
8585 |
size(4); |
|
8586 |
ins_encode %{
|
|
8587 |
// TODO: PPC port $archOpcode(ppc64Opcode_fsubs); |
|
8588 |
__ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8589 |
%} |
|
8590 |
ins_pipe(pipe_class_default); |
|
8591 |
%} |
|
8592 |
||
8593 |
// Sub float double precision |
|
8594 |
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
8595 |
match(Set dst (SubD src1 src2)); |
|
8596 |
format %{ "FSUB $dst, $src1, $src2" %}
|
|
8597 |
size(4); |
|
8598 |
ins_encode %{
|
|
8599 |
// TODO: PPC port $archOpcode(ppc64Opcode_fsub); |
|
8600 |
__ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8601 |
%} |
|
8602 |
ins_pipe(pipe_class_default); |
|
8603 |
%} |
|
8604 |
||
8605 |
// Mul float single precision |
|
8606 |
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
8607 |
match(Set dst (MulF src1 src2)); |
|
8608 |
format %{ "FMULS $dst, $src1, $src2" %}
|
|
8609 |
size(4); |
|
8610 |
ins_encode %{
|
|
8611 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmuls); |
|
8612 |
__ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8613 |
%} |
|
8614 |
ins_pipe(pipe_class_default); |
|
8615 |
%} |
|
8616 |
||
8617 |
// Mul float double precision |
|
8618 |
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
8619 |
match(Set dst (MulD src1 src2)); |
|
8620 |
format %{ "FMUL $dst, $src1, $src2" %}
|
|
8621 |
size(4); |
|
8622 |
ins_encode %{
|
|
8623 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmul); |
|
8624 |
__ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8625 |
%} |
|
8626 |
ins_pipe(pipe_class_default); |
|
8627 |
%} |
|
8628 |
||
8629 |
// Div float single precision |
|
8630 |
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
8631 |
match(Set dst (DivF src1 src2)); |
|
8632 |
format %{ "FDIVS $dst, $src1, $src2" %}
|
|
8633 |
size(4); |
|
8634 |
ins_encode %{
|
|
8635 |
// TODO: PPC port $archOpcode(ppc64Opcode_fdivs); |
|
8636 |
__ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8637 |
%} |
|
8638 |
ins_pipe(pipe_class_default); |
|
8639 |
%} |
|
8640 |
||
8641 |
// Div float double precision |
|
8642 |
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
8643 |
match(Set dst (DivD src1 src2)); |
|
8644 |
format %{ "FDIV $dst, $src1, $src2" %}
|
|
8645 |
size(4); |
|
8646 |
ins_encode %{
|
|
8647 |
// TODO: PPC port $archOpcode(ppc64Opcode_fdiv); |
|
8648 |
__ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8649 |
%} |
|
8650 |
ins_pipe(pipe_class_default); |
|
8651 |
%} |
|
8652 |
||
8653 |
// Absolute float single precision |
|
8654 |
instruct absF_reg(regF dst, regF src) %{
|
|
8655 |
match(Set dst (AbsF src)); |
|
8656 |
format %{ "FABS $dst, $src \t// float" %}
|
|
8657 |
size(4); |
|
8658 |
ins_encode %{
|
|
8659 |
// TODO: PPC port $archOpcode(ppc64Opcode_fabs); |
|
8660 |
__ fabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8661 |
%} |
|
8662 |
ins_pipe(pipe_class_default); |
|
8663 |
%} |
|
8664 |
||
8665 |
// Absolute float double precision |
|
8666 |
instruct absD_reg(regD dst, regD src) %{
|
|
8667 |
match(Set dst (AbsD src)); |
|
8668 |
format %{ "FABS $dst, $src \t// double" %}
|
|
8669 |
size(4); |
|
8670 |
ins_encode %{
|
|
8671 |
// TODO: PPC port $archOpcode(ppc64Opcode_fabs); |
|
8672 |
__ fabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8673 |
%} |
|
8674 |
ins_pipe(pipe_class_default); |
|
8675 |
%} |
|
8676 |
||
8677 |
instruct negF_reg(regF dst, regF src) %{
|
|
8678 |
match(Set dst (NegF src)); |
|
8679 |
format %{ "FNEG $dst, $src \t// float" %}
|
|
8680 |
size(4); |
|
8681 |
ins_encode %{
|
|
8682 |
// TODO: PPC port $archOpcode(ppc64Opcode_fneg); |
|
8683 |
__ fneg($dst$$FloatRegister, $src$$FloatRegister); |
|
8684 |
%} |
|
8685 |
ins_pipe(pipe_class_default); |
|
8686 |
%} |
|
8687 |
||
8688 |
instruct negD_reg(regD dst, regD src) %{
|
|
8689 |
match(Set dst (NegD src)); |
|
8690 |
format %{ "FNEG $dst, $src \t// double" %}
|
|
8691 |
size(4); |
|
8692 |
ins_encode %{
|
|
8693 |
// TODO: PPC port $archOpcode(ppc64Opcode_fneg); |
|
8694 |
__ fneg($dst$$FloatRegister, $src$$FloatRegister); |
|
8695 |
%} |
|
8696 |
ins_pipe(pipe_class_default); |
|
8697 |
%} |
|
8698 |
||
8699 |
// AbsF + NegF. |
|
8700 |
instruct negF_absF_reg(regF dst, regF src) %{
|
|
8701 |
match(Set dst (NegF (AbsF src))); |
|
8702 |
format %{ "FNABS $dst, $src \t// float" %}
|
|
8703 |
size(4); |
|
8704 |
ins_encode %{
|
|
8705 |
// TODO: PPC port $archOpcode(ppc64Opcode_fnabs); |
|
8706 |
__ fnabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8707 |
%} |
|
8708 |
ins_pipe(pipe_class_default); |
|
8709 |
%} |
|
8710 |
||
8711 |
// AbsD + NegD. |
|
8712 |
instruct negD_absD_reg(regD dst, regD src) %{
|
|
8713 |
match(Set dst (NegD (AbsD src))); |
|
8714 |
format %{ "FNABS $dst, $src \t// double" %}
|
|
8715 |
size(4); |
|
8716 |
ins_encode %{
|
|
8717 |
// TODO: PPC port $archOpcode(ppc64Opcode_fnabs); |
|
8718 |
__ fnabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8719 |
%} |
|
8720 |
ins_pipe(pipe_class_default); |
|
8721 |
%} |
|
8722 |
||
|
22879
177361c49b26
8035394: PPC64: Make usage of intrinsic dsqrt depend on processor recognition.
goetz
parents:
22874
diff
changeset
|
8723 |
// VM_Version::has_fsqrt() decides if this node will be used. |
| 22861 | 8724 |
// Sqrt float double precision |
8725 |
instruct sqrtD_reg(regD dst, regD src) %{
|
|
8726 |
match(Set dst (SqrtD src)); |
|
8727 |
format %{ "FSQRT $dst, $src" %}
|
|
8728 |
size(4); |
|
8729 |
ins_encode %{
|
|
8730 |
// TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); |
|
8731 |
__ fsqrt($dst$$FloatRegister, $src$$FloatRegister); |
|
8732 |
%} |
|
8733 |
ins_pipe(pipe_class_default); |
|
8734 |
%} |
|
8735 |
||
8736 |
// Single-precision sqrt. |
|
8737 |
instruct sqrtF_reg(regF dst, regF src) %{
|
|
8738 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
8739 |
ins_cost(DEFAULT_COST); |
|
8740 |
||
8741 |
format %{ "FSQRTS $dst, $src" %}
|
|
8742 |
size(4); |
|
8743 |
ins_encode %{
|
|
8744 |
// TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); |
|
8745 |
__ fsqrts($dst$$FloatRegister, $src$$FloatRegister); |
|
8746 |
%} |
|
8747 |
ins_pipe(pipe_class_default); |
|
8748 |
%} |
|
8749 |
||
8750 |
instruct roundDouble_nop(regD dst) %{
|
|
8751 |
match(Set dst (RoundDouble dst)); |
|
8752 |
ins_cost(0); |
|
8753 |
||
8754 |
format %{ " -- \t// RoundDouble not needed - empty" %}
|
|
8755 |
size(0); |
|
8756 |
// PPC results are already "rounded" (i.e., normal-format IEEE). |
|
8757 |
ins_encode( /*empty*/ ); |
|
8758 |
ins_pipe(pipe_class_default); |
|
8759 |
%} |
|
8760 |
||
8761 |
instruct roundFloat_nop(regF dst) %{
|
|
8762 |
match(Set dst (RoundFloat dst)); |
|
8763 |
ins_cost(0); |
|
8764 |
||
8765 |
format %{ " -- \t// RoundFloat not needed - empty" %}
|
|
8766 |
size(0); |
|
8767 |
// PPC results are already "rounded" (i.e., normal-format IEEE). |
|
8768 |
ins_encode( /*empty*/ ); |
|
8769 |
ins_pipe(pipe_class_default); |
|
8770 |
%} |
|
8771 |
||
8772 |
//----------Logical Instructions----------------------------------------------- |
|
8773 |
||
8774 |
// And Instructions |
|
8775 |
||
8776 |
// Register And |
|
8777 |
instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8778 |
match(Set dst (AndI src1 src2)); |
|
8779 |
format %{ "AND $dst, $src1, $src2" %}
|
|
8780 |
size(4); |
|
8781 |
ins_encode %{
|
|
8782 |
// TODO: PPC port $archOpcode(ppc64Opcode_and); |
|
8783 |
__ andr($dst$$Register, $src1$$Register, $src2$$Register); |
|
8784 |
%} |
|
8785 |
ins_pipe(pipe_class_default); |
|
8786 |
%} |
|
8787 |
||
8788 |
// Immediate And |
|
8789 |
instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
|
|
8790 |
match(Set dst (AndI src1 src2)); |
|
8791 |
effect(KILL cr0); |
|
8792 |
||
8793 |
format %{ "ANDI $dst, $src1, $src2" %}
|
|
8794 |
size(4); |
|
8795 |
ins_encode %{
|
|
8796 |
// TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
8797 |
// FIXME: avoid andi_ ? |
|
8798 |
__ andi_($dst$$Register, $src1$$Register, $src2$$constant); |
|
8799 |
%} |
|
8800 |
ins_pipe(pipe_class_default); |
|
8801 |
%} |
|
8802 |
||
8803 |
// Immediate And where the immediate is a negative power of 2. |
|
8804 |
instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
|
|
8805 |
match(Set dst (AndI src1 src2)); |
|
8806 |
format %{ "ANDWI $dst, $src1, $src2" %}
|
|
8807 |
size(4); |
|
8808 |
ins_encode %{
|
|
8809 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8810 |
__ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); |
|
8811 |
%} |
|
8812 |
ins_pipe(pipe_class_default); |
|
8813 |
%} |
|
8814 |
||
8815 |
instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
|
|
8816 |
match(Set dst (AndI src1 src2)); |
|
8817 |
format %{ "ANDWI $dst, $src1, $src2" %}
|
|
8818 |
size(4); |
|
8819 |
ins_encode %{
|
|
8820 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8821 |
__ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8822 |
%} |
|
8823 |
ins_pipe(pipe_class_default); |
|
8824 |
%} |
|
8825 |
||
8826 |
instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
|
|
8827 |
match(Set dst (AndI src1 src2)); |
|
8828 |
predicate(UseRotateAndMaskInstructionsPPC64); |
|
8829 |
format %{ "ANDWI $dst, $src1, $src2" %}
|
|
8830 |
size(4); |
|
8831 |
ins_encode %{
|
|
8832 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8833 |
__ rlwinm($dst$$Register, $src1$$Register, 0, |
|
8834 |
(31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); |
|
8835 |
%} |
|
8836 |
ins_pipe(pipe_class_default); |
|
8837 |
%} |
|
8838 |
||
8839 |
// Register And Long |
|
8840 |
instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
8841 |
match(Set dst (AndL src1 src2)); |
|
8842 |
ins_cost(DEFAULT_COST); |
|
8843 |
||
8844 |
format %{ "AND $dst, $src1, $src2 \t// long" %}
|
|
8845 |
size(4); |
|
8846 |
ins_encode %{
|
|
8847 |
// TODO: PPC port $archOpcode(ppc64Opcode_and); |
|
8848 |
__ andr($dst$$Register, $src1$$Register, $src2$$Register); |
|
8849 |
%} |
|
8850 |
ins_pipe(pipe_class_default); |
|
8851 |
%} |
|
8852 |
||
8853 |
// Immediate And long |
|
8854 |
instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
|
|
8855 |
match(Set dst (AndL src1 src2)); |
|
8856 |
effect(KILL cr0); |
|
8857 |
ins_cost(DEFAULT_COST); |
|
8858 |
||
8859 |
format %{ "ANDI $dst, $src1, $src2 \t// long" %}
|
|
8860 |
size(4); |
|
8861 |
ins_encode %{
|
|
8862 |
// TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
8863 |
// FIXME: avoid andi_ ? |
|
8864 |
__ andi_($dst$$Register, $src1$$Register, $src2$$constant); |
|
8865 |
%} |
|
8866 |
ins_pipe(pipe_class_default); |
|
8867 |
%} |
|
8868 |
||
8869 |
// Immediate And Long where the immediate is a negative power of 2. |
|
8870 |
instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
|
|
8871 |
match(Set dst (AndL src1 src2)); |
|
8872 |
format %{ "ANDDI $dst, $src1, $src2" %}
|
|
8873 |
size(4); |
|
8874 |
ins_encode %{
|
|
8875 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8876 |
__ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); |
|
8877 |
%} |
|
8878 |
ins_pipe(pipe_class_default); |
|
8879 |
%} |
|
8880 |
||
8881 |
instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
|
|
8882 |
match(Set dst (AndL src1 src2)); |
|
8883 |
format %{ "ANDDI $dst, $src1, $src2" %}
|
|
8884 |
size(4); |
|
8885 |
ins_encode %{
|
|
8886 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8887 |
__ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8888 |
%} |
|
8889 |
ins_pipe(pipe_class_default); |
|
8890 |
%} |
|
8891 |
||
8892 |
// AndL + ConvL2I. |
|
8893 |
instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
|
|
8894 |
match(Set dst (ConvL2I (AndL src1 src2))); |
|
8895 |
ins_cost(DEFAULT_COST); |
|
8896 |
||
8897 |
format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
|
|
8898 |
size(4); |
|
8899 |
ins_encode %{
|
|
8900 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8901 |
__ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8902 |
%} |
|
8903 |
ins_pipe(pipe_class_default); |
|
8904 |
%} |
|
8905 |
||
8906 |
// Or Instructions |
|
8907 |
||
8908 |
// Register Or |
|
8909 |
instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8910 |
match(Set dst (OrI src1 src2)); |
|
8911 |
format %{ "OR $dst, $src1, $src2" %}
|
|
8912 |
size(4); |
|
8913 |
ins_encode %{
|
|
8914 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8915 |
__ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8916 |
%} |
|
8917 |
ins_pipe(pipe_class_default); |
|
8918 |
%} |
|
8919 |
||
8920 |
// Expand does not work with above instruct. (??) |
|
8921 |
instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
8922 |
// no match-rule |
|
8923 |
effect(DEF dst, USE src1, USE src2); |
|
8924 |
format %{ "OR $dst, $src1, $src2" %}
|
|
8925 |
size(4); |
|
8926 |
ins_encode %{
|
|
8927 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8928 |
__ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8929 |
%} |
|
8930 |
ins_pipe(pipe_class_default); |
|
8931 |
%} |
|
8932 |
||
8933 |
instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
|
|
8934 |
match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); |
|
8935 |
ins_cost(DEFAULT_COST*3); |
|
8936 |
||
8937 |
expand %{
|
|
8938 |
// FIXME: we should do this in the ideal world. |
|
8939 |
iRegIdst tmp1; |
|
8940 |
iRegIdst tmp2; |
|
8941 |
orI_reg_reg(tmp1, src1, src2); |
|
8942 |
orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. |
|
8943 |
orI_reg_reg(dst, tmp1, tmp2); |
|
8944 |
%} |
|
8945 |
%} |
|
8946 |
||
8947 |
// Immediate Or |
|
8948 |
instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
|
|
8949 |
match(Set dst (OrI src1 src2)); |
|
8950 |
format %{ "ORI $dst, $src1, $src2" %}
|
|
8951 |
size(4); |
|
8952 |
ins_encode %{
|
|
8953 |
// TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
8954 |
__ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
8955 |
%} |
|
8956 |
ins_pipe(pipe_class_default); |
|
8957 |
%} |
|
8958 |
||
8959 |
// Register Or Long |
|
8960 |
instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
8961 |
match(Set dst (OrL src1 src2)); |
|
8962 |
ins_cost(DEFAULT_COST); |
|
8963 |
||
8964 |
size(4); |
|
8965 |
format %{ "OR $dst, $src1, $src2 \t// long" %}
|
|
8966 |
ins_encode %{
|
|
8967 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8968 |
__ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8969 |
%} |
|
8970 |
ins_pipe(pipe_class_default); |
|
8971 |
%} |
|
8972 |
||
8973 |
// OrL + ConvL2I. |
|
8974 |
instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
8975 |
match(Set dst (ConvL2I (OrL src1 src2))); |
|
8976 |
ins_cost(DEFAULT_COST); |
|
8977 |
||
8978 |
format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
|
|
8979 |
size(4); |
|
8980 |
ins_encode %{
|
|
8981 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8982 |
__ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8983 |
%} |
|
8984 |
ins_pipe(pipe_class_default); |
|
8985 |
%} |
|
8986 |
||
8987 |
// Immediate Or long |
|
8988 |
instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
|
|
8989 |
match(Set dst (OrL src1 con)); |
|
8990 |
ins_cost(DEFAULT_COST); |
|
8991 |
||
8992 |
format %{ "ORI $dst, $src1, $con \t// long" %}
|
|
8993 |
size(4); |
|
8994 |
ins_encode %{
|
|
8995 |
// TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
8996 |
__ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); |
|
8997 |
%} |
|
8998 |
ins_pipe(pipe_class_default); |
|
8999 |
%} |
|
9000 |
||
9001 |
// Xor Instructions |
|
9002 |
||
9003 |
// Register Xor |
|
9004 |
instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
9005 |
match(Set dst (XorI src1 src2)); |
|
9006 |
format %{ "XOR $dst, $src1, $src2" %}
|
|
9007 |
size(4); |
|
9008 |
ins_encode %{
|
|
9009 |
// TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9010 |
__ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9011 |
%} |
|
9012 |
ins_pipe(pipe_class_default); |
|
9013 |
%} |
|
9014 |
||
9015 |
// Expand does not work with above instruct. (??) |
|
9016 |
instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
9017 |
// no match-rule |
|
9018 |
effect(DEF dst, USE src1, USE src2); |
|
9019 |
format %{ "XOR $dst, $src1, $src2" %}
|
|
9020 |
size(4); |
|
9021 |
ins_encode %{
|
|
9022 |
// TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9023 |
__ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9024 |
%} |
|
9025 |
ins_pipe(pipe_class_default); |
|
9026 |
%} |
|
9027 |
||
9028 |
instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
|
|
9029 |
match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); |
|
9030 |
ins_cost(DEFAULT_COST*3); |
|
9031 |
||
9032 |
expand %{
|
|
9033 |
// FIXME: we should do this in the ideal world. |
|
9034 |
iRegIdst tmp1; |
|
9035 |
iRegIdst tmp2; |
|
9036 |
xorI_reg_reg(tmp1, src1, src2); |
|
9037 |
xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. |
|
9038 |
xorI_reg_reg(dst, tmp1, tmp2); |
|
9039 |
%} |
|
9040 |
%} |
|
9041 |
||
9042 |
// Immediate Xor |
|
9043 |
instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
|
|
9044 |
match(Set dst (XorI src1 src2)); |
|
9045 |
format %{ "XORI $dst, $src1, $src2" %}
|
|
9046 |
size(4); |
|
9047 |
ins_encode %{
|
|
9048 |
// TODO: PPC port $archOpcode(ppc64Opcode_xori); |
|
9049 |
__ xori($dst$$Register, $src1$$Register, $src2$$constant); |
|
9050 |
%} |
|
9051 |
ins_pipe(pipe_class_default); |
|
9052 |
%} |
|
9053 |
||
9054 |
// Register Xor Long |
|
9055 |
instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
9056 |
match(Set dst (XorL src1 src2)); |
|
9057 |
ins_cost(DEFAULT_COST); |
|
9058 |
||
9059 |
format %{ "XOR $dst, $src1, $src2 \t// long" %}
|
|
9060 |
size(4); |
|
9061 |
ins_encode %{
|
|
9062 |
// TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9063 |
__ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9064 |
%} |
|
9065 |
ins_pipe(pipe_class_default); |
|
9066 |
%} |
|
9067 |
||
9068 |
// XorL + ConvL2I. |
|
9069 |
instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
9070 |
match(Set dst (ConvL2I (XorL src1 src2))); |
|
9071 |
ins_cost(DEFAULT_COST); |
|
9072 |
||
9073 |
format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
|
|
9074 |
size(4); |
|
9075 |
ins_encode %{
|
|
9076 |
// TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9077 |
__ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9078 |
%} |
|
9079 |
ins_pipe(pipe_class_default); |
|
9080 |
%} |
|
9081 |
||
9082 |
// Immediate Xor Long |
|
9083 |
instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
|
|
9084 |
match(Set dst (XorL src1 src2)); |
|
9085 |
ins_cost(DEFAULT_COST); |
|
9086 |
||
9087 |
format %{ "XORI $dst, $src1, $src2 \t// long" %}
|
|
9088 |
size(4); |
|
9089 |
ins_encode %{
|
|
9090 |
// TODO: PPC port $archOpcode(ppc64Opcode_xori); |
|
9091 |
__ xori($dst$$Register, $src1$$Register, $src2$$constant); |
|
9092 |
%} |
|
9093 |
ins_pipe(pipe_class_default); |
|
9094 |
%} |
|
9095 |
||
9096 |
instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
|
|
9097 |
match(Set dst (XorI src1 src2)); |
|
9098 |
ins_cost(DEFAULT_COST); |
|
9099 |
||
9100 |
format %{ "NOT $dst, $src1 ($src2)" %}
|
|
9101 |
size(4); |
|
9102 |
ins_encode %{
|
|
9103 |
// TODO: PPC port $archOpcode(ppc64Opcode_nor); |
|
9104 |
__ nor($dst$$Register, $src1$$Register, $src1$$Register); |
|
9105 |
%} |
|
9106 |
ins_pipe(pipe_class_default); |
|
9107 |
%} |
|
9108 |
||
9109 |
instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
|
|
9110 |
match(Set dst (XorL src1 src2)); |
|
9111 |
ins_cost(DEFAULT_COST); |
|
9112 |
||
9113 |
format %{ "NOT $dst, $src1 ($src2) \t// long" %}
|
|
9114 |
size(4); |
|
9115 |
ins_encode %{
|
|
9116 |
// TODO: PPC port $archOpcode(ppc64Opcode_nor); |
|
9117 |
__ nor($dst$$Register, $src1$$Register, $src1$$Register); |
|
9118 |
%} |
|
9119 |
ins_pipe(pipe_class_default); |
|
9120 |
%} |
|
9121 |
||
9122 |
// And-complement |
|
9123 |
instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
|
|
9124 |
match(Set dst (AndI (XorI src1 src2) src3)); |
|
9125 |
ins_cost(DEFAULT_COST); |
|
9126 |
||
9127 |
format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
|
|
9128 |
size(4); |
|
9129 |
ins_encode( enc_andc(dst, src3, src1) ); |
|
9130 |
ins_pipe(pipe_class_default); |
|
9131 |
%} |
|
9132 |
||
9133 |
// And-complement |
|
9134 |
instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
9135 |
// no match-rule, false predicate |
|
9136 |
effect(DEF dst, USE src1, USE src2); |
|
9137 |
predicate(false); |
|
9138 |
||
9139 |
format %{ "ANDC $dst, $src1, $src2" %}
|
|
9140 |
size(4); |
|
9141 |
ins_encode %{
|
|
9142 |
// TODO: PPC port $archOpcode(ppc64Opcode_andc); |
|
9143 |
__ andc($dst$$Register, $src1$$Register, $src2$$Register); |
|
9144 |
%} |
|
9145 |
ins_pipe(pipe_class_default); |
|
9146 |
%} |
|
9147 |
||
9148 |
//----------Moves between int/long and float/double---------------------------- |
|
9149 |
// |
|
9150 |
// The following rules move values from int/long registers/stack-locations |
|
9151 |
// to float/double registers/stack-locations and vice versa, without doing any |
|
9152 |
// conversions. These rules are used to implement the bit-conversion methods |
|
9153 |
// of java.lang.Float etc., e.g. |
|
9154 |
// int floatToIntBits(float value) |
|
9155 |
// float intBitsToFloat(int bits) |
|
9156 |
// |
|
9157 |
// Notes on the implementation on ppc64: |
|
9158 |
// We only provide rules which move between a register and a stack-location, |
|
9159 |
// because we always have to go through memory when moving between a float |
|
9160 |
// register and an integer register. |
|
9161 |
||
9162 |
//---------- Chain stack slots between similar types -------- |
|
9163 |
||
9164 |
// These are needed so that the rules below can match. |
|
9165 |
||
9166 |
// Load integer from stack slot |
|
9167 |
instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
|
|
9168 |
match(Set dst src); |
|
9169 |
ins_cost(MEMORY_REF_COST); |
|
9170 |
||
9171 |
format %{ "LWZ $dst, $src" %}
|
|
9172 |
size(4); |
|
9173 |
ins_encode( enc_lwz(dst, src) ); |
|
9174 |
ins_pipe(pipe_class_memory); |
|
9175 |
%} |
|
9176 |
||
9177 |
// Store integer to stack slot |
|
9178 |
instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
|
|
9179 |
match(Set dst src); |
|
9180 |
ins_cost(MEMORY_REF_COST); |
|
9181 |
||
9182 |
format %{ "STW $src, $dst \t// stk" %}
|
|
9183 |
size(4); |
|
9184 |
ins_encode( enc_stw(src, dst) ); // rs=rt |
|
9185 |
ins_pipe(pipe_class_memory); |
|
9186 |
%} |
|
9187 |
||
9188 |
// Load long from stack slot |
|
9189 |
instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
|
|
9190 |
match(Set dst src); |
|
9191 |
ins_cost(MEMORY_REF_COST); |
|
9192 |
||
9193 |
format %{ "LD $dst, $src \t// long" %}
|
|
9194 |
size(4); |
|
9195 |
ins_encode( enc_ld(dst, src) ); |
|
9196 |
ins_pipe(pipe_class_memory); |
|
9197 |
%} |
|
9198 |
||
9199 |
// Store long to stack slot |
|
9200 |
instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
|
|
9201 |
match(Set dst src); |
|
9202 |
ins_cost(MEMORY_REF_COST); |
|
9203 |
||
9204 |
format %{ "STD $src, $dst \t// long" %}
|
|
9205 |
size(4); |
|
9206 |
ins_encode( enc_std(src, dst) ); // rs=rt |
|
9207 |
ins_pipe(pipe_class_memory); |
|
9208 |
%} |
|
9209 |
||
9210 |
//----------Moves between int and float |
|
9211 |
||
9212 |
// Move float value from float stack-location to integer register. |
|
9213 |
instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
|
|
9214 |
match(Set dst (MoveF2I src)); |
|
9215 |
ins_cost(MEMORY_REF_COST); |
|
9216 |
||
9217 |
format %{ "LWZ $dst, $src \t// MoveF2I" %}
|
|
9218 |
size(4); |
|
9219 |
ins_encode( enc_lwz(dst, src) ); |
|
9220 |
ins_pipe(pipe_class_memory); |
|
9221 |
%} |
|
9222 |
||
9223 |
// Move float value from float register to integer stack-location. |
|
9224 |
instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
|
|
9225 |
match(Set dst (MoveF2I src)); |
|
9226 |
ins_cost(MEMORY_REF_COST); |
|
9227 |
||
9228 |
format %{ "STFS $src, $dst \t// MoveF2I" %}
|
|
9229 |
size(4); |
|
9230 |
ins_encode( enc_stfs(src, dst) ); |
|
9231 |
ins_pipe(pipe_class_memory); |
|
9232 |
%} |
|
9233 |
||
9234 |
// Move integer value from integer stack-location to float register. |
|
9235 |
instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
|
|
9236 |
match(Set dst (MoveI2F src)); |
|
9237 |
ins_cost(MEMORY_REF_COST); |
|
9238 |
||
9239 |
format %{ "LFS $dst, $src \t// MoveI2F" %}
|
|
9240 |
size(4); |
|
9241 |
ins_encode %{
|
|
9242 |
// TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
9243 |
int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); |
|
9244 |
__ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); |
|
9245 |
%} |
|
9246 |
ins_pipe(pipe_class_memory); |
|
9247 |
%} |
|
9248 |
||
9249 |
// Move integer value from integer register to float stack-location. |
|
9250 |
instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
|
|
9251 |
match(Set dst (MoveI2F src)); |
|
9252 |
ins_cost(MEMORY_REF_COST); |
|
9253 |
||
9254 |
format %{ "STW $src, $dst \t// MoveI2F" %}
|
|
9255 |
size(4); |
|
9256 |
ins_encode( enc_stw(src, dst) ); |
|
9257 |
ins_pipe(pipe_class_memory); |
|
9258 |
%} |
|
9259 |
||
9260 |
//----------Moves between long and float |
|
9261 |
||
9262 |
instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
|
|
9263 |
// no match-rule, false predicate |
|
9264 |
effect(DEF dst, USE src); |
|
9265 |
predicate(false); |
|
9266 |
||
9267 |
format %{ "storeD $src, $dst \t// STACK" %}
|
|
9268 |
size(4); |
|
9269 |
ins_encode( enc_stfd(src, dst) ); |
|
9270 |
ins_pipe(pipe_class_default); |
|
9271 |
%} |
|
9272 |
||
9273 |
//----------Moves between long and double |
|
9274 |
||
9275 |
// Move double value from double stack-location to long register. |
|
9276 |
instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
|
|
9277 |
match(Set dst (MoveD2L src)); |
|
9278 |
ins_cost(MEMORY_REF_COST); |
|
9279 |
size(4); |
|
9280 |
format %{ "LD $dst, $src \t// MoveD2L" %}
|
|
9281 |
ins_encode( enc_ld(dst, src) ); |
|
9282 |
ins_pipe(pipe_class_memory); |
|
9283 |
%} |
|
9284 |
||
9285 |
// Move double value from double register to long stack-location. |
|
9286 |
instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
|
|
9287 |
match(Set dst (MoveD2L src)); |
|
9288 |
effect(DEF dst, USE src); |
|
9289 |
ins_cost(MEMORY_REF_COST); |
|
9290 |
||
9291 |
format %{ "STFD $src, $dst \t// MoveD2L" %}
|
|
9292 |
size(4); |
|
9293 |
ins_encode( enc_stfd(src, dst) ); |
|
9294 |
ins_pipe(pipe_class_memory); |
|
9295 |
%} |
|
9296 |
||
9297 |
// Move long value from long stack-location to double register. |
|
9298 |
instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
|
|
9299 |
match(Set dst (MoveL2D src)); |
|
9300 |
ins_cost(MEMORY_REF_COST); |
|
9301 |
||
9302 |
format %{ "LFD $dst, $src \t// MoveL2D" %}
|
|
9303 |
size(4); |
|
9304 |
ins_encode( enc_lfd(dst, src) ); |
|
9305 |
ins_pipe(pipe_class_memory); |
|
9306 |
%} |
|
9307 |
||
9308 |
// Move long value from long register to double stack-location. |
|
9309 |
instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
|
|
9310 |
match(Set dst (MoveL2D src)); |
|
9311 |
ins_cost(MEMORY_REF_COST); |
|
9312 |
||
9313 |
format %{ "STD $src, $dst \t// MoveL2D" %}
|
|
9314 |
size(4); |
|
9315 |
ins_encode( enc_std(src, dst) ); |
|
9316 |
ins_pipe(pipe_class_memory); |
|
9317 |
%} |
|
9318 |
||
9319 |
//----------Register Move Instructions----------------------------------------- |
|
9320 |
||
9321 |
// Replicate for Superword |
|
9322 |
||
9323 |
instruct moveReg(iRegLdst dst, iRegIsrc src) %{
|
|
9324 |
predicate(false); |
|
9325 |
effect(DEF dst, USE src); |
|
9326 |
||
9327 |
format %{ "MR $dst, $src \t// replicate " %}
|
|
9328 |
// variable size, 0 or 4. |
|
9329 |
ins_encode %{
|
|
9330 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9331 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
9332 |
%} |
|
9333 |
ins_pipe(pipe_class_default); |
|
9334 |
%} |
|
9335 |
||
9336 |
//----------Cast instructions (Java-level type cast)--------------------------- |
|
9337 |
||
9338 |
// Cast Long to Pointer for unsafe natives. |
|
9339 |
instruct castX2P(iRegPdst dst, iRegLsrc src) %{
|
|
9340 |
match(Set dst (CastX2P src)); |
|
9341 |
||
9342 |
format %{ "MR $dst, $src \t// Long->Ptr" %}
|
|
9343 |
// variable size, 0 or 4. |
|
9344 |
ins_encode %{
|
|
9345 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9346 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
9347 |
%} |
|
9348 |
ins_pipe(pipe_class_default); |
|
9349 |
%} |
|
9350 |
||
9351 |
// Cast Pointer to Long for unsafe natives. |
|
9352 |
instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
|
|
9353 |
match(Set dst (CastP2X src)); |
|
9354 |
||
9355 |
format %{ "MR $dst, $src \t// Ptr->Long" %}
|
|
9356 |
// variable size, 0 or 4. |
|
9357 |
ins_encode %{
|
|
9358 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9359 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
9360 |
%} |
|
9361 |
ins_pipe(pipe_class_default); |
|
9362 |
%} |
|
9363 |
||
9364 |
instruct castPP(iRegPdst dst) %{
|
|
9365 |
match(Set dst (CastPP dst)); |
|
9366 |
format %{ " -- \t// castPP of $dst" %}
|
|
9367 |
size(0); |
|
9368 |
ins_encode( /*empty*/ ); |
|
9369 |
ins_pipe(pipe_class_default); |
|
9370 |
%} |
|
9371 |
||
9372 |
instruct castII(iRegIdst dst) %{
|
|
9373 |
match(Set dst (CastII dst)); |
|
9374 |
format %{ " -- \t// castII of $dst" %}
|
|
9375 |
size(0); |
|
9376 |
ins_encode( /*empty*/ ); |
|
9377 |
ins_pipe(pipe_class_default); |
|
9378 |
%} |
|
9379 |
||
9380 |
instruct checkCastPP(iRegPdst dst) %{
|
|
9381 |
match(Set dst (CheckCastPP dst)); |
|
9382 |
format %{ " -- \t// checkcastPP of $dst" %}
|
|
9383 |
size(0); |
|
9384 |
ins_encode( /*empty*/ ); |
|
9385 |
ins_pipe(pipe_class_default); |
|
9386 |
%} |
|
9387 |
||
9388 |
//----------Convert instructions----------------------------------------------- |
|
9389 |
||
9390 |
// Convert to boolean. |
|
9391 |
||
9392 |
// int_to_bool(src) : { 1 if src != 0
|
|
9393 |
// { 0 else
|
|
9394 |
// |
|
9395 |
// strategy: |
|
9396 |
// 1) Count leading zeros of 32 bit-value src, |
|
9397 |
// this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. |
|
9398 |
// 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. |
|
9399 |
// 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. |
|
9400 |
||
9401 |
// convI2Bool |
|
9402 |
instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
|
|
9403 |
match(Set dst (Conv2B src)); |
|
9404 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9405 |
ins_cost(DEFAULT_COST); |
|
9406 |
||
9407 |
expand %{
|
|
9408 |
immI shiftAmount %{ 0x5 %}
|
|
9409 |
uimmI16 mask %{ 0x1 %}
|
|
9410 |
iRegIdst tmp1; |
|
9411 |
iRegIdst tmp2; |
|
9412 |
countLeadingZerosI(tmp1, src); |
|
9413 |
urShiftI_reg_imm(tmp2, tmp1, shiftAmount); |
|
9414 |
xorI_reg_uimm16(dst, tmp2, mask); |
|
9415 |
%} |
|
9416 |
%} |
|
9417 |
||
9418 |
instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
|
|
9419 |
match(Set dst (Conv2B src)); |
|
9420 |
effect(TEMP crx); |
|
9421 |
predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9422 |
ins_cost(DEFAULT_COST); |
|
9423 |
||
9424 |
format %{ "CMPWI $crx, $src, #0 \t// convI2B"
|
|
9425 |
"LI $dst, #0\n\t" |
|
9426 |
"BEQ $crx, done\n\t" |
|
9427 |
"LI $dst, #1\n" |
|
9428 |
"done:" %} |
|
9429 |
size(16); |
|
9430 |
ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); |
|
9431 |
ins_pipe(pipe_class_compare); |
|
9432 |
%} |
|
9433 |
||
9434 |
// ConvI2B + XorI |
|
9435 |
instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
|
|
9436 |
match(Set dst (XorI (Conv2B src) mask)); |
|
9437 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9438 |
ins_cost(DEFAULT_COST); |
|
9439 |
||
9440 |
expand %{
|
|
9441 |
immI shiftAmount %{ 0x5 %}
|
|
9442 |
iRegIdst tmp1; |
|
9443 |
countLeadingZerosI(tmp1, src); |
|
9444 |
urShiftI_reg_imm(dst, tmp1, shiftAmount); |
|
9445 |
%} |
|
9446 |
%} |
|
9447 |
||
9448 |
instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
|
|
9449 |
match(Set dst (XorI (Conv2B src) mask)); |
|
9450 |
effect(TEMP crx); |
|
9451 |
predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9452 |
ins_cost(DEFAULT_COST); |
|
9453 |
||
9454 |
format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
|
|
9455 |
"LI $dst, #1\n\t" |
|
9456 |
"BEQ $crx, done\n\t" |
|
9457 |
"LI $dst, #0\n" |
|
9458 |
"done:" %} |
|
9459 |
size(16); |
|
9460 |
ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); |
|
9461 |
ins_pipe(pipe_class_compare); |
|
9462 |
%} |
|
9463 |
||
9464 |
// AndI 0b0..010..0 + ConvI2B |
|
9465 |
instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
|
|
9466 |
match(Set dst (Conv2B (AndI src mask))); |
|
9467 |
predicate(UseRotateAndMaskInstructionsPPC64); |
|
9468 |
ins_cost(DEFAULT_COST); |
|
9469 |
||
9470 |
format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
|
|
9471 |
size(4); |
|
9472 |
ins_encode %{
|
|
9473 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
9474 |
__ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); |
|
9475 |
%} |
|
9476 |
ins_pipe(pipe_class_default); |
|
9477 |
%} |
|
9478 |
||
9479 |
// Convert pointer to boolean. |
|
9480 |
// |
|
9481 |
// ptr_to_bool(src) : { 1 if src != 0
|
|
9482 |
// { 0 else
|
|
9483 |
// |
|
9484 |
// strategy: |
|
9485 |
// 1) Count leading zeros of 64 bit-value src, |
|
9486 |
// this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. |
|
9487 |
// 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. |
|
9488 |
// 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. |
|
9489 |
||
9490 |
// ConvP2B |
|
9491 |
instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
|
|
9492 |
match(Set dst (Conv2B src)); |
|
9493 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9494 |
ins_cost(DEFAULT_COST); |
|
9495 |
||
9496 |
expand %{
|
|
9497 |
immI shiftAmount %{ 0x6 %}
|
|
9498 |
uimmI16 mask %{ 0x1 %}
|
|
9499 |
iRegIdst tmp1; |
|
9500 |
iRegIdst tmp2; |
|
9501 |
countLeadingZerosP(tmp1, src); |
|
9502 |
urShiftI_reg_imm(tmp2, tmp1, shiftAmount); |
|
9503 |
xorI_reg_uimm16(dst, tmp2, mask); |
|
9504 |
%} |
|
9505 |
%} |
|
9506 |
||
9507 |
instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
|
|
9508 |
match(Set dst (Conv2B src)); |
|
9509 |
effect(TEMP crx); |
|
9510 |
predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9511 |
ins_cost(DEFAULT_COST); |
|
9512 |
||
9513 |
format %{ "CMPDI $crx, $src, #0 \t// convP2B"
|
|
9514 |
"LI $dst, #0\n\t" |
|
9515 |
"BEQ $crx, done\n\t" |
|
9516 |
"LI $dst, #1\n" |
|
9517 |
"done:" %} |
|
9518 |
size(16); |
|
9519 |
ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); |
|
9520 |
ins_pipe(pipe_class_compare); |
|
9521 |
%} |
|
9522 |
||
9523 |
// ConvP2B + XorI |
|
9524 |
instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
|
|
9525 |
match(Set dst (XorI (Conv2B src) mask)); |
|
9526 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9527 |
ins_cost(DEFAULT_COST); |
|
9528 |
||
9529 |
expand %{
|
|
9530 |
immI shiftAmount %{ 0x6 %}
|
|
9531 |
iRegIdst tmp1; |
|
9532 |
countLeadingZerosP(tmp1, src); |
|
9533 |
urShiftI_reg_imm(dst, tmp1, shiftAmount); |
|
9534 |
%} |
|
9535 |
%} |
|
9536 |
||
9537 |
instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
|
|
9538 |
match(Set dst (XorI (Conv2B src) mask)); |
|
9539 |
effect(TEMP crx); |
|
9540 |
predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9541 |
ins_cost(DEFAULT_COST); |
|
9542 |
||
9543 |
format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
|
|
9544 |
"LI $dst, #1\n\t" |
|
9545 |
"BEQ $crx, done\n\t" |
|
9546 |
"LI $dst, #0\n" |
|
9547 |
"done:" %} |
|
9548 |
size(16); |
|
9549 |
ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); |
|
9550 |
ins_pipe(pipe_class_compare); |
|
9551 |
%} |
|
9552 |
||
9553 |
// if src1 < src2, return -1 else return 0 |
|
9554 |
instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
9555 |
match(Set dst (CmpLTMask src1 src2)); |
|
9556 |
ins_cost(DEFAULT_COST*4); |
|
9557 |
||
9558 |
expand %{
|
|
9559 |
iRegIdst src1s; |
|
9560 |
iRegIdst src2s; |
|
9561 |
iRegIdst diff; |
|
9562 |
sxtI_reg(src1s, src1); // ensure proper sign extention |
|
9563 |
sxtI_reg(src2s, src2); // ensure proper sign extention |
|
9564 |
subI_reg_reg(diff, src1s, src2s); |
|
9565 |
// Need to consider >=33 bit result, therefore we need signmaskL. |
|
9566 |
signmask64I_regI(dst, diff); |
|
9567 |
%} |
|
9568 |
%} |
|
9569 |
||
9570 |
instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
|
|
9571 |
match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 |
|
9572 |
format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
|
|
9573 |
size(4); |
|
9574 |
ins_encode %{
|
|
9575 |
// TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
9576 |
__ srawi($dst$$Register, $src1$$Register, 0x1f); |
|
9577 |
%} |
|
9578 |
ins_pipe(pipe_class_default); |
|
9579 |
%} |
|
9580 |
||
9581 |
//----------Arithmetic Conversion Instructions--------------------------------- |
|
9582 |
||
9583 |
// Convert to Byte -- nop |
|
9584 |
// Convert to Short -- nop |
|
9585 |
||
9586 |
// Convert to Int |
|
9587 |
||
9588 |
instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
|
|
9589 |
match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
9590 |
format %{ "EXTSB $dst, $src \t// byte->int" %}
|
|
9591 |
size(4); |
|
9592 |
ins_encode %{
|
|
9593 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsb); |
|
9594 |
__ extsb($dst$$Register, $src$$Register); |
|
9595 |
%} |
|
9596 |
ins_pipe(pipe_class_default); |
|
9597 |
%} |
|
9598 |
||
9599 |
// LShiftI 16 + RShiftI 16 converts short to int. |
|
9600 |
instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
|
|
9601 |
match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
9602 |
format %{ "EXTSH $dst, $src \t// short->int" %}
|
|
9603 |
size(4); |
|
9604 |
ins_encode %{
|
|
9605 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsh); |
|
9606 |
__ extsh($dst$$Register, $src$$Register); |
|
9607 |
%} |
|
9608 |
ins_pipe(pipe_class_default); |
|
9609 |
%} |
|
9610 |
||
9611 |
// ConvL2I + ConvI2L: Sign extend int in long register. |
|
9612 |
instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
|
|
9613 |
match(Set dst (ConvI2L (ConvL2I src))); |
|
9614 |
||
9615 |
format %{ "EXTSW $dst, $src \t// long->long" %}
|
|
9616 |
size(4); |
|
9617 |
ins_encode %{
|
|
9618 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
9619 |
__ extsw($dst$$Register, $src$$Register); |
|
9620 |
%} |
|
9621 |
ins_pipe(pipe_class_default); |
|
9622 |
%} |
|
9623 |
||
9624 |
instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
|
|
9625 |
match(Set dst (ConvL2I src)); |
|
9626 |
format %{ "MR $dst, $src \t// long->int" %}
|
|
9627 |
// variable size, 0 or 4 |
|
9628 |
ins_encode %{
|
|
9629 |
// TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9630 |
__ mr_if_needed($dst$$Register, $src$$Register); |
|
9631 |
%} |
|
9632 |
ins_pipe(pipe_class_default); |
|
9633 |
%} |
|
9634 |
||
9635 |
instruct convD2IRaw_regD(regD dst, regD src) %{
|
|
9636 |
// no match-rule, false predicate |
|
9637 |
effect(DEF dst, USE src); |
|
9638 |
predicate(false); |
|
9639 |
||
9640 |
format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
|
|
9641 |
size(4); |
|
9642 |
ins_encode %{
|
|
9643 |
// TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; |
|
9644 |
__ fctiwz($dst$$FloatRegister, $src$$FloatRegister); |
|
9645 |
%} |
|
9646 |
ins_pipe(pipe_class_default); |
|
9647 |
%} |
|
9648 |
||
9649 |
instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
|
|
9650 |
// no match-rule, false predicate |
|
9651 |
effect(DEF dst, USE crx, USE src); |
|
9652 |
predicate(false); |
|
9653 |
||
9654 |
ins_variable_size_depending_on_alignment(true); |
|
9655 |
||
9656 |
format %{ "cmovI $crx, $dst, $src" %}
|
|
9657 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
9658 |
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
9659 |
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); |
|
9660 |
ins_pipe(pipe_class_default); |
|
9661 |
%} |
|
9662 |
||
9663 |
instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
|
|
9664 |
// no match-rule, false predicate |
|
9665 |
effect(DEF dst, USE crx, USE mem); |
|
9666 |
predicate(false); |
|
9667 |
||
9668 |
format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
|
|
9669 |
postalloc_expand %{
|
|
9670 |
// |
|
9671 |
// replaces |
|
9672 |
// |
|
9673 |
// region dst crx mem |
|
9674 |
// \ | | / |
|
9675 |
// dst=cmovI_bso_stackSlotL_conLvalue0 |
|
9676 |
// |
|
9677 |
// with |
|
9678 |
// |
|
9679 |
// region dst |
|
9680 |
// \ / |
|
9681 |
// dst=loadConI16(0) |
|
9682 |
// | |
|
9683 |
// ^ region dst crx mem |
|
9684 |
// | \ | | / |
|
9685 |
// dst=cmovI_bso_stackSlotL |
|
9686 |
// |
|
9687 |
||
9688 |
// Create new nodes. |
|
9689 |
MachNode *m1 = new (C) loadConI16Node(); |
|
9690 |
MachNode *m2 = new (C) cmovI_bso_stackSlotLNode(); |
|
9691 |
||
9692 |
// inputs for new nodes |
|
9693 |
m1->add_req(n_region); |
|
9694 |
m2->add_req(n_region, n_crx, n_mem); |
|
9695 |
||
9696 |
// precedences for new nodes |
|
9697 |
m2->add_prec(m1); |
|
9698 |
||
9699 |
// operands for new nodes |
|
9700 |
m1->_opnds[0] = op_dst; |
|
9701 |
m1->_opnds[1] = new (C) immI16Oper(0); |
|
9702 |
||
9703 |
m2->_opnds[0] = op_dst; |
|
9704 |
m2->_opnds[1] = op_crx; |
|
9705 |
m2->_opnds[2] = op_mem; |
|
9706 |
||
9707 |
// registers for new nodes |
|
9708 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9709 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9710 |
||
9711 |
// Insert new nodes. |
|
9712 |
nodes->push(m1); |
|
9713 |
nodes->push(m2); |
|
9714 |
%} |
|
9715 |
%} |
|
9716 |
||
9717 |
// Double to Int conversion, NaN is mapped to 0. |
|
9718 |
instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
|
|
9719 |
match(Set dst (ConvD2I src)); |
|
9720 |
ins_cost(DEFAULT_COST); |
|
9721 |
||
9722 |
expand %{
|
|
9723 |
regD tmpD; |
|
9724 |
stackSlotL tmpS; |
|
9725 |
flagsReg crx; |
|
9726 |
cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9727 |
convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). |
|
9728 |
moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). |
|
9729 |
cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9730 |
%} |
|
9731 |
%} |
|
9732 |
||
9733 |
instruct convF2IRaw_regF(regF dst, regF src) %{
|
|
9734 |
// no match-rule, false predicate |
|
9735 |
effect(DEF dst, USE src); |
|
9736 |
predicate(false); |
|
9737 |
||
9738 |
format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
|
|
9739 |
size(4); |
|
9740 |
ins_encode %{
|
|
9741 |
// TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9742 |
__ fctiwz($dst$$FloatRegister, $src$$FloatRegister); |
|
9743 |
%} |
|
9744 |
ins_pipe(pipe_class_default); |
|
9745 |
%} |
|
9746 |
||
9747 |
// Float to Int conversion, NaN is mapped to 0. |
|
9748 |
instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
|
|
9749 |
match(Set dst (ConvF2I src)); |
|
9750 |
ins_cost(DEFAULT_COST); |
|
9751 |
||
9752 |
expand %{
|
|
9753 |
regF tmpF; |
|
9754 |
stackSlotL tmpS; |
|
9755 |
flagsReg crx; |
|
9756 |
cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9757 |
convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). |
|
9758 |
moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). |
|
9759 |
cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9760 |
%} |
|
9761 |
%} |
|
9762 |
||
9763 |
// Convert to Long |
|
9764 |
||
9765 |
instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
|
|
9766 |
match(Set dst (ConvI2L src)); |
|
9767 |
format %{ "EXTSW $dst, $src \t// int->long" %}
|
|
9768 |
size(4); |
|
9769 |
ins_encode %{
|
|
9770 |
// TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
9771 |
__ extsw($dst$$Register, $src$$Register); |
|
9772 |
%} |
|
9773 |
ins_pipe(pipe_class_default); |
|
9774 |
%} |
|
9775 |
||
9776 |
// Zero-extend: convert unsigned int to long (convUI2L). |
|
9777 |
instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
|
|
9778 |
match(Set dst (AndL (ConvI2L src) mask)); |
|
9779 |
ins_cost(DEFAULT_COST); |
|
9780 |
||
9781 |
format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
|
|
9782 |
size(4); |
|
9783 |
ins_encode %{
|
|
9784 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
9785 |
__ clrldi($dst$$Register, $src$$Register, 32); |
|
9786 |
%} |
|
9787 |
ins_pipe(pipe_class_default); |
|
9788 |
%} |
|
9789 |
||
9790 |
// Zero-extend: convert unsigned int to long in long register. |
|
9791 |
instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
|
|
9792 |
match(Set dst (AndL src mask)); |
|
9793 |
ins_cost(DEFAULT_COST); |
|
9794 |
||
9795 |
format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
|
|
9796 |
size(4); |
|
9797 |
ins_encode %{
|
|
9798 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
9799 |
__ clrldi($dst$$Register, $src$$Register, 32); |
|
9800 |
%} |
|
9801 |
ins_pipe(pipe_class_default); |
|
9802 |
%} |
|
9803 |
||
9804 |
instruct convF2LRaw_regF(regF dst, regF src) %{
|
|
9805 |
// no match-rule, false predicate |
|
9806 |
effect(DEF dst, USE src); |
|
9807 |
predicate(false); |
|
9808 |
||
9809 |
format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
|
|
9810 |
size(4); |
|
9811 |
ins_encode %{
|
|
9812 |
// TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9813 |
__ fctidz($dst$$FloatRegister, $src$$FloatRegister); |
|
9814 |
%} |
|
9815 |
ins_pipe(pipe_class_default); |
|
9816 |
%} |
|
9817 |
||
9818 |
instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
|
|
9819 |
// no match-rule, false predicate |
|
9820 |
effect(DEF dst, USE crx, USE src); |
|
9821 |
predicate(false); |
|
9822 |
||
9823 |
ins_variable_size_depending_on_alignment(true); |
|
9824 |
||
9825 |
format %{ "cmovL $crx, $dst, $src" %}
|
|
9826 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
9827 |
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
9828 |
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); |
|
9829 |
ins_pipe(pipe_class_default); |
|
9830 |
%} |
|
9831 |
||
9832 |
instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
|
|
9833 |
// no match-rule, false predicate |
|
9834 |
effect(DEF dst, USE crx, USE mem); |
|
9835 |
predicate(false); |
|
9836 |
||
9837 |
format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
|
|
9838 |
postalloc_expand %{
|
|
9839 |
// |
|
9840 |
// replaces |
|
9841 |
// |
|
9842 |
// region dst crx mem |
|
9843 |
// \ | | / |
|
9844 |
// dst=cmovL_bso_stackSlotL_conLvalue0 |
|
9845 |
// |
|
9846 |
// with |
|
9847 |
// |
|
9848 |
// region dst |
|
9849 |
// \ / |
|
9850 |
// dst=loadConL16(0) |
|
9851 |
// | |
|
9852 |
// ^ region dst crx mem |
|
9853 |
// | \ | | / |
|
9854 |
// dst=cmovL_bso_stackSlotL |
|
9855 |
// |
|
9856 |
||
9857 |
// Create new nodes. |
|
9858 |
MachNode *m1 = new (C) loadConL16Node(); |
|
9859 |
MachNode *m2 = new (C) cmovL_bso_stackSlotLNode(); |
|
9860 |
||
9861 |
// inputs for new nodes |
|
9862 |
m1->add_req(n_region); |
|
9863 |
m2->add_req(n_region, n_crx, n_mem); |
|
9864 |
m2->add_prec(m1); |
|
9865 |
||
9866 |
// operands for new nodes |
|
9867 |
m1->_opnds[0] = op_dst; |
|
9868 |
m1->_opnds[1] = new (C) immL16Oper(0); |
|
9869 |
m2->_opnds[0] = op_dst; |
|
9870 |
m2->_opnds[1] = op_crx; |
|
9871 |
m2->_opnds[2] = op_mem; |
|
9872 |
||
9873 |
// registers for new nodes |
|
9874 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9875 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9876 |
||
9877 |
// Insert new nodes. |
|
9878 |
nodes->push(m1); |
|
9879 |
nodes->push(m2); |
|
9880 |
%} |
|
9881 |
%} |
|
9882 |
||
9883 |
// Float to Long conversion, NaN is mapped to 0. |
|
9884 |
instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
|
|
9885 |
match(Set dst (ConvF2L src)); |
|
9886 |
ins_cost(DEFAULT_COST); |
|
9887 |
||
9888 |
expand %{
|
|
9889 |
regF tmpF; |
|
9890 |
stackSlotL tmpS; |
|
9891 |
flagsReg crx; |
|
9892 |
cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9893 |
convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). |
|
9894 |
moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). |
|
9895 |
cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9896 |
%} |
|
9897 |
%} |
|
9898 |
||
9899 |
instruct convD2LRaw_regD(regD dst, regD src) %{
|
|
9900 |
// no match-rule, false predicate |
|
9901 |
effect(DEF dst, USE src); |
|
9902 |
predicate(false); |
|
9903 |
||
9904 |
format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
|
|
9905 |
size(4); |
|
9906 |
ins_encode %{
|
|
9907 |
// TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9908 |
__ fctidz($dst$$FloatRegister, $src$$FloatRegister); |
|
9909 |
%} |
|
9910 |
ins_pipe(pipe_class_default); |
|
9911 |
%} |
|
9912 |
||
9913 |
// Double to Long conversion, NaN is mapped to 0. |
|
9914 |
instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
|
|
9915 |
match(Set dst (ConvD2L src)); |
|
9916 |
ins_cost(DEFAULT_COST); |
|
9917 |
||
9918 |
expand %{
|
|
9919 |
regD tmpD; |
|
9920 |
stackSlotL tmpS; |
|
9921 |
flagsReg crx; |
|
9922 |
cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9923 |
convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). |
|
9924 |
moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). |
|
9925 |
cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9926 |
%} |
|
9927 |
%} |
|
9928 |
||
9929 |
// Convert to Float |
|
9930 |
||
9931 |
// Placed here as needed in expand. |
|
9932 |
instruct convL2DRaw_regD(regD dst, regD src) %{
|
|
9933 |
// no match-rule, false predicate |
|
9934 |
effect(DEF dst, USE src); |
|
9935 |
predicate(false); |
|
9936 |
||
9937 |
format %{ "FCFID $dst, $src \t// convL2D" %}
|
|
9938 |
size(4); |
|
9939 |
ins_encode %{
|
|
9940 |
// TODO: PPC port $archOpcode(ppc64Opcode_fcfid); |
|
9941 |
__ fcfid($dst$$FloatRegister, $src$$FloatRegister); |
|
9942 |
%} |
|
9943 |
ins_pipe(pipe_class_default); |
|
9944 |
%} |
|
9945 |
||
9946 |
// Placed here as needed in expand. |
|
9947 |
instruct convD2F_reg(regF dst, regD src) %{
|
|
9948 |
match(Set dst (ConvD2F src)); |
|
9949 |
format %{ "FRSP $dst, $src \t// convD2F" %}
|
|
9950 |
size(4); |
|
9951 |
ins_encode %{
|
|
9952 |
// TODO: PPC port $archOpcode(ppc64Opcode_frsp); |
|
9953 |
__ frsp($dst$$FloatRegister, $src$$FloatRegister); |
|
9954 |
%} |
|
9955 |
ins_pipe(pipe_class_default); |
|
9956 |
%} |
|
9957 |
||
9958 |
// Integer to Float conversion. |
|
9959 |
instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
|
|
9960 |
match(Set dst (ConvI2F src)); |
|
9961 |
predicate(!VM_Version::has_fcfids()); |
|
9962 |
ins_cost(DEFAULT_COST); |
|
9963 |
||
9964 |
expand %{
|
|
9965 |
iRegLdst tmpL; |
|
9966 |
stackSlotL tmpS; |
|
9967 |
regD tmpD; |
|
9968 |
regD tmpD2; |
|
9969 |
convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
9970 |
regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
9971 |
moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
9972 |
convL2DRaw_regD(tmpD2, tmpD); // Convert to double. |
|
9973 |
convD2F_reg(dst, tmpD2); // Convert double to float. |
|
9974 |
%} |
|
9975 |
%} |
|
9976 |
||
9977 |
instruct convL2FRaw_regF(regF dst, regD src) %{
|
|
9978 |
// no match-rule, false predicate |
|
9979 |
effect(DEF dst, USE src); |
|
9980 |
predicate(false); |
|
9981 |
||
9982 |
format %{ "FCFIDS $dst, $src \t// convL2F" %}
|
|
9983 |
size(4); |
|
9984 |
ins_encode %{
|
|
9985 |
// TODO: PPC port $archOpcode(ppc64Opcode_fcfid); |
|
9986 |
__ fcfids($dst$$FloatRegister, $src$$FloatRegister); |
|
9987 |
%} |
|
9988 |
ins_pipe(pipe_class_default); |
|
9989 |
%} |
|
9990 |
||
9991 |
// Integer to Float conversion. Special version for Power7. |
|
9992 |
instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
|
|
9993 |
match(Set dst (ConvI2F src)); |
|
9994 |
predicate(VM_Version::has_fcfids()); |
|
9995 |
ins_cost(DEFAULT_COST); |
|
9996 |
||
9997 |
expand %{
|
|
9998 |
iRegLdst tmpL; |
|
9999 |
stackSlotL tmpS; |
|
10000 |
regD tmpD; |
|
10001 |
convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
10002 |
regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
10003 |
moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10004 |
convL2FRaw_regF(dst, tmpD); // Convert to float. |
|
10005 |
%} |
|
10006 |
%} |
|
10007 |
||
10008 |
// L2F to avoid runtime call. |
|
10009 |
instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
|
|
10010 |
match(Set dst (ConvL2F src)); |
|
10011 |
predicate(VM_Version::has_fcfids()); |
|
10012 |
ins_cost(DEFAULT_COST); |
|
10013 |
||
10014 |
expand %{
|
|
10015 |
stackSlotL tmpS; |
|
10016 |
regD tmpD; |
|
10017 |
regL_to_stkL(tmpS, src); // Store long to stack. |
|
10018 |
moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10019 |
convL2FRaw_regF(dst, tmpD); // Convert to float. |
|
10020 |
%} |
|
10021 |
%} |
|
10022 |
||
10023 |
// Moved up as used in expand. |
|
10024 |
//instruct convD2F_reg(regF dst, regD src) %{%}
|
|
10025 |
||
10026 |
// Convert to Double |
|
10027 |
||
10028 |
// Integer to Double conversion. |
|
10029 |
instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
|
|
10030 |
match(Set dst (ConvI2D src)); |
|
10031 |
ins_cost(DEFAULT_COST); |
|
10032 |
||
10033 |
expand %{
|
|
10034 |
iRegLdst tmpL; |
|
10035 |
stackSlotL tmpS; |
|
10036 |
regD tmpD; |
|
10037 |
convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
10038 |
regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
10039 |
moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10040 |
convL2DRaw_regD(dst, tmpD); // Convert to double. |
|
10041 |
%} |
|
10042 |
%} |
|
10043 |
||
10044 |
// Long to Double conversion |
|
10045 |
instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
|
|
10046 |
match(Set dst (ConvL2D src)); |
|
10047 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
10048 |
||
10049 |
expand %{
|
|
10050 |
regD tmpD; |
|
10051 |
moveL2D_stack_reg(tmpD, src); |
|
10052 |
convL2DRaw_regD(dst, tmpD); |
|
10053 |
%} |
|
10054 |
%} |
|
10055 |
||
10056 |
instruct convF2D_reg(regD dst, regF src) %{
|
|
10057 |
match(Set dst (ConvF2D src)); |
|
10058 |
format %{ "FMR $dst, $src \t// float->double" %}
|
|
10059 |
// variable size, 0 or 4 |
|
10060 |
ins_encode %{
|
|
10061 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
10062 |
__ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); |
|
10063 |
%} |
|
10064 |
ins_pipe(pipe_class_default); |
|
10065 |
%} |
|
10066 |
||
10067 |
//----------Control Flow Instructions------------------------------------------ |
|
10068 |
// Compare Instructions |
|
10069 |
||
10070 |
// Compare Integers |
|
10071 |
instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
|
|
10072 |
match(Set crx (CmpI src1 src2)); |
|
10073 |
size(4); |
|
10074 |
format %{ "CMPW $crx, $src1, $src2" %}
|
|
10075 |
ins_encode %{
|
|
10076 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmp); |
|
10077 |
__ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10078 |
%} |
|
10079 |
ins_pipe(pipe_class_compare); |
|
10080 |
%} |
|
10081 |
||
10082 |
instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
|
|
10083 |
match(Set crx (CmpI src1 src2)); |
|
10084 |
format %{ "CMPWI $crx, $src1, $src2" %}
|
|
10085 |
size(4); |
|
10086 |
ins_encode %{
|
|
10087 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10088 |
__ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10089 |
%} |
|
10090 |
ins_pipe(pipe_class_compare); |
|
10091 |
%} |
|
10092 |
||
10093 |
// (src1 & src2) == 0? |
|
10094 |
instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
|
|
10095 |
match(Set cr0 (CmpI (AndI src1 src2) zero)); |
|
10096 |
// r0 is killed |
|
10097 |
format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
|
|
10098 |
size(4); |
|
10099 |
ins_encode %{
|
|
10100 |
// TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
10101 |
// FIXME: avoid andi_ ? |
|
10102 |
__ andi_(R0, $src1$$Register, $src2$$constant); |
|
10103 |
%} |
|
10104 |
ins_pipe(pipe_class_compare); |
|
10105 |
%} |
|
10106 |
||
10107 |
instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
|
|
10108 |
match(Set crx (CmpL src1 src2)); |
|
10109 |
format %{ "CMPD $crx, $src1, $src2" %}
|
|
10110 |
size(4); |
|
10111 |
ins_encode %{
|
|
10112 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmp); |
|
10113 |
__ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10114 |
%} |
|
10115 |
ins_pipe(pipe_class_compare); |
|
10116 |
%} |
|
10117 |
||
10118 |
instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
|
|
10119 |
match(Set crx (CmpL src1 src2)); |
|
10120 |
format %{ "CMPDI $crx, $src1, $src2" %}
|
|
10121 |
size(4); |
|
10122 |
ins_encode %{
|
|
10123 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10124 |
__ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10125 |
%} |
|
10126 |
ins_pipe(pipe_class_compare); |
|
10127 |
%} |
|
10128 |
||
10129 |
instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
|
|
10130 |
match(Set cr0 (CmpL (AndL src1 src2) zero)); |
|
10131 |
// r0 is killed |
|
10132 |
format %{ "AND R0, $src1, $src2 \t// BTST long" %}
|
|
10133 |
size(4); |
|
10134 |
ins_encode %{
|
|
10135 |
// TODO: PPC port $archOpcode(ppc64Opcode_and_); |
|
10136 |
__ and_(R0, $src1$$Register, $src2$$Register); |
|
10137 |
%} |
|
10138 |
ins_pipe(pipe_class_compare); |
|
10139 |
%} |
|
10140 |
||
10141 |
instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
|
|
10142 |
match(Set cr0 (CmpL (AndL src1 src2) zero)); |
|
10143 |
// r0 is killed |
|
10144 |
format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
|
|
10145 |
size(4); |
|
10146 |
ins_encode %{
|
|
10147 |
// TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
10148 |
// FIXME: avoid andi_ ? |
|
10149 |
__ andi_(R0, $src1$$Register, $src2$$constant); |
|
10150 |
%} |
|
10151 |
ins_pipe(pipe_class_compare); |
|
10152 |
%} |
|
10153 |
||
10154 |
instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
|
|
10155 |
// no match-rule, false predicate |
|
10156 |
effect(DEF dst, USE crx); |
|
10157 |
predicate(false); |
|
10158 |
||
10159 |
ins_variable_size_depending_on_alignment(true); |
|
10160 |
||
10161 |
format %{ "cmovI $crx, $dst, -1, 0, +1" %}
|
|
10162 |
// Worst case is branch + move + branch + move + stop, no stop without scheduler. |
|
10163 |
size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); |
|
10164 |
ins_encode %{
|
|
10165 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
10166 |
Label done; |
|
10167 |
// li(Rdst, 0); // equal -> 0 |
|
10168 |
__ beq($crx$$CondRegister, done); |
|
10169 |
__ li($dst$$Register, 1); // greater -> +1 |
|
10170 |
__ bgt($crx$$CondRegister, done); |
|
10171 |
__ li($dst$$Register, -1); // unordered or less -> -1 |
|
10172 |
// TODO: PPC port__ endgroup_if_needed(_size == 20); |
|
10173 |
__ bind(done); |
|
10174 |
%} |
|
10175 |
ins_pipe(pipe_class_compare); |
|
10176 |
%} |
|
10177 |
||
10178 |
instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
|
|
10179 |
// no match-rule, false predicate |
|
10180 |
effect(DEF dst, USE crx); |
|
10181 |
predicate(false); |
|
10182 |
||
10183 |
format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
|
|
10184 |
postalloc_expand %{
|
|
10185 |
// |
|
10186 |
// replaces |
|
10187 |
// |
|
10188 |
// region crx |
|
10189 |
// \ | |
|
10190 |
// dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 |
|
10191 |
// |
|
10192 |
// with |
|
10193 |
// |
|
10194 |
// region |
|
10195 |
// \ |
|
10196 |
// dst=loadConI16(0) |
|
10197 |
// | |
|
10198 |
// ^ region crx |
|
10199 |
// | \ | |
|
10200 |
// dst=cmovI_conIvalueMinus1_conIvalue1 |
|
10201 |
// |
|
10202 |
||
10203 |
// Create new nodes. |
|
10204 |
MachNode *m1 = new (C) loadConI16Node(); |
|
10205 |
MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node(); |
|
10206 |
||
10207 |
// inputs for new nodes |
|
10208 |
m1->add_req(n_region); |
|
10209 |
m2->add_req(n_region, n_crx); |
|
10210 |
m2->add_prec(m1); |
|
10211 |
||
10212 |
// operands for new nodes |
|
10213 |
m1->_opnds[0] = op_dst; |
|
10214 |
m1->_opnds[1] = new (C) immI16Oper(0); |
|
10215 |
m2->_opnds[0] = op_dst; |
|
10216 |
m2->_opnds[1] = op_crx; |
|
10217 |
||
10218 |
// registers for new nodes |
|
10219 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
10220 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
10221 |
||
10222 |
// Insert new nodes. |
|
10223 |
nodes->push(m1); |
|
10224 |
nodes->push(m2); |
|
10225 |
%} |
|
10226 |
%} |
|
10227 |
||
10228 |
// Manifest a CmpL3 result in an integer register. Very painful. |
|
10229 |
// This is the test to avoid. |
|
10230 |
// (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) |
|
10231 |
instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
|
|
10232 |
match(Set dst (CmpL3 src1 src2)); |
|
10233 |
ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10234 |
||
10235 |
expand %{
|
|
10236 |
flagsReg tmp1; |
|
10237 |
cmpL_reg_reg(tmp1, src1, src2); |
|
10238 |
cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10239 |
%} |
|
10240 |
%} |
|
10241 |
||
10242 |
// Implicit range checks. |
|
10243 |
// A range check in the ideal world has one of the following shapes: |
|
10244 |
// - (If le (CmpU length index)), (IfTrue throw exception) |
|
10245 |
// - (If lt (CmpU index length)), (IfFalse throw exception) |
|
10246 |
// |
|
10247 |
// Match range check 'If le (CmpU length index)'. |
|
10248 |
instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
|
|
10249 |
match(If cmp (CmpU src_length index)); |
|
10250 |
effect(USE labl); |
|
10251 |
predicate(TrapBasedRangeChecks && |
|
10252 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && |
|
10253 |
PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && |
|
10254 |
(Matcher::branches_to_uncommon_trap(_leaf))); |
|
10255 |
||
10256 |
ins_is_TrapBasedCheckNode(true); |
|
10257 |
||
10258 |
format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
|
|
10259 |
size(4); |
|
10260 |
ins_encode %{
|
|
10261 |
// TODO: PPC port $archOpcode(ppc64Opcode_twi); |
|
10262 |
if ($cmp$$cmpcode == 0x1 /* less_equal */) {
|
|
10263 |
__ trap_range_check_le($src_length$$Register, $index$$constant); |
|
10264 |
} else {
|
|
10265 |
// Both successors are uncommon traps, probability is 0. |
|
10266 |
// Node got flipped during fixup flow. |
|
10267 |
assert($cmp$$cmpcode == 0x9, "must be greater"); |
|
10268 |
__ trap_range_check_g($src_length$$Register, $index$$constant); |
|
10269 |
} |
|
10270 |
%} |
|
10271 |
ins_pipe(pipe_class_trap); |
|
10272 |
%} |
|
10273 |
||
10274 |
// Match range check 'If lt (CmpU index length)'. |
|
10275 |
instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
|
|
10276 |
match(If cmp (CmpU src_index src_length)); |
|
10277 |
effect(USE labl); |
|
10278 |
predicate(TrapBasedRangeChecks && |
|
10279 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
10280 |
_leaf->as_If()->_prob >= PROB_ALWAYS && |
|
10281 |
(Matcher::branches_to_uncommon_trap(_leaf))); |
|
10282 |
||
10283 |
ins_is_TrapBasedCheckNode(true); |
|
10284 |
||
10285 |
format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
|
|
10286 |
size(4); |
|
10287 |
ins_encode %{
|
|
10288 |
// TODO: PPC port $archOpcode(ppc64Opcode_tw); |
|
10289 |
if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
|
|
10290 |
__ trap_range_check_ge($src_index$$Register, $src_length$$Register); |
|
10291 |
} else {
|
|
10292 |
// Both successors are uncommon traps, probability is 0. |
|
10293 |
// Node got flipped during fixup flow. |
|
10294 |
assert($cmp$$cmpcode == 0x8, "must be less"); |
|
10295 |
__ trap_range_check_l($src_index$$Register, $src_length$$Register); |
|
10296 |
} |
|
10297 |
%} |
|
10298 |
ins_pipe(pipe_class_trap); |
|
10299 |
%} |
|
10300 |
||
10301 |
// Match range check 'If lt (CmpU index length)'. |
|
10302 |
instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
|
|
10303 |
match(If cmp (CmpU src_index length)); |
|
10304 |
effect(USE labl); |
|
10305 |
predicate(TrapBasedRangeChecks && |
|
10306 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
10307 |
_leaf->as_If()->_prob >= PROB_ALWAYS && |
|
10308 |
(Matcher::branches_to_uncommon_trap(_leaf))); |
|
10309 |
||
10310 |
ins_is_TrapBasedCheckNode(true); |
|
10311 |
||
10312 |
format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
|
|
10313 |
size(4); |
|
10314 |
ins_encode %{
|
|
10315 |
// TODO: PPC port $archOpcode(ppc64Opcode_twi); |
|
10316 |
if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
|
|
10317 |
__ trap_range_check_ge($src_index$$Register, $length$$constant); |
|
10318 |
} else {
|
|
10319 |
// Both successors are uncommon traps, probability is 0. |
|
10320 |
// Node got flipped during fixup flow. |
|
10321 |
assert($cmp$$cmpcode == 0x8, "must be less"); |
|
10322 |
__ trap_range_check_l($src_index$$Register, $length$$constant); |
|
10323 |
} |
|
10324 |
%} |
|
10325 |
ins_pipe(pipe_class_trap); |
|
10326 |
%} |
|
10327 |
||
10328 |
instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
|
|
10329 |
match(Set crx (CmpU src1 src2)); |
|
10330 |
format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
|
|
10331 |
size(4); |
|
10332 |
ins_encode %{
|
|
10333 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10334 |
__ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10335 |
%} |
|
10336 |
ins_pipe(pipe_class_compare); |
|
10337 |
%} |
|
10338 |
||
10339 |
instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
|
|
10340 |
match(Set crx (CmpU src1 src2)); |
|
10341 |
size(4); |
|
10342 |
format %{ "CMPLWI $crx, $src1, $src2" %}
|
|
10343 |
ins_encode %{
|
|
10344 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpli); |
|
10345 |
__ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10346 |
%} |
|
10347 |
ins_pipe(pipe_class_compare); |
|
10348 |
%} |
|
10349 |
||
10350 |
// Implicit zero checks (more implicit null checks). |
|
10351 |
// No constant pool entries required. |
|
10352 |
instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
|
|
10353 |
match(If cmp (CmpN value zero)); |
|
10354 |
effect(USE labl); |
|
10355 |
predicate(TrapBasedNullChecks && |
|
10356 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
10357 |
_leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && |
|
10358 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
10359 |
ins_cost(1); |
|
10360 |
||
10361 |
ins_is_TrapBasedCheckNode(true); |
|
10362 |
||
10363 |
format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
|
|
10364 |
size(4); |
|
10365 |
ins_encode %{
|
|
10366 |
// TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
10367 |
if ($cmp$$cmpcode == 0xA) {
|
|
10368 |
__ trap_null_check($value$$Register); |
|
10369 |
} else {
|
|
10370 |
// Both successors are uncommon traps, probability is 0. |
|
10371 |
// Node got flipped during fixup flow. |
|
10372 |
assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); |
|
10373 |
__ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); |
|
10374 |
} |
|
10375 |
%} |
|
10376 |
ins_pipe(pipe_class_trap); |
|
10377 |
%} |
|
10378 |
||
10379 |
// Compare narrow oops. |
|
10380 |
instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
|
|
10381 |
match(Set crx (CmpN src1 src2)); |
|
10382 |
||
10383 |
size(4); |
|
10384 |
ins_cost(DEFAULT_COST); |
|
10385 |
format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
|
|
10386 |
ins_encode %{
|
|
10387 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10388 |
__ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10389 |
%} |
|
10390 |
ins_pipe(pipe_class_compare); |
|
10391 |
%} |
|
10392 |
||
10393 |
instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
|
|
10394 |
match(Set crx (CmpN src1 src2)); |
|
10395 |
// Make this more expensive than zeroCheckN_iReg_imm0. |
|
10396 |
ins_cost(DEFAULT_COST); |
|
10397 |
||
10398 |
format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
|
|
10399 |
size(4); |
|
10400 |
ins_encode %{
|
|
10401 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpli); |
|
10402 |
__ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10403 |
%} |
|
10404 |
ins_pipe(pipe_class_compare); |
|
10405 |
%} |
|
10406 |
||
10407 |
// Implicit zero checks (more implicit null checks). |
|
10408 |
// No constant pool entries required. |
|
10409 |
instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
|
|
10410 |
match(If cmp (CmpP value zero)); |
|
10411 |
effect(USE labl); |
|
10412 |
predicate(TrapBasedNullChecks && |
|
10413 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
10414 |
_leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && |
|
10415 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
10416 |
||
10417 |
ins_is_TrapBasedCheckNode(true); |
|
10418 |
||
10419 |
format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
|
|
10420 |
size(4); |
|
10421 |
ins_encode %{
|
|
10422 |
// TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
10423 |
if ($cmp$$cmpcode == 0xA) {
|
|
10424 |
__ trap_null_check($value$$Register); |
|
10425 |
} else {
|
|
10426 |
// Both successors are uncommon traps, probability is 0. |
|
10427 |
// Node got flipped during fixup flow. |
|
10428 |
assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); |
|
10429 |
__ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); |
|
10430 |
} |
|
10431 |
%} |
|
10432 |
ins_pipe(pipe_class_trap); |
|
10433 |
%} |
|
10434 |
||
10435 |
// Compare Pointers |
|
10436 |
instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
|
|
10437 |
match(Set crx (CmpP src1 src2)); |
|
10438 |
format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
|
|
10439 |
size(4); |
|
10440 |
ins_encode %{
|
|
10441 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10442 |
__ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10443 |
%} |
|
10444 |
ins_pipe(pipe_class_compare); |
|
10445 |
%} |
|
10446 |
||
10447 |
// Used in postalloc expand. |
|
10448 |
instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
|
|
10449 |
// This match rule prevents reordering of node before a safepoint. |
|
10450 |
// This only makes sense if this instructions is used exclusively |
|
10451 |
// for the expansion of EncodeP! |
|
10452 |
match(Set crx (CmpP src1 src2)); |
|
10453 |
predicate(false); |
|
10454 |
||
10455 |
format %{ "CMPDI $crx, $src1, $src2" %}
|
|
10456 |
size(4); |
|
10457 |
ins_encode %{
|
|
10458 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10459 |
__ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10460 |
%} |
|
10461 |
ins_pipe(pipe_class_compare); |
|
10462 |
%} |
|
10463 |
||
10464 |
//----------Float Compares---------------------------------------------------- |
|
10465 |
||
10466 |
instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
|
|
10467 |
// no match-rule, false predicate |
|
10468 |
effect(DEF crx, USE src1, USE src2); |
|
10469 |
predicate(false); |
|
10470 |
||
10471 |
format %{ "cmpFUrd $crx, $src1, $src2" %}
|
|
10472 |
size(4); |
|
10473 |
ins_encode %{
|
|
10474 |
// TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); |
|
10475 |
__ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
10476 |
%} |
|
10477 |
ins_pipe(pipe_class_default); |
|
10478 |
%} |
|
10479 |
||
10480 |
instruct cmov_bns_less(flagsReg crx) %{
|
|
10481 |
// no match-rule, false predicate |
|
10482 |
effect(DEF crx); |
|
10483 |
predicate(false); |
|
10484 |
||
10485 |
ins_variable_size_depending_on_alignment(true); |
|
10486 |
||
10487 |
format %{ "cmov $crx" %}
|
|
10488 |
// Worst case is branch + move + stop, no stop without scheduler. |
|
10489 |
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); |
|
10490 |
ins_encode %{
|
|
10491 |
// TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); |
|
10492 |
Label done; |
|
10493 |
__ bns($crx$$CondRegister, done); // not unordered -> keep crx |
|
10494 |
__ li(R0, 0); |
|
10495 |
__ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' |
|
10496 |
// TODO PPC port __ endgroup_if_needed(_size == 16); |
|
10497 |
__ bind(done); |
|
10498 |
%} |
|
10499 |
ins_pipe(pipe_class_default); |
|
10500 |
%} |
|
10501 |
||
10502 |
// Compare floating, generate condition code. |
|
10503 |
instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
|
|
10504 |
// FIXME: should we match 'If cmp (CmpF src1 src2))' ?? |
|
10505 |
// |
|
10506 |
// The following code sequence occurs a lot in mpegaudio: |
|
10507 |
// |
|
10508 |
// block BXX: |
|
10509 |
// 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): |
|
10510 |
// cmpFUrd CCR6, F11, F9 |
|
10511 |
// 4: instruct cmov_bns_less (cmpF_reg_reg-1): |
|
10512 |
// cmov CCR6 |
|
10513 |
// 8: instruct branchConSched: |
|
10514 |
// B_FARle CCR6, B56 P=0.500000 C=-1.000000 |
|
10515 |
match(Set crx (CmpF src1 src2)); |
|
10516 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
10517 |
||
10518 |
format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
|
|
10519 |
postalloc_expand %{
|
|
10520 |
// |
|
10521 |
// replaces |
|
10522 |
// |
|
10523 |
// region src1 src2 |
|
10524 |
// \ | | |
|
10525 |
// crx=cmpF_reg_reg |
|
10526 |
// |
|
10527 |
// with |
|
10528 |
// |
|
10529 |
// region src1 src2 |
|
10530 |
// \ | | |
|
10531 |
// crx=cmpFUnordered_reg_reg |
|
10532 |
// | |
|
10533 |
// ^ region |
|
10534 |
// | \ |
|
10535 |
// crx=cmov_bns_less |
|
10536 |
// |
|
10537 |
||
10538 |
// Create new nodes. |
|
10539 |
MachNode *m1 = new (C) cmpFUnordered_reg_regNode(); |
|
10540 |
MachNode *m2 = new (C) cmov_bns_lessNode(); |
|
10541 |
||
10542 |
// inputs for new nodes |
|
10543 |
m1->add_req(n_region, n_src1, n_src2); |
|
10544 |
m2->add_req(n_region); |
|
10545 |
m2->add_prec(m1); |
|
10546 |
||
10547 |
// operands for new nodes |
|
10548 |
m1->_opnds[0] = op_crx; |
|
10549 |
m1->_opnds[1] = op_src1; |
|
10550 |
m1->_opnds[2] = op_src2; |
|
10551 |
m2->_opnds[0] = op_crx; |
|
10552 |
||
10553 |
// registers for new nodes |
|
10554 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10555 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10556 |
||
10557 |
// Insert new nodes. |
|
10558 |
nodes->push(m1); |
|
10559 |
nodes->push(m2); |
|
10560 |
%} |
|
10561 |
%} |
|
10562 |
||
10563 |
// Compare float, generate -1,0,1 |
|
10564 |
instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
|
|
10565 |
match(Set dst (CmpF3 src1 src2)); |
|
10566 |
ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10567 |
||
10568 |
expand %{
|
|
10569 |
flagsReg tmp1; |
|
10570 |
cmpFUnordered_reg_reg(tmp1, src1, src2); |
|
10571 |
cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10572 |
%} |
|
10573 |
%} |
|
10574 |
||
10575 |
instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
|
|
10576 |
// no match-rule, false predicate |
|
10577 |
effect(DEF crx, USE src1, USE src2); |
|
10578 |
predicate(false); |
|
10579 |
||
10580 |
format %{ "cmpFUrd $crx, $src1, $src2" %}
|
|
10581 |
size(4); |
|
10582 |
ins_encode %{
|
|
10583 |
// TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); |
|
10584 |
__ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
10585 |
%} |
|
10586 |
ins_pipe(pipe_class_default); |
|
10587 |
%} |
|
10588 |
||
10589 |
instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
|
|
10590 |
match(Set crx (CmpD src1 src2)); |
|
10591 |
ins_cost(DEFAULT_COST+BRANCH_COST); |
|
10592 |
||
10593 |
format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
|
|
10594 |
postalloc_expand %{
|
|
10595 |
// |
|
10596 |
// replaces |
|
10597 |
// |
|
10598 |
// region src1 src2 |
|
10599 |
// \ | | |
|
10600 |
// crx=cmpD_reg_reg |
|
10601 |
// |
|
10602 |
// with |
|
10603 |
// |
|
10604 |
// region src1 src2 |
|
10605 |
// \ | | |
|
10606 |
// crx=cmpDUnordered_reg_reg |
|
10607 |
// | |
|
10608 |
// ^ region |
|
10609 |
// | \ |
|
10610 |
// crx=cmov_bns_less |
|
10611 |
// |
|
10612 |
||
10613 |
// create new nodes |
|
10614 |
MachNode *m1 = new (C) cmpDUnordered_reg_regNode(); |
|
10615 |
MachNode *m2 = new (C) cmov_bns_lessNode(); |
|
10616 |
||
10617 |
// inputs for new nodes |
|
10618 |
m1->add_req(n_region, n_src1, n_src2); |
|
10619 |
m2->add_req(n_region); |
|
10620 |
m2->add_prec(m1); |
|
10621 |
||
10622 |
// operands for new nodes |
|
10623 |
m1->_opnds[0] = op_crx; |
|
10624 |
m1->_opnds[1] = op_src1; |
|
10625 |
m1->_opnds[2] = op_src2; |
|
10626 |
m2->_opnds[0] = op_crx; |
|
10627 |
||
10628 |
// registers for new nodes |
|
10629 |
ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10630 |
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10631 |
||
10632 |
// Insert new nodes. |
|
10633 |
nodes->push(m1); |
|
10634 |
nodes->push(m2); |
|
10635 |
%} |
|
10636 |
%} |
|
10637 |
||
10638 |
// Compare double, generate -1,0,1 |
|
10639 |
instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
|
|
10640 |
match(Set dst (CmpD3 src1 src2)); |
|
10641 |
ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10642 |
||
10643 |
expand %{
|
|
10644 |
flagsReg tmp1; |
|
10645 |
cmpDUnordered_reg_reg(tmp1, src1, src2); |
|
10646 |
cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10647 |
%} |
|
10648 |
%} |
|
10649 |
||
10650 |
//----------Branches--------------------------------------------------------- |
|
10651 |
// Jump |
|
10652 |
||
10653 |
// Direct Branch. |
|
10654 |
instruct branch(label labl) %{
|
|
10655 |
match(Goto); |
|
10656 |
effect(USE labl); |
|
10657 |
ins_cost(BRANCH_COST); |
|
10658 |
||
10659 |
format %{ "B $labl" %}
|
|
10660 |
size(4); |
|
10661 |
ins_encode %{
|
|
10662 |
// TODO: PPC port $archOpcode(ppc64Opcode_b); |
|
10663 |
Label d; // dummy |
|
10664 |
__ bind(d); |
|
10665 |
Label* p = $labl$$label; |
|
10666 |
// `p' is `NULL' when this encoding class is used only to |
|
10667 |
// determine the size of the encoded instruction. |
|
10668 |
Label& l = (NULL == p)? d : *(p); |
|
10669 |
__ b(l); |
|
10670 |
%} |
|
10671 |
ins_pipe(pipe_class_default); |
|
10672 |
%} |
|
10673 |
||
10674 |
// Conditional Near Branch |
|
10675 |
instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
|
|
10676 |
// Same match rule as `branchConFar'. |
|
10677 |
match(If cmp crx); |
|
10678 |
effect(USE lbl); |
|
10679 |
ins_cost(BRANCH_COST); |
|
10680 |
||
10681 |
// If set to 1 this indicates that the current instruction is a |
|
10682 |
// short variant of a long branch. This avoids using this |
|
10683 |
// instruction in first-pass matching. It will then only be used in |
|
10684 |
// the `Shorten_branches' pass. |
|
10685 |
ins_short_branch(1); |
|
10686 |
||
10687 |
format %{ "B$cmp $crx, $lbl" %}
|
|
10688 |
size(4); |
|
10689 |
ins_encode( enc_bc(crx, cmp, lbl) ); |
|
10690 |
ins_pipe(pipe_class_default); |
|
10691 |
%} |
|
10692 |
||
10693 |
// This is for cases when the ppc64 `bc' instruction does not |
|
10694 |
// reach far enough. So we emit a far branch here, which is more |
|
10695 |
// expensive. |
|
10696 |
// |
|
10697 |
// Conditional Far Branch |
|
10698 |
instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
|
|
10699 |
// Same match rule as `branchCon'. |
|
10700 |
match(If cmp crx); |
|
10701 |
effect(USE crx, USE lbl); |
|
10702 |
predicate(!false /* TODO: PPC port HB_Schedule*/); |
|
10703 |
// Higher cost than `branchCon'. |
|
10704 |
ins_cost(5*BRANCH_COST); |
|
10705 |
||
10706 |
// This is not a short variant of a branch, but the long variant. |
|
10707 |
ins_short_branch(0); |
|
10708 |
||
10709 |
format %{ "B_FAR$cmp $crx, $lbl" %}
|
|
10710 |
size(8); |
|
10711 |
ins_encode( enc_bc_far(crx, cmp, lbl) ); |
|
10712 |
ins_pipe(pipe_class_default); |
|
10713 |
%} |
|
10714 |
||
10715 |
// Conditional Branch used with Power6 scheduler (can be far or short). |
|
10716 |
instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
|
|
10717 |
// Same match rule as `branchCon'. |
|
10718 |
match(If cmp crx); |
|
10719 |
effect(USE crx, USE lbl); |
|
10720 |
predicate(false /* TODO: PPC port HB_Schedule*/); |
|
10721 |
// Higher cost than `branchCon'. |
|
10722 |
ins_cost(5*BRANCH_COST); |
|
10723 |
||
10724 |
// Actually size doesn't depend on alignment but on shortening. |
|
10725 |
ins_variable_size_depending_on_alignment(true); |
|
10726 |
// long variant. |
|
10727 |
ins_short_branch(0); |
|
10728 |
||
10729 |
format %{ "B_FAR$cmp $crx, $lbl" %}
|
|
10730 |
size(8); // worst case |
|
10731 |
ins_encode( enc_bc_short_far(crx, cmp, lbl) ); |
|
10732 |
ins_pipe(pipe_class_default); |
|
10733 |
%} |
|
10734 |
||
10735 |
instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
|
|
10736 |
match(CountedLoopEnd cmp crx); |
|
10737 |
effect(USE labl); |
|
10738 |
ins_cost(BRANCH_COST); |
|
10739 |
||
10740 |
// short variant. |
|
10741 |
ins_short_branch(1); |
|
10742 |
||
10743 |
format %{ "B$cmp $crx, $labl \t// counted loop end" %}
|
|
10744 |
size(4); |
|
10745 |
ins_encode( enc_bc(crx, cmp, labl) ); |
|
10746 |
ins_pipe(pipe_class_default); |
|
10747 |
%} |
|
10748 |
||
10749 |
instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
|
|
10750 |
match(CountedLoopEnd cmp crx); |
|
10751 |
effect(USE labl); |
|
10752 |
predicate(!false /* TODO: PPC port HB_Schedule */); |
|
10753 |
ins_cost(BRANCH_COST); |
|
10754 |
||
10755 |
// Long variant. |
|
10756 |
ins_short_branch(0); |
|
10757 |
||
10758 |
format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
|
|
10759 |
size(8); |
|
10760 |
ins_encode( enc_bc_far(crx, cmp, labl) ); |
|
10761 |
ins_pipe(pipe_class_default); |
|
10762 |
%} |
|
10763 |
||
10764 |
// Conditional Branch used with Power6 scheduler (can be far or short). |
|
10765 |
instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
|
|
10766 |
match(CountedLoopEnd cmp crx); |
|
10767 |
effect(USE labl); |
|
10768 |
predicate(false /* TODO: PPC port HB_Schedule */); |
|
10769 |
// Higher cost than `branchCon'. |
|
10770 |
ins_cost(5*BRANCH_COST); |
|
10771 |
||
10772 |
// Actually size doesn't depend on alignment but on shortening. |
|
10773 |
ins_variable_size_depending_on_alignment(true); |
|
10774 |
// Long variant. |
|
10775 |
ins_short_branch(0); |
|
10776 |
||
10777 |
format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
|
|
10778 |
size(8); // worst case |
|
10779 |
ins_encode( enc_bc_short_far(crx, cmp, labl) ); |
|
10780 |
ins_pipe(pipe_class_default); |
|
10781 |
%} |
|
10782 |
||
10783 |
// ============================================================================ |
|
10784 |
// Java runtime operations, intrinsics and other complex operations. |
|
10785 |
||
10786 |
// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass |
|
10787 |
// array for an instance of the superklass. Set a hidden internal cache on a |
|
10788 |
// hit (cache is checked with exposed code in gen_subtype_check()). Return |
|
10789 |
// not zero for a miss or zero for a hit. The encoding ALSO sets flags. |
|
10790 |
// |
|
10791 |
// GL TODO: Improve this. |
|
10792 |
// - result should not be a TEMP |
|
10793 |
// - Add match rule as on sparc avoiding additional Cmp. |
|
10794 |
instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, |
|
10795 |
iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
|
|
10796 |
match(Set result (PartialSubtypeCheck subklass superklass)); |
|
10797 |
effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr); |
|
10798 |
ins_cost(DEFAULT_COST*10); |
|
10799 |
||
10800 |
format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
|
|
10801 |
ins_encode %{
|
|
10802 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10803 |
__ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, |
|
10804 |
$tmp_klass$$Register, NULL, $result$$Register); |
|
10805 |
%} |
|
10806 |
ins_pipe(pipe_class_default); |
|
10807 |
%} |
|
10808 |
||
10809 |
// inlined locking and unlocking |
|
10810 |
||
10811 |
instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
|
|
10812 |
match(Set crx (FastLock oop box)); |
|
10813 |
effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); |
|
10814 |
// TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); |
|
10815 |
||
10816 |
format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
|
|
10817 |
ins_encode %{
|
|
10818 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10819 |
__ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, |
|
10820 |
$tmp3$$Register, $tmp1$$Register, $tmp2$$Register); |
|
10821 |
// If locking was successfull, crx should indicate 'EQ'. |
|
10822 |
// The compiler generates a branch to the runtime call to |
|
10823 |
// _complete_monitor_locking_Java for the case where crx is 'NE'. |
|
10824 |
%} |
|
10825 |
ins_pipe(pipe_class_compare); |
|
10826 |
%} |
|
10827 |
||
10828 |
instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
|
|
10829 |
match(Set crx (FastUnlock oop box)); |
|
10830 |
effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); |
|
10831 |
||
10832 |
format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
|
|
10833 |
ins_encode %{
|
|
10834 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10835 |
__ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, |
|
10836 |
$tmp3$$Register, $tmp1$$Register, $tmp2$$Register); |
|
10837 |
// If unlocking was successfull, crx should indicate 'EQ'. |
|
10838 |
// The compiler generates a branch to the runtime call to |
|
10839 |
// _complete_monitor_unlocking_Java for the case where crx is 'NE'. |
|
10840 |
%} |
|
10841 |
ins_pipe(pipe_class_compare); |
|
10842 |
%} |
|
10843 |
||
10844 |
// Align address. |
|
10845 |
instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
|
|
10846 |
match(Set dst (CastX2P (AndL (CastP2X src) mask))); |
|
10847 |
||
10848 |
format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
|
|
10849 |
size(4); |
|
10850 |
ins_encode %{
|
|
10851 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
10852 |
__ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); |
|
10853 |
%} |
|
10854 |
ins_pipe(pipe_class_default); |
|
10855 |
%} |
|
10856 |
||
10857 |
// Array size computation. |
|
10858 |
instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
|
|
10859 |
match(Set dst (SubL (CastP2X end) (CastP2X start))); |
|
10860 |
||
10861 |
format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
|
|
10862 |
size(4); |
|
10863 |
ins_encode %{
|
|
10864 |
// TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
10865 |
__ subf($dst$$Register, $start$$Register, $end$$Register); |
|
10866 |
%} |
|
10867 |
ins_pipe(pipe_class_default); |
|
10868 |
%} |
|
10869 |
||
10870 |
// Clear-array with dynamic array-size. |
|
10871 |
instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
|
|
10872 |
match(Set dummy (ClearArray cnt base)); |
|
10873 |
effect(USE_KILL cnt, USE_KILL base, KILL ctr); |
|
10874 |
ins_cost(MEMORY_REF_COST); |
|
10875 |
||
10876 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
10877 |
||
10878 |
format %{ "ClearArray $cnt, $base" %}
|
|
10879 |
ins_encode %{
|
|
10880 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10881 |
__ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 |
|
10882 |
%} |
|
10883 |
ins_pipe(pipe_class_default); |
|
10884 |
%} |
|
10885 |
||
10886 |
// String_IndexOf for needle of length 1. |
|
10887 |
// |
|
10888 |
// Match needle into immediate operands: no loadConP node needed. Saves one |
|
10889 |
// register and two instructions over string_indexOf_imm1Node. |
|
10890 |
// |
|
10891 |
// Assumes register result differs from all input registers. |
|
10892 |
// |
|
10893 |
// Preserves registers haystack, haycnt |
|
10894 |
// Kills registers tmp1, tmp2 |
|
10895 |
// Defines registers result |
|
10896 |
// |
|
10897 |
// Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
10898 |
// |
|
10899 |
// Unfortunately this does not match too often. In many situations the AddP is used |
|
10900 |
// by several nodes, even several StrIndexOf nodes, breaking the match tree. |
|
10901 |
instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, |
|
10902 |
immP needleImm, immL offsetImm, immI_1 needlecntImm, |
|
10903 |
iRegIdst tmp1, iRegIdst tmp2, |
|
10904 |
flagsRegCR0 cr0, flagsRegCR1 cr1) %{
|
|
10905 |
predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported |
|
10906 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); |
|
10907 |
||
10908 |
effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); |
|
10909 |
||
10910 |
ins_cost(150); |
|
10911 |
format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
|
|
10912 |
"-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} |
|
10913 |
||
10914 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted |
|
10915 |
ins_encode %{
|
|
10916 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10917 |
immPOper *needleOper = (immPOper *)$needleImm; |
|
10918 |
const TypeOopPtr *t = needleOper->type()->isa_oopptr(); |
|
10919 |
ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * |
|
10920 |
||
10921 |
__ string_indexof_1($result$$Register, |
|
10922 |
$haystack$$Register, $haycnt$$Register, |
|
10923 |
R0, needle_values->char_at(0), |
|
10924 |
$tmp1$$Register, $tmp2$$Register); |
|
10925 |
%} |
|
10926 |
ins_pipe(pipe_class_compare); |
|
10927 |
%} |
|
10928 |
||
10929 |
// String_IndexOf for needle of length 1. |
|
10930 |
// |
|
10931 |
// Special case requires less registers and emits less instructions. |
|
10932 |
// |
|
10933 |
// Assumes register result differs from all input registers. |
|
10934 |
// |
|
10935 |
// Preserves registers haystack, haycnt |
|
10936 |
// Kills registers tmp1, tmp2, needle |
|
10937 |
// Defines registers result |
|
10938 |
// |
|
10939 |
// Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
10940 |
instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, |
|
10941 |
rscratch2RegP needle, immI_1 needlecntImm, |
|
10942 |
iRegIdst tmp1, iRegIdst tmp2, |
|
10943 |
flagsRegCR0 cr0, flagsRegCR1 cr1) %{
|
|
10944 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10945 |
effect(USE_KILL needle, /* TDEF needle, */ TEMP result, |
|
10946 |
TEMP tmp1, TEMP tmp2); |
|
10947 |
// Required for EA: check if it is still a type_array. |
|
10948 |
predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && |
|
10949 |
n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); |
|
10950 |
ins_cost(180); |
|
10951 |
||
10952 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
10953 |
||
10954 |
format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
|
|
10955 |
" -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} |
|
10956 |
ins_encode %{
|
|
10957 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10958 |
Node *ndl = in(operand_index($needle)); // The node that defines needle. |
|
10959 |
ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); |
|
10960 |
guarantee(needle_values, "sanity"); |
|
10961 |
if (needle_values != NULL) {
|
|
10962 |
__ string_indexof_1($result$$Register, |
|
10963 |
$haystack$$Register, $haycnt$$Register, |
|
10964 |
R0, needle_values->char_at(0), |
|
10965 |
$tmp1$$Register, $tmp2$$Register); |
|
10966 |
} else {
|
|
10967 |
__ string_indexof_1($result$$Register, |
|
10968 |
$haystack$$Register, $haycnt$$Register, |
|
10969 |
$needle$$Register, 0, |
|
10970 |
$tmp1$$Register, $tmp2$$Register); |
|
10971 |
} |
|
10972 |
%} |
|
10973 |
ins_pipe(pipe_class_compare); |
|
10974 |
%} |
|
10975 |
||
10976 |
// String_IndexOf. |
|
10977 |
// |
|
10978 |
// Length of needle as immediate. This saves instruction loading constant needle |
|
10979 |
// length. |
|
10980 |
// @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle |
|
10981 |
// completely or do it in vector instruction. This should save registers for |
|
10982 |
// needlecnt and needle. |
|
10983 |
// |
|
10984 |
// Assumes register result differs from all input registers. |
|
10985 |
// Overwrites haycnt, needlecnt. |
|
10986 |
// Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
10987 |
instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, |
|
10988 |
iRegPsrc needle, uimmI15 needlecntImm, |
|
10989 |
iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, |
|
10990 |
flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
|
|
10991 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10992 |
effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result, |
|
10993 |
TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); |
|
10994 |
// Required for EA: check if it is still a type_array. |
|
10995 |
predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && |
|
10996 |
n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); |
|
10997 |
ins_cost(250); |
|
10998 |
||
10999 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11000 |
||
11001 |
format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
|
|
11002 |
" -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} |
|
11003 |
ins_encode %{
|
|
11004 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11005 |
Node *ndl = in(operand_index($needle)); // The node that defines needle. |
|
11006 |
ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); |
|
11007 |
||
11008 |
__ string_indexof($result$$Register, |
|
11009 |
$haystack$$Register, $haycnt$$Register, |
|
11010 |
$needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, |
|
11011 |
$tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); |
|
11012 |
%} |
|
11013 |
ins_pipe(pipe_class_compare); |
|
11014 |
%} |
|
11015 |
||
11016 |
// StrIndexOf node. |
|
11017 |
// |
|
11018 |
// Assumes register result differs from all input registers. |
|
11019 |
// Overwrites haycnt, needlecnt. |
|
11020 |
// Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
11021 |
instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, |
|
11022 |
iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, |
|
11023 |
flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
|
|
11024 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
11025 |
effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ |
|
11026 |
TEMP result, |
|
11027 |
TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); |
|
11028 |
predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. |
|
11029 |
ins_cost(300); |
|
11030 |
||
11031 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11032 |
||
11033 |
format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
|
|
11034 |
" -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} |
|
11035 |
ins_encode %{
|
|
11036 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11037 |
__ string_indexof($result$$Register, |
|
11038 |
$haystack$$Register, $haycnt$$Register, |
|
11039 |
$needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. |
|
11040 |
$tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); |
|
11041 |
%} |
|
11042 |
ins_pipe(pipe_class_compare); |
|
11043 |
%} |
|
11044 |
||
11045 |
// String equals with immediate. |
|
11046 |
instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, |
|
11047 |
iRegPdst tmp1, iRegPdst tmp2, |
|
11048 |
flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
|
|
11049 |
match(Set result (StrEquals (Binary str1 str2) cntImm)); |
|
11050 |
effect(TEMP result, TEMP tmp1, TEMP tmp2, |
|
11051 |
KILL cr0, KILL cr6, KILL ctr); |
|
11052 |
predicate(SpecialStringEquals); // See Matcher::match_rule_supported. |
|
11053 |
ins_cost(250); |
|
11054 |
||
11055 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11056 |
||
11057 |
format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
|
|
11058 |
" -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} |
|
11059 |
ins_encode %{
|
|
11060 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11061 |
__ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, |
|
11062 |
$result$$Register, $tmp1$$Register, $tmp2$$Register); |
|
11063 |
%} |
|
11064 |
ins_pipe(pipe_class_compare); |
|
11065 |
%} |
|
11066 |
||
11067 |
// String equals. |
|
11068 |
// Use dst register classes if register gets killed, as it is the case for TEMP operands! |
|
11069 |
instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, |
|
11070 |
iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, |
|
11071 |
flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
|
|
11072 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
11073 |
effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, |
|
11074 |
KILL cr0, KILL cr1, KILL cr6, KILL ctr); |
|
11075 |
predicate(SpecialStringEquals); // See Matcher::match_rule_supported. |
|
11076 |
ins_cost(300); |
|
11077 |
||
11078 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11079 |
||
11080 |
format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
|
|
11081 |
" \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} |
|
11082 |
ins_encode %{
|
|
11083 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11084 |
__ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, |
|
11085 |
$tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); |
|
11086 |
%} |
|
11087 |
ins_pipe(pipe_class_compare); |
|
11088 |
%} |
|
11089 |
||
11090 |
// String compare. |
|
11091 |
// Char[] pointers are passed in. |
|
11092 |
// Use dst register classes if register gets killed, as it is the case for TEMP operands! |
|
11093 |
instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, |
|
11094 |
iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
|
|
11095 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
11096 |
effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr); |
|
11097 |
ins_cost(300); |
|
11098 |
||
11099 |
ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11100 |
||
11101 |
format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
|
|
11102 |
" \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} |
|
11103 |
ins_encode %{
|
|
11104 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11105 |
__ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, |
|
11106 |
$result$$Register, $tmp$$Register); |
|
11107 |
%} |
|
11108 |
ins_pipe(pipe_class_compare); |
|
11109 |
%} |
|
11110 |
||
11111 |
//---------- Min/Max Instructions --------------------------------------------- |
|
11112 |
||
11113 |
instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
11114 |
match(Set dst (MinI src1 src2)); |
|
11115 |
ins_cost(DEFAULT_COST*6); |
|
11116 |
||
11117 |
expand %{
|
|
11118 |
iRegIdst src1s; |
|
11119 |
iRegIdst src2s; |
|
11120 |
iRegIdst diff; |
|
11121 |
iRegIdst sm; |
|
11122 |
iRegIdst doz; // difference or zero |
|
11123 |
sxtI_reg(src1s, src1); // Ensure proper sign extention. |
|
11124 |
sxtI_reg(src2s, src2); // Ensure proper sign extention. |
|
11125 |
subI_reg_reg(diff, src2s, src1s); |
|
11126 |
// Need to consider >=33 bit result, therefore we need signmaskL. |
|
11127 |
signmask64I_regI(sm, diff); |
|
11128 |
andI_reg_reg(doz, diff, sm); // <=0 |
|
11129 |
addI_reg_reg(dst, doz, src1s); |
|
11130 |
%} |
|
11131 |
%} |
|
11132 |
||
11133 |
instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
|
11134 |
match(Set dst (MaxI src1 src2)); |
|
11135 |
ins_cost(DEFAULT_COST*6); |
|
11136 |
||
11137 |
expand %{
|
|
11138 |
immI_minus1 m1 %{ -1 %}
|
|
11139 |
iRegIdst src1s; |
|
11140 |
iRegIdst src2s; |
|
11141 |
iRegIdst diff; |
|
11142 |
iRegIdst sm; |
|
11143 |
iRegIdst doz; // difference or zero |
|
11144 |
sxtI_reg(src1s, src1); // Ensure proper sign extention. |
|
11145 |
sxtI_reg(src2s, src2); // Ensure proper sign extention. |
|
11146 |
subI_reg_reg(diff, src2s, src1s); |
|
11147 |
// Need to consider >=33 bit result, therefore we need signmaskL. |
|
11148 |
signmask64I_regI(sm, diff); |
|
11149 |
andcI_reg_reg(doz, sm, m1, diff); // >=0 |
|
11150 |
addI_reg_reg(dst, doz, src1s); |
|
11151 |
%} |
|
11152 |
%} |
|
11153 |
||
11154 |
//---------- Population Count Instructions ------------------------------------ |
|
11155 |
||
11156 |
// Popcnt for Power7. |
|
11157 |
instruct popCountI(iRegIdst dst, iRegIsrc src) %{
|
|
11158 |
match(Set dst (PopCountI src)); |
|
11159 |
predicate(UsePopCountInstruction && VM_Version::has_popcntw()); |
|
11160 |
ins_cost(DEFAULT_COST); |
|
11161 |
||
11162 |
format %{ "POPCNTW $dst, $src" %}
|
|
11163 |
size(4); |
|
11164 |
ins_encode %{
|
|
11165 |
// TODO: PPC port $archOpcode(ppc64Opcode_popcntb); |
|
11166 |
__ popcntw($dst$$Register, $src$$Register); |
|
11167 |
%} |
|
11168 |
ins_pipe(pipe_class_default); |
|
11169 |
%} |
|
11170 |
||
11171 |
// Popcnt for Power7. |
|
11172 |
instruct popCountL(iRegIdst dst, iRegLsrc src) %{
|
|
11173 |
predicate(UsePopCountInstruction && VM_Version::has_popcntw()); |
|
11174 |
match(Set dst (PopCountL src)); |
|
11175 |
ins_cost(DEFAULT_COST); |
|
11176 |
||
11177 |
format %{ "POPCNTD $dst, $src" %}
|
|
11178 |
size(4); |
|
11179 |
ins_encode %{
|
|
11180 |
// TODO: PPC port $archOpcode(ppc64Opcode_popcntb); |
|
11181 |
__ popcntd($dst$$Register, $src$$Register); |
|
11182 |
%} |
|
11183 |
ins_pipe(pipe_class_default); |
|
11184 |
%} |
|
11185 |
||
11186 |
instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
|
|
11187 |
match(Set dst (CountLeadingZerosI src)); |
|
11188 |
predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. |
|
11189 |
ins_cost(DEFAULT_COST); |
|
11190 |
||
11191 |
format %{ "CNTLZW $dst, $src" %}
|
|
11192 |
size(4); |
|
11193 |
ins_encode %{
|
|
11194 |
// TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); |
|
11195 |
__ cntlzw($dst$$Register, $src$$Register); |
|
11196 |
%} |
|
11197 |
ins_pipe(pipe_class_default); |
|
11198 |
%} |
|
11199 |
||
11200 |
instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
|
|
11201 |
match(Set dst (CountLeadingZerosL src)); |
|
11202 |
predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. |
|
11203 |
ins_cost(DEFAULT_COST); |
|
11204 |
||
11205 |
format %{ "CNTLZD $dst, $src" %}
|
|
11206 |
size(4); |
|
11207 |
ins_encode %{
|
|
11208 |
// TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); |
|
11209 |
__ cntlzd($dst$$Register, $src$$Register); |
|
11210 |
%} |
|
11211 |
ins_pipe(pipe_class_default); |
|
11212 |
%} |
|
11213 |
||
11214 |
instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
|
|
11215 |
// no match-rule, false predicate |
|
11216 |
effect(DEF dst, USE src); |
|
11217 |
predicate(false); |
|
11218 |
||
11219 |
format %{ "CNTLZD $dst, $src" %}
|
|
11220 |
size(4); |
|
11221 |
ins_encode %{
|
|
11222 |
// TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); |
|
11223 |
__ cntlzd($dst$$Register, $src$$Register); |
|
11224 |
%} |
|
11225 |
ins_pipe(pipe_class_default); |
|
11226 |
%} |
|
11227 |
||
11228 |
instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
|
|
11229 |
match(Set dst (CountTrailingZerosI src)); |
|
11230 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11231 |
ins_cost(DEFAULT_COST); |
|
11232 |
||
11233 |
expand %{
|
|
11234 |
immI16 imm1 %{ (int)-1 %}
|
|
11235 |
immI16 imm2 %{ (int)32 %}
|
|
11236 |
immI_minus1 m1 %{ -1 %}
|
|
11237 |
iRegIdst tmpI1; |
|
11238 |
iRegIdst tmpI2; |
|
11239 |
iRegIdst tmpI3; |
|
11240 |
addI_reg_imm16(tmpI1, src, imm1); |
|
11241 |
andcI_reg_reg(tmpI2, src, m1, tmpI1); |
|
11242 |
countLeadingZerosI(tmpI3, tmpI2); |
|
11243 |
subI_imm16_reg(dst, imm2, tmpI3); |
|
11244 |
%} |
|
11245 |
%} |
|
11246 |
||
11247 |
instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
|
|
11248 |
match(Set dst (CountTrailingZerosL src)); |
|
11249 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11250 |
ins_cost(DEFAULT_COST); |
|
11251 |
||
11252 |
expand %{
|
|
11253 |
immL16 imm1 %{ (long)-1 %}
|
|
11254 |
immI16 imm2 %{ (int)64 %}
|
|
11255 |
iRegLdst tmpL1; |
|
11256 |
iRegLdst tmpL2; |
|
11257 |
iRegIdst tmpL3; |
|
11258 |
addL_reg_imm16(tmpL1, src, imm1); |
|
11259 |
andcL_reg_reg(tmpL2, tmpL1, src); |
|
11260 |
countLeadingZerosL(tmpL3, tmpL2); |
|
11261 |
subI_imm16_reg(dst, imm2, tmpL3); |
|
11262 |
%} |
|
11263 |
%} |
|
11264 |
||
11265 |
// Expand nodes for byte_reverse_int. |
|
11266 |
instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
|
|
11267 |
effect(DEF dst, USE src, USE pos, USE shift); |
|
11268 |
predicate(false); |
|
11269 |
||
11270 |
format %{ "INSRWI $dst, $src, $pos, $shift" %}
|
|
11271 |
size(4); |
|
11272 |
ins_encode %{
|
|
11273 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); |
|
11274 |
__ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); |
|
11275 |
%} |
|
11276 |
ins_pipe(pipe_class_default); |
|
11277 |
%} |
|
11278 |
||
11279 |
// As insrwi_a, but with USE_DEF. |
|
11280 |
instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
|
|
11281 |
effect(USE_DEF dst, USE src, USE pos, USE shift); |
|
11282 |
predicate(false); |
|
11283 |
||
11284 |
format %{ "INSRWI $dst, $src, $pos, $shift" %}
|
|
11285 |
size(4); |
|
11286 |
ins_encode %{
|
|
11287 |
// TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); |
|
11288 |
__ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); |
|
11289 |
%} |
|
11290 |
ins_pipe(pipe_class_default); |
|
11291 |
%} |
|
11292 |
||
11293 |
// Just slightly faster than java implementation. |
|
11294 |
instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
|
|
11295 |
match(Set dst (ReverseBytesI src)); |
|
11296 |
predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11297 |
ins_cost(DEFAULT_COST); |
|
11298 |
||
11299 |
expand %{
|
|
11300 |
immI16 imm24 %{ (int) 24 %}
|
|
11301 |
immI16 imm16 %{ (int) 16 %}
|
|
11302 |
immI16 imm8 %{ (int) 8 %}
|
|
11303 |
immI16 imm4 %{ (int) 4 %}
|
|
11304 |
immI16 imm0 %{ (int) 0 %}
|
|
11305 |
iRegLdst tmpI1; |
|
11306 |
iRegLdst tmpI2; |
|
11307 |
iRegLdst tmpI3; |
|
11308 |
||
11309 |
urShiftI_reg_imm(tmpI1, src, imm24); |
|
11310 |
insrwi_a(dst, tmpI1, imm24, imm8); |
|
11311 |
urShiftI_reg_imm(tmpI2, src, imm16); |
|
11312 |
insrwi(dst, tmpI2, imm8, imm16); |
|
11313 |
urShiftI_reg_imm(tmpI3, src, imm8); |
|
11314 |
insrwi(dst, tmpI3, imm8, imm8); |
|
11315 |
insrwi(dst, src, imm0, imm8); |
|
11316 |
%} |
|
11317 |
%} |
|
11318 |
||
11319 |
//---------- Replicate Vector Instructions ------------------------------------ |
|
11320 |
||
11321 |
// Insrdi does replicate if src == dst. |
|
11322 |
instruct repl32(iRegLdst dst) %{
|
|
11323 |
predicate(false); |
|
11324 |
effect(USE_DEF dst); |
|
11325 |
||
11326 |
format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
|
|
11327 |
size(4); |
|
11328 |
ins_encode %{
|
|
11329 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11330 |
__ insrdi($dst$$Register, $dst$$Register, 32, 0); |
|
11331 |
%} |
|
11332 |
ins_pipe(pipe_class_default); |
|
11333 |
%} |
|
11334 |
||
11335 |
// Insrdi does replicate if src == dst. |
|
11336 |
instruct repl48(iRegLdst dst) %{
|
|
11337 |
predicate(false); |
|
11338 |
effect(USE_DEF dst); |
|
11339 |
||
11340 |
format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
|
|
11341 |
size(4); |
|
11342 |
ins_encode %{
|
|
11343 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11344 |
__ insrdi($dst$$Register, $dst$$Register, 48, 0); |
|
11345 |
%} |
|
11346 |
ins_pipe(pipe_class_default); |
|
11347 |
%} |
|
11348 |
||
11349 |
// Insrdi does replicate if src == dst. |
|
11350 |
instruct repl56(iRegLdst dst) %{
|
|
11351 |
predicate(false); |
|
11352 |
effect(USE_DEF dst); |
|
11353 |
||
11354 |
format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
|
|
11355 |
size(4); |
|
11356 |
ins_encode %{
|
|
11357 |
// TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11358 |
__ insrdi($dst$$Register, $dst$$Register, 56, 0); |
|
11359 |
%} |
|
11360 |
ins_pipe(pipe_class_default); |
|
11361 |
%} |
|
11362 |
||
11363 |
instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
|
|
11364 |
match(Set dst (ReplicateB src)); |
|
11365 |
predicate(n->as_Vector()->length() == 8); |
|
11366 |
expand %{
|
|
11367 |
moveReg(dst, src); |
|
11368 |
repl56(dst); |
|
11369 |
repl48(dst); |
|
11370 |
repl32(dst); |
|
11371 |
%} |
|
11372 |
%} |
|
11373 |
||
11374 |
instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
|
|
11375 |
match(Set dst (ReplicateB zero)); |
|
11376 |
predicate(n->as_Vector()->length() == 8); |
|
11377 |
format %{ "LI $dst, #0 \t// replicate8B" %}
|
|
11378 |
size(4); |
|
11379 |
ins_encode %{
|
|
11380 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11381 |
__ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11382 |
%} |
|
11383 |
ins_pipe(pipe_class_default); |
|
11384 |
%} |
|
11385 |
||
11386 |
instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
|
|
11387 |
match(Set dst (ReplicateB src)); |
|
11388 |
predicate(n->as_Vector()->length() == 8); |
|
11389 |
format %{ "LI $dst, #-1 \t// replicate8B" %}
|
|
11390 |
size(4); |
|
11391 |
ins_encode %{
|
|
11392 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11393 |
__ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11394 |
%} |
|
11395 |
ins_pipe(pipe_class_default); |
|
11396 |
%} |
|
11397 |
||
11398 |
instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
|
|
11399 |
match(Set dst (ReplicateS src)); |
|
11400 |
predicate(n->as_Vector()->length() == 4); |
|
11401 |
expand %{
|
|
11402 |
moveReg(dst, src); |
|
11403 |
repl48(dst); |
|
11404 |
repl32(dst); |
|
11405 |
%} |
|
11406 |
%} |
|
11407 |
||
11408 |
instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
|
|
11409 |
match(Set dst (ReplicateS zero)); |
|
11410 |
predicate(n->as_Vector()->length() == 4); |
|
11411 |
format %{ "LI $dst, #0 \t// replicate4C" %}
|
|
11412 |
size(4); |
|
11413 |
ins_encode %{
|
|
11414 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11415 |
__ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11416 |
%} |
|
11417 |
ins_pipe(pipe_class_default); |
|
11418 |
%} |
|
11419 |
||
11420 |
instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
|
|
11421 |
match(Set dst (ReplicateS src)); |
|
11422 |
predicate(n->as_Vector()->length() == 4); |
|
11423 |
format %{ "LI $dst, -1 \t// replicate4C" %}
|
|
11424 |
size(4); |
|
11425 |
ins_encode %{
|
|
11426 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11427 |
__ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11428 |
%} |
|
11429 |
ins_pipe(pipe_class_default); |
|
11430 |
%} |
|
11431 |
||
11432 |
instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
|
|
11433 |
match(Set dst (ReplicateI src)); |
|
11434 |
predicate(n->as_Vector()->length() == 2); |
|
11435 |
ins_cost(2 * DEFAULT_COST); |
|
11436 |
expand %{
|
|
11437 |
moveReg(dst, src); |
|
11438 |
repl32(dst); |
|
11439 |
%} |
|
11440 |
%} |
|
11441 |
||
11442 |
instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
|
|
11443 |
match(Set dst (ReplicateI zero)); |
|
11444 |
predicate(n->as_Vector()->length() == 2); |
|
11445 |
format %{ "LI $dst, #0 \t// replicate4C" %}
|
|
11446 |
size(4); |
|
11447 |
ins_encode %{
|
|
11448 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11449 |
__ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11450 |
%} |
|
11451 |
ins_pipe(pipe_class_default); |
|
11452 |
%} |
|
11453 |
||
11454 |
instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
|
|
11455 |
match(Set dst (ReplicateI src)); |
|
11456 |
predicate(n->as_Vector()->length() == 2); |
|
11457 |
format %{ "LI $dst, -1 \t// replicate4C" %}
|
|
11458 |
size(4); |
|
11459 |
ins_encode %{
|
|
11460 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11461 |
__ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11462 |
%} |
|
11463 |
ins_pipe(pipe_class_default); |
|
11464 |
%} |
|
11465 |
||
11466 |
// Move float to int register via stack, replicate. |
|
11467 |
instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
|
|
11468 |
match(Set dst (ReplicateF src)); |
|
11469 |
predicate(n->as_Vector()->length() == 2); |
|
11470 |
ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); |
|
11471 |
expand %{
|
|
11472 |
stackSlotL tmpS; |
|
11473 |
iRegIdst tmpI; |
|
11474 |
moveF2I_reg_stack(tmpS, src); // Move float to stack. |
|
11475 |
moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. |
|
11476 |
moveReg(dst, tmpI); // Move int to long reg. |
|
11477 |
repl32(dst); // Replicate bitpattern. |
|
11478 |
%} |
|
11479 |
%} |
|
11480 |
||
11481 |
// Replicate scalar constant to packed float values in Double register |
|
11482 |
instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
|
|
11483 |
match(Set dst (ReplicateF src)); |
|
11484 |
predicate(n->as_Vector()->length() == 2); |
|
11485 |
ins_cost(5 * DEFAULT_COST); |
|
11486 |
||
11487 |
format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
|
|
11488 |
postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); |
|
11489 |
%} |
|
11490 |
||
11491 |
// Replicate scalar zero constant to packed float values in Double register |
|
11492 |
instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
|
|
11493 |
match(Set dst (ReplicateF zero)); |
|
11494 |
predicate(n->as_Vector()->length() == 2); |
|
11495 |
||
11496 |
format %{ "LI $dst, #0 \t// replicate2F" %}
|
|
11497 |
ins_encode %{
|
|
11498 |
// TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11499 |
__ li($dst$$Register, 0x0); |
|
11500 |
%} |
|
11501 |
ins_pipe(pipe_class_default); |
|
11502 |
%} |
|
11503 |
||
11504 |
// ============================================================================ |
|
11505 |
// Safepoint Instruction |
|
11506 |
||
11507 |
instruct safePoint_poll(iRegPdst poll) %{
|
|
11508 |
match(SafePoint poll); |
|
11509 |
predicate(LoadPollAddressFromThread); |
|
11510 |
||
11511 |
// It caused problems to add the effect that r0 is killed, but this |
|
11512 |
// effect no longer needs to be mentioned, since r0 is not contained |
|
11513 |
// in a reg_class. |
|
11514 |
||
11515 |
format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
|
|
11516 |
size(4); |
|
11517 |
ins_encode( enc_poll(0x0, poll) ); |
|
11518 |
ins_pipe(pipe_class_default); |
|
11519 |
%} |
|
11520 |
||
11521 |
// Safepoint without per-thread support. Load address of page to poll |
|
11522 |
// as constant. |
|
11523 |
// Rscratch2RegP is R12. |
|
11524 |
// LoadConPollAddr node is added in pd_post_matching_hook(). It must be |
|
11525 |
// a seperate node so that the oop map is at the right location. |
|
11526 |
instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
|
|
11527 |
match(SafePoint poll); |
|
11528 |
predicate(!LoadPollAddressFromThread); |
|
11529 |
||
11530 |
// It caused problems to add the effect that r0 is killed, but this |
|
11531 |
// effect no longer needs to be mentioned, since r0 is not contained |
|
11532 |
// in a reg_class. |
|
11533 |
||
11534 |
format %{ "LD R12, addr of polling page\n\t"
|
|
11535 |
"LD R0, #0, R12 \t// Safepoint poll for GC" %} |
|
11536 |
ins_encode( enc_poll(0x0, poll) ); |
|
11537 |
ins_pipe(pipe_class_default); |
|
11538 |
%} |
|
11539 |
||
11540 |
// ============================================================================ |
|
11541 |
// Call Instructions |
|
11542 |
||
11543 |
// Call Java Static Instruction |
|
11544 |
||
11545 |
// Schedulable version of call static node. |
|
11546 |
instruct CallStaticJavaDirect(method meth) %{
|
|
11547 |
match(CallStaticJava); |
|
11548 |
effect(USE meth); |
|
11549 |
predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
11550 |
ins_cost(CALL_COST); |
|
11551 |
||
11552 |
ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); |
|
11553 |
||
11554 |
format %{ "CALL,static $meth \t// ==> " %}
|
|
11555 |
size(4); |
|
11556 |
ins_encode( enc_java_static_call(meth) ); |
|
11557 |
ins_pipe(pipe_class_call); |
|
11558 |
%} |
|
11559 |
||
11560 |
// Schedulable version of call static node. |
|
11561 |
instruct CallStaticJavaDirectHandle(method meth) %{
|
|
11562 |
match(CallStaticJava); |
|
11563 |
effect(USE meth); |
|
11564 |
predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
11565 |
ins_cost(CALL_COST); |
|
11566 |
||
11567 |
ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); |
|
11568 |
||
11569 |
format %{ "CALL,static $meth \t// ==> " %}
|
|
11570 |
ins_encode( enc_java_handle_call(meth) ); |
|
11571 |
ins_pipe(pipe_class_call); |
|
11572 |
%} |
|
11573 |
||
11574 |
// Call Java Dynamic Instruction |
|
11575 |
||
11576 |
// Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). |
|
11577 |
// Loading of IC was postalloc expanded. The nodes loading the IC are reachable |
|
11578 |
// via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. |
|
11579 |
// The call destination must still be placed in the constant pool. |
|
11580 |
instruct CallDynamicJavaDirectSched(method meth) %{
|
|
11581 |
match(CallDynamicJava); // To get all the data fields we need ... |
|
11582 |
effect(USE meth); |
|
11583 |
predicate(false); // ... but never match. |
|
11584 |
||
11585 |
ins_field_load_ic_hi_node(loadConL_hiNode*); |
|
11586 |
ins_field_load_ic_node(loadConLNode*); |
|
11587 |
ins_num_consts(1 /* 1 patchable constant: call destination */); |
|
11588 |
||
11589 |
format %{ "BL \t// dynamic $meth ==> " %}
|
|
11590 |
size(4); |
|
11591 |
ins_encode( enc_java_dynamic_call_sched(meth) ); |
|
11592 |
ins_pipe(pipe_class_call); |
|
11593 |
%} |
|
11594 |
||
11595 |
// Schedulable (i.e. postalloc expanded) version of call dynamic java. |
|
11596 |
// We use postalloc expanded calls if we use inline caches |
|
11597 |
// and do not update method data. |
|
11598 |
// |
|
11599 |
// This instruction has two constants: inline cache (IC) and call destination. |
|
11600 |
// Loading the inline cache will be postalloc expanded, thus leaving a call with |
|
11601 |
// one constant. |
|
11602 |
instruct CallDynamicJavaDirectSched_Ex(method meth) %{
|
|
11603 |
match(CallDynamicJava); |
|
11604 |
effect(USE meth); |
|
11605 |
predicate(UseInlineCaches); |
|
11606 |
ins_cost(CALL_COST); |
|
11607 |
||
11608 |
ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); |
|
11609 |
||
11610 |
format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
|
|
11611 |
postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); |
|
11612 |
%} |
|
11613 |
||
11614 |
// Compound version of call dynamic java |
|
11615 |
// We use postalloc expanded calls if we use inline caches |
|
11616 |
// and do not update method data. |
|
11617 |
instruct CallDynamicJavaDirect(method meth) %{
|
|
11618 |
match(CallDynamicJava); |
|
11619 |
effect(USE meth); |
|
11620 |
predicate(!UseInlineCaches); |
|
11621 |
ins_cost(CALL_COST); |
|
11622 |
||
11623 |
// Enc_java_to_runtime_call needs up to 4 constants (method data oop). |
|
11624 |
ins_num_consts(4); |
|
11625 |
||
11626 |
format %{ "CALL,dynamic $meth \t// ==> " %}
|
|
11627 |
ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); |
|
11628 |
ins_pipe(pipe_class_call); |
|
11629 |
%} |
|
11630 |
||
11631 |
// Call Runtime Instruction |
|
11632 |
||
11633 |
instruct CallRuntimeDirect(method meth) %{
|
|
11634 |
match(CallRuntime); |
|
11635 |
effect(USE meth); |
|
11636 |
ins_cost(CALL_COST); |
|
11637 |
||
11638 |
// Enc_java_to_runtime_call needs up to 3 constants: call target, |
|
11639 |
// env for callee, C-toc. |
|
11640 |
ins_num_consts(3); |
|
11641 |
||
11642 |
format %{ "CALL,runtime" %}
|
|
11643 |
ins_encode( enc_java_to_runtime_call(meth) ); |
|
11644 |
ins_pipe(pipe_class_call); |
|
11645 |
%} |
|
11646 |
||
11647 |
// Call Leaf |
|
11648 |
||
11649 |
// Used by postalloc expand of CallLeafDirect_Ex (mtctr). |
|
11650 |
instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
|
|
11651 |
effect(DEF dst, USE src); |
|
11652 |
||
11653 |
ins_num_consts(1); |
|
11654 |
||
11655 |
format %{ "MTCTR $src" %}
|
|
11656 |
size(4); |
|
11657 |
ins_encode( enc_leaf_call_mtctr(src) ); |
|
11658 |
ins_pipe(pipe_class_default); |
|
11659 |
%} |
|
11660 |
||
11661 |
// Used by postalloc expand of CallLeafDirect_Ex (actual call). |
|
11662 |
instruct CallLeafDirect(method meth) %{
|
|
11663 |
match(CallLeaf); // To get the data all the data fields we need ... |
|
11664 |
effect(USE meth); |
|
11665 |
predicate(false); // but never match. |
|
11666 |
||
11667 |
format %{ "BCTRL \t// leaf call $meth ==> " %}
|
|
11668 |
size(4); |
|
11669 |
ins_encode %{
|
|
11670 |
// TODO: PPC port $archOpcode(ppc64Opcode_bctrl); |
|
11671 |
__ bctrl(); |
|
11672 |
%} |
|
11673 |
ins_pipe(pipe_class_call); |
|
11674 |
%} |
|
11675 |
||
11676 |
// postalloc expand of CallLeafDirect. |
|
11677 |
// Load adress to call from TOC, then bl to it. |
|
11678 |
instruct CallLeafDirect_Ex(method meth) %{
|
|
11679 |
match(CallLeaf); |
|
11680 |
effect(USE meth); |
|
11681 |
ins_cost(CALL_COST); |
|
11682 |
||
11683 |
// Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, |
|
11684 |
// env for callee, C-toc. |
|
11685 |
ins_num_consts(3); |
|
11686 |
||
11687 |
format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
|
|
11688 |
postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); |
|
11689 |
%} |
|
11690 |
||
11691 |
// Call runtime without safepoint - same as CallLeaf. |
|
11692 |
// postalloc expand of CallLeafNoFPDirect. |
|
11693 |
// Load adress to call from TOC, then bl to it. |
|
11694 |
instruct CallLeafNoFPDirect_Ex(method meth) %{
|
|
11695 |
match(CallLeafNoFP); |
|
11696 |
effect(USE meth); |
|
11697 |
ins_cost(CALL_COST); |
|
11698 |
||
11699 |
// Enc_java_to_runtime_call needs up to 3 constants: call target, |
|
11700 |
// env for callee, C-toc. |
|
11701 |
ins_num_consts(3); |
|
11702 |
||
11703 |
format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
|
|
11704 |
postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); |
|
11705 |
%} |
|
11706 |
||
11707 |
// Tail Call; Jump from runtime stub to Java code. |
|
11708 |
// Also known as an 'interprocedural jump'. |
|
11709 |
// Target of jump will eventually return to caller. |
|
11710 |
// TailJump below removes the return address. |
|
11711 |
instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
|
|
11712 |
match(TailCall jump_target method_oop); |
|
11713 |
ins_cost(CALL_COST); |
|
11714 |
||
11715 |
format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
|
|
11716 |
"BCTR \t// tail call" %} |
|
11717 |
size(8); |
|
11718 |
ins_encode %{
|
|
11719 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11720 |
__ mtctr($jump_target$$Register); |
|
11721 |
__ bctr(); |
|
11722 |
%} |
|
11723 |
ins_pipe(pipe_class_call); |
|
11724 |
%} |
|
11725 |
||
11726 |
// Return Instruction |
|
11727 |
instruct Ret() %{
|
|
11728 |
match(Return); |
|
11729 |
format %{ "BLR \t// branch to link register" %}
|
|
11730 |
size(4); |
|
11731 |
ins_encode %{
|
|
11732 |
// TODO: PPC port $archOpcode(ppc64Opcode_blr); |
|
11733 |
// LR is restored in MachEpilogNode. Just do the RET here. |
|
11734 |
__ blr(); |
|
11735 |
%} |
|
11736 |
ins_pipe(pipe_class_default); |
|
11737 |
%} |
|
11738 |
||
11739 |
// Tail Jump; remove the return address; jump to target. |
|
11740 |
// TailCall above leaves the return address around. |
|
11741 |
// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). |
|
11742 |
// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a |
|
11743 |
// "restore" before this instruction (in Epilogue), we need to materialize it |
|
11744 |
// in %i0. |
|
11745 |
instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
|
|
11746 |
match(TailJump jump_target ex_oop); |
|
11747 |
ins_cost(CALL_COST); |
|
11748 |
||
11749 |
format %{ "LD R4_ARG2 = LR\n\t"
|
|
11750 |
"MTCTR $jump_target\n\t" |
|
11751 |
"BCTR \t// TailJump, exception oop: $ex_oop" %} |
|
11752 |
size(12); |
|
11753 |
ins_encode %{
|
|
11754 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11755 |
__ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); |
|
11756 |
__ mtctr($jump_target$$Register); |
|
11757 |
__ bctr(); |
|
11758 |
%} |
|
11759 |
ins_pipe(pipe_class_call); |
|
11760 |
%} |
|
11761 |
||
11762 |
// Create exception oop: created by stack-crawling runtime code. |
|
11763 |
// Created exception is now available to this handler, and is setup |
|
11764 |
// just prior to jumping to this handler. No code emitted. |
|
11765 |
instruct CreateException(rarg1RegP ex_oop) %{
|
|
11766 |
match(Set ex_oop (CreateEx)); |
|
11767 |
ins_cost(0); |
|
11768 |
||
11769 |
format %{ " -- \t// exception oop; no code emitted" %}
|
|
11770 |
size(0); |
|
11771 |
ins_encode( /*empty*/ ); |
|
11772 |
ins_pipe(pipe_class_default); |
|
11773 |
%} |
|
11774 |
||
11775 |
// Rethrow exception: The exception oop will come in the first |
|
11776 |
// argument position. Then JUMP (not call) to the rethrow stub code. |
|
11777 |
instruct RethrowException() %{
|
|
11778 |
match(Rethrow); |
|
11779 |
ins_cost(CALL_COST); |
|
11780 |
||
11781 |
format %{ "Jmp rethrow_stub" %}
|
|
11782 |
ins_encode %{
|
|
11783 |
// TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11784 |
cbuf.set_insts_mark(); |
|
11785 |
__ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); |
|
11786 |
%} |
|
11787 |
ins_pipe(pipe_class_call); |
|
11788 |
%} |
|
11789 |
||
11790 |
// Die now. |
|
11791 |
instruct ShouldNotReachHere() %{
|
|
11792 |
match(Halt); |
|
11793 |
ins_cost(CALL_COST); |
|
11794 |
||
11795 |
format %{ "ShouldNotReachHere" %}
|
|
11796 |
size(4); |
|
11797 |
ins_encode %{
|
|
11798 |
// TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
11799 |
__ trap_should_not_reach_here(); |
|
11800 |
%} |
|
11801 |
ins_pipe(pipe_class_default); |
|
11802 |
%} |
|
11803 |
||
11804 |
// This name is KNOWN by the ADLC and cannot be changed. The ADLC |
|
11805 |
// forces a 'TypeRawPtr::BOTTOM' output type for this guy. |
|
11806 |
// Get a DEF on threadRegP, no costs, no encoding, use |
|
11807 |
// 'ins_should_rematerialize(true)' to avoid spilling. |
|
11808 |
instruct tlsLoadP(threadRegP dst) %{
|
|
11809 |
match(Set dst (ThreadLocal)); |
|
11810 |
ins_cost(0); |
|
11811 |
||
11812 |
ins_should_rematerialize(true); |
|
11813 |
||
11814 |
format %{ " -- \t// $dst=Thread::current(), empty" %}
|
|
11815 |
size(0); |
|
11816 |
ins_encode( /*empty*/ ); |
|
11817 |
ins_pipe(pipe_class_empty); |
|
11818 |
%} |
|
11819 |
||
11820 |
//---Some PPC specific nodes--------------------------------------------------- |
|
11821 |
||
11822 |
// Stop a group. |
|
11823 |
instruct endGroup() %{
|
|
11824 |
ins_cost(0); |
|
11825 |
||
11826 |
ins_is_nop(true); |
|
11827 |
||
11828 |
format %{ "End Bundle (ori r1, r1, 0)" %}
|
|
11829 |
size(4); |
|
11830 |
ins_encode %{
|
|
11831 |
// TODO: PPC port $archOpcode(ppc64Opcode_endgroup); |
|
11832 |
__ endgroup(); |
|
11833 |
%} |
|
11834 |
ins_pipe(pipe_class_default); |
|
11835 |
%} |
|
11836 |
||
11837 |
// Nop instructions |
|
11838 |
||
11839 |
instruct fxNop() %{
|
|
11840 |
ins_cost(0); |
|
11841 |
||
11842 |
ins_is_nop(true); |
|
11843 |
||
11844 |
format %{ "fxNop" %}
|
|
11845 |
size(4); |
|
11846 |
ins_encode %{
|
|
11847 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11848 |
__ nop(); |
|
11849 |
%} |
|
11850 |
ins_pipe(pipe_class_default); |
|
11851 |
%} |
|
11852 |
||
11853 |
instruct fpNop0() %{
|
|
11854 |
ins_cost(0); |
|
11855 |
||
11856 |
ins_is_nop(true); |
|
11857 |
||
11858 |
format %{ "fpNop0" %}
|
|
11859 |
size(4); |
|
11860 |
ins_encode %{
|
|
11861 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11862 |
__ fpnop0(); |
|
11863 |
%} |
|
11864 |
ins_pipe(pipe_class_default); |
|
11865 |
%} |
|
11866 |
||
11867 |
instruct fpNop1() %{
|
|
11868 |
ins_cost(0); |
|
11869 |
||
11870 |
ins_is_nop(true); |
|
11871 |
||
11872 |
format %{ "fpNop1" %}
|
|
11873 |
size(4); |
|
11874 |
ins_encode %{
|
|
11875 |
// TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11876 |
__ fpnop1(); |
|
11877 |
%} |
|
11878 |
ins_pipe(pipe_class_default); |
|
11879 |
%} |
|
11880 |
||
11881 |
instruct brNop0() %{
|
|
11882 |
ins_cost(0); |
|
11883 |
size(4); |
|
11884 |
format %{ "brNop0" %}
|
|
11885 |
ins_encode %{
|
|
11886 |
// TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11887 |
__ brnop0(); |
|
11888 |
%} |
|
11889 |
ins_is_nop(true); |
|
11890 |
ins_pipe(pipe_class_default); |
|
11891 |
%} |
|
11892 |
||
11893 |
instruct brNop1() %{
|
|
11894 |
ins_cost(0); |
|
11895 |
||
11896 |
ins_is_nop(true); |
|
11897 |
||
11898 |
format %{ "brNop1" %}
|
|
11899 |
size(4); |
|
11900 |
ins_encode %{
|
|
11901 |
// TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11902 |
__ brnop1(); |
|
11903 |
%} |
|
11904 |
ins_pipe(pipe_class_default); |
|
11905 |
%} |
|
11906 |
||
11907 |
instruct brNop2() %{
|
|
11908 |
ins_cost(0); |
|
11909 |
||
11910 |
ins_is_nop(true); |
|
11911 |
||
11912 |
format %{ "brNop2" %}
|
|
11913 |
size(4); |
|
11914 |
ins_encode %{
|
|
11915 |
// TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11916 |
__ brnop2(); |
|
11917 |
%} |
|
11918 |
ins_pipe(pipe_class_default); |
|
11919 |
%} |
|
11920 |
||
11921 |
//----------PEEPHOLE RULES----------------------------------------------------- |
|
11922 |
// These must follow all instruction definitions as they use the names |
|
11923 |
// defined in the instructions definitions. |
|
11924 |
// |
|
11925 |
// peepmatch ( root_instr_name [preceeding_instruction]* ); |
|
11926 |
// |
|
11927 |
// peepconstraint %{
|
|
11928 |
// (instruction_number.operand_name relational_op instruction_number.operand_name |
|
11929 |
// [, ...] ); |
|
11930 |
// // instruction numbers are zero-based using left to right order in peepmatch |
|
11931 |
// |
|
11932 |
// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); |
|
11933 |
// // provide an instruction_number.operand_name for each operand that appears |
|
11934 |
// // in the replacement instruction's match rule |
|
11935 |
// |
|
11936 |
// ---------VM FLAGS--------------------------------------------------------- |
|
11937 |
// |
|
11938 |
// All peephole optimizations can be turned off using -XX:-OptoPeephole |
|
11939 |
// |
|
11940 |
// Each peephole rule is given an identifying number starting with zero and |
|
11941 |
// increasing by one in the order seen by the parser. An individual peephole |
|
11942 |
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# |
|
11943 |
// on the command-line. |
|
11944 |
// |
|
11945 |
// ---------CURRENT LIMITATIONS---------------------------------------------- |
|
11946 |
// |
|
11947 |
// Only match adjacent instructions in same basic block |
|
11948 |
// Only equality constraints |
|
11949 |
// Only constraints between operands, not (0.dest_reg == EAX_enc) |
|
11950 |
// Only one replacement instruction |
|
11951 |
// |
|
11952 |
// ---------EXAMPLE---------------------------------------------------------- |
|
11953 |
// |
|
11954 |
// // pertinent parts of existing instructions in architecture description |
|
11955 |
// instruct movI(eRegI dst, eRegI src) %{
|
|
11956 |
// match(Set dst (CopyI src)); |
|
11957 |
// %} |
|
11958 |
// |
|
11959 |
// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
|
|
11960 |
// match(Set dst (AddI dst src)); |
|
11961 |
// effect(KILL cr); |
|
11962 |
// %} |
|
11963 |
// |
|
11964 |
// // Change (inc mov) to lea |
|
11965 |
// peephole %{
|
|
11966 |
// // increment preceeded by register-register move |
|
11967 |
// peepmatch ( incI_eReg movI ); |
|
11968 |
// // require that the destination register of the increment |
|
11969 |
// // match the destination register of the move |
|
11970 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11971 |
// // construct a replacement instruction that sets |
|
11972 |
// // the destination to ( move's source register + one ) |
|
11973 |
// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
11974 |
// %} |
|
11975 |
// |
|
11976 |
// Implementation no longer uses movX instructions since |
|
11977 |
// machine-independent system no longer uses CopyX nodes. |
|
11978 |
// |
|
11979 |
// peephole %{
|
|
11980 |
// peepmatch ( incI_eReg movI ); |
|
11981 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11982 |
// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
11983 |
// %} |
|
11984 |
// |
|
11985 |
// peephole %{
|
|
11986 |
// peepmatch ( decI_eReg movI ); |
|
11987 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11988 |
// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
11989 |
// %} |
|
11990 |
// |
|
11991 |
// peephole %{
|
|
11992 |
// peepmatch ( addI_eReg_imm movI ); |
|
11993 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11994 |
// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
11995 |
// %} |
|
11996 |
// |
|
11997 |
// peephole %{
|
|
11998 |
// peepmatch ( addP_eReg_imm movP ); |
|
11999 |
// peepconstraint ( 0.dst == 1.dst ); |
|
12000 |
// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12001 |
// %} |
|
12002 |
||
12003 |
// // Change load of spilled value to only a spill |
|
12004 |
// instruct storeI(memory mem, eRegI src) %{
|
|
12005 |
// match(Set mem (StoreI mem src)); |
|
12006 |
// %} |
|
12007 |
// |
|
12008 |
// instruct loadI(eRegI dst, memory mem) %{
|
|
12009 |
// match(Set dst (LoadI mem)); |
|
12010 |
// %} |
|
12011 |
// |
|
12012 |
peephole %{
|
|
12013 |
peepmatch ( loadI storeI ); |
|
12014 |
peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); |
|
12015 |
peepreplace ( storeI( 1.mem 1.mem 1.src ) ); |
|
12016 |
%} |
|
12017 |
||
12018 |
peephole %{
|
|
12019 |
peepmatch ( loadL storeL ); |
|
12020 |
peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); |
|
12021 |
peepreplace ( storeL( 1.mem 1.mem 1.src ) ); |
|
12022 |
%} |
|
12023 |
||
12024 |
peephole %{
|
|
12025 |
peepmatch ( loadP storeP ); |
|
12026 |
peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); |
|
12027 |
peepreplace ( storeP( 1.dst 1.dst 1.src ) ); |
|
12028 |
%} |
|
12029 |
||
12030 |
//----------SMARTSPILL RULES--------------------------------------------------- |
|
12031 |
// These must follow all instruction definitions as they use the names |
|
12032 |
// defined in the instructions definitions. |