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/*
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* Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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* CA 95054 USA or visit www.sun.com if you need additional information or
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* have any questions.
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*
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*/
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class LoopTree;
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class MachCallNode;
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class MachSafePointNode;
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class Matcher;
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class PhaseCFG;
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class PhaseLive;
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class PhaseRegAlloc;
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class PhaseChaitin;
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#define OPTO_DEBUG_SPLIT_FREQ BLOCK_FREQUENCY(0.001)
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#define OPTO_LRG_HIGH_FREQ BLOCK_FREQUENCY(0.25)
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//------------------------------LRG--------------------------------------------
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// Live-RanGe structure.
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class LRG : public ResourceObj {
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public:
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enum { SPILL_REG=29999 }; // Register number of a spilled LRG
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double _cost; // 2 for loads/1 for stores times block freq
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double _area; // Sum of all simultaneously live values
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double score() const; // Compute score from cost and area
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double _maxfreq; // Maximum frequency of any def or use
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Node *_def; // Check for multi-def live ranges
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#ifndef PRODUCT
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GrowableArray<Node*>* _defs;
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#endif
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uint _risk_bias; // Index of LRG which we want to avoid color
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uint _copy_bias; // Index of LRG which we want to share color
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uint _next; // Index of next LRG in linked list
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uint _prev; // Index of prev LRG in linked list
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private:
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uint _reg; // Chosen register; undefined if mask is plural
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public:
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// Return chosen register for this LRG. Error if the LRG is not bound to
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// a single register.
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OptoReg::Name reg() const { return OptoReg::Name(_reg); }
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void set_reg( OptoReg::Name r ) { _reg = r; }
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private:
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uint _eff_degree; // Effective degree: Sum of neighbors _num_regs
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public:
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int degree() const { assert( _degree_valid, "" ); return _eff_degree; }
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// Degree starts not valid and any change to the IFG neighbor
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// set makes it not valid.
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void set_degree( uint degree ) { _eff_degree = degree; debug_only(_degree_valid = 1;) }
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// Made a change that hammered degree
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void invalid_degree() { debug_only(_degree_valid=0;) }
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// Incrementally modify degree. If it was correct, it should remain correct
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void inc_degree( uint mod ) { _eff_degree += mod; }
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// Compute the degree between 2 live ranges
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int compute_degree( LRG &l ) const;
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private:
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RegMask _mask; // Allowed registers for this LRG
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uint _mask_size; // cache of _mask.Size();
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public:
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int compute_mask_size() const { return _mask.is_AllStack() ? 65535 : _mask.Size(); }
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void set_mask_size( int size ) {
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assert((size == 65535) || (size == (int)_mask.Size()), "");
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_mask_size = size;
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debug_only(_msize_valid=1;)
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debug_only( if( _num_regs == 2 && !_fat_proj ) _mask.VerifyPairs(); )
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}
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void compute_set_mask_size() { set_mask_size(compute_mask_size()); }
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int mask_size() const { assert( _msize_valid, "mask size not valid" );
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return _mask_size; }
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// Get the last mask size computed, even if it does not match the
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// count of bits in the current mask.
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int get_invalid_mask_size() const { return _mask_size; }
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const RegMask &mask() const { return _mask; }
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void set_mask( const RegMask &rm ) { _mask = rm; debug_only(_msize_valid=0;)}
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void AND( const RegMask &rm ) { _mask.AND(rm); debug_only(_msize_valid=0;)}
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void SUBTRACT( const RegMask &rm ) { _mask.SUBTRACT(rm); debug_only(_msize_valid=0;)}
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void Clear() { _mask.Clear() ; debug_only(_msize_valid=1); _mask_size = 0; }
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void Set_All() { _mask.Set_All(); debug_only(_msize_valid=1); _mask_size = RegMask::CHUNK_SIZE; }
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void Insert( OptoReg::Name reg ) { _mask.Insert(reg); debug_only(_msize_valid=0;) }
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void Remove( OptoReg::Name reg ) { _mask.Remove(reg); debug_only(_msize_valid=0;) }
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void ClearToPairs() { _mask.ClearToPairs(); debug_only(_msize_valid=0;) }
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// Number of registers this live range uses when it colors
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private:
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uint8 _num_regs; // 2 for Longs and Doubles, 1 for all else
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// except _num_regs is kill count for fat_proj
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public:
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int num_regs() const { return _num_regs; }
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void set_num_regs( int reg ) { assert( _num_regs == reg || !_num_regs, "" ); _num_regs = reg; }
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private:
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// Number of physical registers this live range uses when it colors
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// Architecture and register-set dependent
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uint8 _reg_pressure;
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public:
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void set_reg_pressure(int i) { _reg_pressure = i; }
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int reg_pressure() const { return _reg_pressure; }
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// How much 'wiggle room' does this live range have?
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// How many color choices can it make (scaled by _num_regs)?
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int degrees_of_freedom() const { return mask_size() - _num_regs; }
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// Bound LRGs have ZERO degrees of freedom. We also count
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// must_spill as bound.
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bool is_bound () const { return _is_bound; }
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// Negative degrees-of-freedom; even with no neighbors this
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// live range must spill.
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bool not_free() const { return degrees_of_freedom() < 0; }
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// Is this live range of "low-degree"? Trivially colorable?
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bool lo_degree () const { return degree() <= degrees_of_freedom(); }
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// Is this live range just barely "low-degree"? Trivially colorable?
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bool just_lo_degree () const { return degree() == degrees_of_freedom(); }
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uint _is_oop:1, // Live-range holds an oop
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_is_float:1, // True if in float registers
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_was_spilled1:1, // True if prior spilling on def
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_was_spilled2:1, // True if twice prior spilling on def
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_is_bound:1, // live range starts life with no
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// degrees of freedom.
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_direct_conflict:1, // True if def and use registers in conflict
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_must_spill:1, // live range has lost all degrees of freedom
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// If _fat_proj is set, live range does NOT require aligned, adjacent
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// registers and has NO interferences.
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// If _fat_proj is clear, live range requires num_regs() to be a power of
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// 2, and it requires registers to form an aligned, adjacent set.
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_fat_proj:1, //
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_was_lo:1, // Was lo-degree prior to coalesce
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_msize_valid:1, // _mask_size cache valid
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_degree_valid:1, // _degree cache valid
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_has_copy:1, // Adjacent to some copy instruction
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_at_risk:1; // Simplify says this guy is at risk to spill
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// Alive if non-zero, dead if zero
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bool alive() const { return _def != NULL; }
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#ifndef PRODUCT
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void dump( ) const;
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#endif
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};
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//------------------------------LRG_List---------------------------------------
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// Map Node indices to Live RanGe indices.
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// Array lookup in the optimized case.
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class LRG_List : public ResourceObj {
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uint _cnt, _max;
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uint* _lidxs;
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ReallocMark _nesting; // assertion check for reallocations
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public:
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LRG_List( uint max );
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uint lookup( uint nidx ) const {
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return _lidxs[nidx];
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}
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uint operator[] (uint nidx) const { return lookup(nidx); }
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void map( uint nidx, uint lidx ) {
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assert( nidx < _cnt, "oob" );
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_lidxs[nidx] = lidx;
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}
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void extend( uint nidx, uint lidx );
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uint Size() const { return _cnt; }
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};
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//------------------------------IFG--------------------------------------------
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// InterFerence Graph
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// An undirected graph implementation. Created with a fixed number of
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// vertices. Edges can be added & tested. Vertices can be removed, then
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// added back later with all edges intact. Can add edges between one vertex
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// and a list of other vertices. Can union vertices (and their edges)
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// together. The IFG needs to be really really fast, and also fairly
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// abstract! It needs abstraction so I can fiddle with the implementation to
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// get even more speed.
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class PhaseIFG : public Phase {
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// Current implementation: a triangular adjacency list.
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// Array of adjacency-lists, indexed by live-range number
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IndexSet *_adjs;
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// Assertion bit for proper use of Squaring
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bool _is_square;
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// Live range structure goes here
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LRG *_lrgs; // Array of LRG structures
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public:
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// Largest live-range number
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uint _maxlrg;
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Arena *_arena;
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// Keep track of inserted and deleted Nodes
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VectorSet *_yanked;
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PhaseIFG( Arena *arena );
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void init( uint maxlrg );
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// Add edge between a and b. Returns true if actually addded.
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int add_edge( uint a, uint b );
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// Add edge between a and everything in the vector
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void add_vector( uint a, IndexSet *vec );
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// Test for edge existance
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int test_edge( uint a, uint b ) const;
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// Square-up matrix for faster Union
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void SquareUp();
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// Return number of LRG neighbors
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uint neighbor_cnt( uint a ) const { return _adjs[a].count(); }
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// Union edges of b into a on Squared-up matrix
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void Union( uint a, uint b );
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// Test for edge in Squared-up matrix
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int test_edge_sq( uint a, uint b ) const;
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// Yank a Node and all connected edges from the IFG. Be prepared to
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// re-insert the yanked Node in reverse order of yanking. Return a
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// list of neighbors (edges) yanked.
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IndexSet *remove_node( uint a );
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// Reinsert a yanked Node
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void re_insert( uint a );
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// Return set of neighbors
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IndexSet *neighbors( uint a ) const { return &_adjs[a]; }
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#ifndef PRODUCT
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// Dump the IFG
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void dump() const;
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void stats() const;
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void verify( const PhaseChaitin * ) const;
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#endif
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//--------------- Live Range Accessors
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LRG &lrgs(uint idx) const { assert(idx < _maxlrg, "oob"); return _lrgs[idx]; }
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// Compute and set effective degree. Might be folded into SquareUp().
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void Compute_Effective_Degree();
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// Compute effective degree as the sum of neighbors' _sizes.
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int effective_degree( uint lidx ) const;
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};
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// TEMPORARILY REPLACED WITH COMMAND LINE FLAG
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//// !!!!! Magic Constants need to move into ad file
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#ifdef SPARC
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//#define FLOAT_PRESSURE 30 /* SFLT_REG_mask.Size() - 1 */
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//#define INT_PRESSURE 23 /* NOTEMP_I_REG_mask.Size() - 1 */
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#define FLOAT_INCREMENT(regs) regs
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#else
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//#define FLOAT_PRESSURE 6
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//#define INT_PRESSURE 6
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#define FLOAT_INCREMENT(regs) 1
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#endif
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//------------------------------Chaitin----------------------------------------
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// Briggs-Chaitin style allocation, mostly.
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class PhaseChaitin : public PhaseRegAlloc {
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int _trip_cnt;
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int _alternate;
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uint _maxlrg; // Max live range number
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LRG &lrgs(uint idx) const { return _ifg->lrgs(idx); }
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PhaseLive *_live; // Liveness, used in the interference graph
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PhaseIFG *_ifg; // Interference graph (for original chunk)
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Node_List **_lrg_nodes; // Array of node; lists for lrgs which spill
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VectorSet _spilled_once; // Nodes that have been spilled
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VectorSet _spilled_twice; // Nodes that have been spilled twice
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LRG_List _names; // Map from Nodes to Live RanGes
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// Union-find map. Declared as a short for speed.
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// Indexed by live-range number, it returns the compacted live-range number
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LRG_List _uf_map;
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// Reset the Union-Find map to identity
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void reset_uf_map( uint maxlrg );
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// Remove the need for the Union-Find mapping
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void compress_uf_map_for_nodes( );
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// Combine the Live Range Indices for these 2 Nodes into a single live
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// range. Future requests for any Node in either live range will
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// return the live range index for the combined live range.
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void Union( const Node *src, const Node *dst );
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void new_lrg( const Node *x, uint lrg );
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// Compact live ranges, removing unused ones. Return new maxlrg.
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void compact();
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uint _lo_degree; // Head of lo-degree LRGs list
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uint _lo_stk_degree; // Head of lo-stk-degree LRGs list
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uint _hi_degree; // Head of hi-degree LRGs list
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uint _simplified; // Linked list head of simplified LRGs
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// Helper functions for Split()
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uint split_DEF( Node *def, Block *b, int loc, uint max, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx );
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uint split_USE( Node *def, Block *b, Node *use, uint useidx, uint max, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx );
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int clone_projs( Block *b, uint idx, Node *con, Node *copy, uint &maxlrg );
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Node *split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru );
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// True if lidx is used before any real register is def'd in the block
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bool prompt_use( Block *b, uint lidx );
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Node *get_spillcopy_wide( Node *def, Node *use, uint uidx );
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// Insert the spill at chosen location. Skip over any interveneing Proj's or
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// Phis. Skip over a CatchNode and projs, inserting in the fall-through block
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// instead. Update high-pressure indices. Create a new live range.
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void insert_proj( Block *b, uint i, Node *spill, uint maxlrg );
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bool is_high_pressure( Block *b, LRG *lrg, uint insidx );
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uint _oldphi; // Node index which separates pre-allocation nodes
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Block **_blks; // Array of blocks sorted by frequency for coalescing
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#ifndef PRODUCT
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bool _trace_spilling;
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#endif
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public:
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PhaseChaitin( uint unique, PhaseCFG &cfg, Matcher &matcher );
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~PhaseChaitin() {}
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// Convert a Node into a Live Range Index - a lidx
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uint Find( const Node *n ) {
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uint lidx = n2lidx(n);
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uint uf_lidx = _uf_map[lidx];
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return (uf_lidx == lidx) ? uf_lidx : Find_compress(n);
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}
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uint Find_const( uint lrg ) const;
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uint Find_const( const Node *n ) const;
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// Do all the real work of allocate
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void Register_Allocate();
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uint n2lidx( const Node *n ) const { return _names[n->_idx]; }
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#ifndef PRODUCT
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bool trace_spilling() const { return _trace_spilling; }
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#endif
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private:
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// De-SSA the world. Assign registers to Nodes. Use the same register for
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// all inputs to a PhiNode, effectively coalescing live ranges. Insert
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// copies as needed.
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void de_ssa();
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uint Find_compress( const Node *n );
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uint Find( uint lidx ) {
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uint uf_lidx = _uf_map[lidx];
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372 |
return (uf_lidx == lidx) ? uf_lidx : Find_compress(lidx);
|
|
373 |
}
|
|
374 |
uint Find_compress( uint lidx );
|
|
375 |
|
|
376 |
uint Find_id( const Node *n ) {
|
|
377 |
uint retval = n2lidx(n);
|
|
378 |
assert(retval == Find(n),"Invalid node to lidx mapping");
|
|
379 |
return retval;
|
|
380 |
}
|
|
381 |
|
|
382 |
// Add edge between reg and everything in the vector.
|
|
383 |
// Same as _ifg->add_vector(reg,live) EXCEPT use the RegMask
|
|
384 |
// information to trim the set of interferences. Return the
|
|
385 |
// count of edges added.
|
|
386 |
void interfere_with_live( uint reg, IndexSet *live );
|
|
387 |
// Count register pressure for asserts
|
|
388 |
uint count_int_pressure( IndexSet *liveout );
|
|
389 |
uint count_float_pressure( IndexSet *liveout );
|
|
390 |
|
|
391 |
// Build the interference graph using virtual registers only.
|
|
392 |
// Used for aggressive coalescing.
|
|
393 |
void build_ifg_virtual( );
|
|
394 |
|
|
395 |
// Build the interference graph using physical registers when available.
|
|
396 |
// That is, if 2 live ranges are simultaneously alive but in their
|
|
397 |
// acceptable register sets do not overlap, then they do not interfere.
|
|
398 |
uint build_ifg_physical( ResourceArea *a );
|
|
399 |
|
|
400 |
// Gather LiveRanGe information, including register masks and base pointer/
|
|
401 |
// derived pointer relationships.
|
|
402 |
void gather_lrg_masks( bool mod_cisc_masks );
|
|
403 |
|
|
404 |
// Force the bases of derived pointers to be alive at GC points.
|
|
405 |
bool stretch_base_pointer_live_ranges( ResourceArea *a );
|
|
406 |
// Helper to stretch above; recursively discover the base Node for
|
|
407 |
// a given derived Node. Easy for AddP-related machine nodes, but
|
|
408 |
// needs to be recursive for derived Phis.
|
|
409 |
Node *find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg );
|
|
410 |
|
|
411 |
// Set the was-lo-degree bit. Conservative coalescing should not change the
|
|
412 |
// colorability of the graph. If any live range was of low-degree before
|
|
413 |
// coalescing, it should Simplify. This call sets the was-lo-degree bit.
|
|
414 |
void set_was_low();
|
|
415 |
|
|
416 |
// Split live-ranges that must spill due to register conflicts (as opposed
|
|
417 |
// to capacity spills). Typically these are things def'd in a register
|
|
418 |
// and used on the stack or vice-versa.
|
|
419 |
void pre_spill();
|
|
420 |
|
|
421 |
// Init LRG caching of degree, numregs. Init lo_degree list.
|
|
422 |
void cache_lrg_info( );
|
|
423 |
|
|
424 |
// Simplify the IFG by removing LRGs of low degree with no copies
|
|
425 |
void Pre_Simplify();
|
|
426 |
|
|
427 |
// Simplify the IFG by removing LRGs of low degree
|
|
428 |
void Simplify();
|
|
429 |
|
|
430 |
// Select colors by re-inserting edges into the IFG.
|
|
431 |
// Return TRUE if any spills occured.
|
|
432 |
uint Select( );
|
|
433 |
// Helper function for select which allows biased coloring
|
|
434 |
OptoReg::Name choose_color( LRG &lrg, int chunk );
|
|
435 |
// Helper function which implements biasing heuristic
|
|
436 |
OptoReg::Name bias_color( LRG &lrg, int chunk );
|
|
437 |
|
|
438 |
// Split uncolorable live ranges
|
|
439 |
// Return new number of live ranges
|
|
440 |
uint Split( uint maxlrg );
|
|
441 |
|
|
442 |
// Copy 'was_spilled'-edness from one Node to another.
|
|
443 |
void copy_was_spilled( Node *src, Node *dst );
|
|
444 |
// Set the 'spilled_once' or 'spilled_twice' flag on a node.
|
|
445 |
void set_was_spilled( Node *n );
|
|
446 |
|
|
447 |
// Convert ideal spill-nodes into machine loads & stores
|
|
448 |
// Set C->failing when fixup spills could not complete, node limit exceeded.
|
|
449 |
void fixup_spills();
|
|
450 |
|
|
451 |
// Post-Allocation peephole copy removal
|
|
452 |
void post_allocate_copy_removal();
|
|
453 |
Node *skip_copies( Node *c );
|
|
454 |
int yank_if_dead( Node *old, Block *current_block, Node_List *value, Node_List *regnd );
|
|
455 |
int elide_copy( Node *n, int k, Block *current_block, Node_List &value, Node_List ®nd, bool can_change_regs );
|
|
456 |
int use_prior_register( Node *copy, uint idx, Node *def, Block *current_block, Node_List &value, Node_List ®nd );
|
|
457 |
bool may_be_copy_of_callee( Node *def ) const;
|
|
458 |
|
|
459 |
// If nreg already contains the same constant as val then eliminate it
|
|
460 |
bool eliminate_copy_of_constant(Node* val, Block *current_block, Node_List& value, Node_List ®nd,
|
|
461 |
OptoReg::Name nreg, OptoReg::Name nreg2);
|
|
462 |
// Extend the node to LRG mapping
|
|
463 |
void add_reference( const Node *node, const Node *old_node);
|
|
464 |
|
|
465 |
private:
|
|
466 |
|
|
467 |
static int _final_loads, _final_stores, _final_copies, _final_memoves;
|
|
468 |
static double _final_load_cost, _final_store_cost, _final_copy_cost, _final_memove_cost;
|
|
469 |
static int _conserv_coalesce, _conserv_coalesce_pair;
|
|
470 |
static int _conserv_coalesce_trie, _conserv_coalesce_quad;
|
|
471 |
static int _post_alloc;
|
|
472 |
static int _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce;
|
|
473 |
static int _used_cisc_instructions, _unused_cisc_instructions;
|
|
474 |
static int _allocator_attempts, _allocator_successes;
|
|
475 |
|
|
476 |
#ifndef PRODUCT
|
|
477 |
static uint _high_pressure, _low_pressure;
|
|
478 |
|
|
479 |
void dump() const;
|
|
480 |
void dump( const Node *n ) const;
|
|
481 |
void dump( const Block * b ) const;
|
|
482 |
void dump_degree_lists() const;
|
|
483 |
void dump_simplified() const;
|
|
484 |
void dump_lrg( uint lidx ) const;
|
|
485 |
void dump_bb( uint pre_order ) const;
|
|
486 |
|
|
487 |
// Verify that base pointers and derived pointers are still sane
|
|
488 |
void verify_base_ptrs( ResourceArea *a ) const;
|
|
489 |
|
|
490 |
void dump_for_spill_split_recycle() const;
|
|
491 |
|
|
492 |
public:
|
|
493 |
void dump_frame() const;
|
|
494 |
char *dump_register( const Node *n, char *buf ) const;
|
|
495 |
private:
|
|
496 |
static void print_chaitin_statistics();
|
|
497 |
#endif
|
|
498 |
friend class PhaseCoalesce;
|
|
499 |
friend class PhaseAggressiveCoalesce;
|
|
500 |
friend class PhaseConservativeCoalesce;
|
|
501 |
};
|