1
|
1 |
/*
|
|
2 |
* Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
|
|
3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
|
4 |
*
|
|
5 |
* This code is free software; you can redistribute it and/or modify it
|
|
6 |
* under the terms of the GNU General Public License version 2 only, as
|
|
7 |
* published by the Free Software Foundation.
|
|
8 |
*
|
|
9 |
* This code is distributed in the hope that it will be useful, but WITHOUT
|
|
10 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
11 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
12 |
* version 2 for more details (a copy is included in the LICENSE file that
|
|
13 |
* accompanied this code).
|
|
14 |
*
|
|
15 |
* You should have received a copy of the GNU General Public License version
|
|
16 |
* 2 along with this work; if not, write to the Free Software Foundation,
|
|
17 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
|
18 |
*
|
|
19 |
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
|
|
20 |
* CA 95054 USA or visit www.sun.com if you need additional information or
|
|
21 |
* have any questions.
|
|
22 |
*
|
|
23 |
*/
|
|
24 |
|
|
25 |
#include "incls/_precompiled.incl"
|
|
26 |
#include "incls/_chaitin.cpp.incl"
|
|
27 |
|
|
28 |
//=============================================================================
|
|
29 |
|
|
30 |
#ifndef PRODUCT
|
|
31 |
void LRG::dump( ) const {
|
|
32 |
ttyLocker ttyl;
|
|
33 |
tty->print("%d ",num_regs());
|
|
34 |
_mask.dump();
|
|
35 |
if( _msize_valid ) {
|
|
36 |
if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
|
|
37 |
else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
|
|
38 |
} else {
|
|
39 |
tty->print(", #?(%d) ",_mask.Size());
|
|
40 |
}
|
|
41 |
|
|
42 |
tty->print("EffDeg: ");
|
|
43 |
if( _degree_valid ) tty->print( "%d ", _eff_degree );
|
|
44 |
else tty->print("? ");
|
|
45 |
|
|
46 |
if( _def == NodeSentinel ) {
|
|
47 |
tty->print("MultiDef ");
|
|
48 |
if (_defs != NULL) {
|
|
49 |
tty->print("(");
|
|
50 |
for (int i = 0; i < _defs->length(); i++) {
|
|
51 |
tty->print("N%d ", _defs->at(i)->_idx);
|
|
52 |
}
|
|
53 |
tty->print(") ");
|
|
54 |
}
|
|
55 |
}
|
|
56 |
else if( _def == 0 ) tty->print("Dead ");
|
|
57 |
else tty->print("Def: N%d ",_def->_idx);
|
|
58 |
|
|
59 |
tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
|
|
60 |
// Flags
|
|
61 |
if( _is_oop ) tty->print("Oop ");
|
|
62 |
if( _is_float ) tty->print("Float ");
|
|
63 |
if( _was_spilled1 ) tty->print("Spilled ");
|
|
64 |
if( _was_spilled2 ) tty->print("Spilled2 ");
|
|
65 |
if( _direct_conflict ) tty->print("Direct_conflict ");
|
|
66 |
if( _fat_proj ) tty->print("Fat ");
|
|
67 |
if( _was_lo ) tty->print("Lo ");
|
|
68 |
if( _has_copy ) tty->print("Copy ");
|
|
69 |
if( _at_risk ) tty->print("Risk ");
|
|
70 |
|
|
71 |
if( _must_spill ) tty->print("Must_spill ");
|
|
72 |
if( _is_bound ) tty->print("Bound ");
|
|
73 |
if( _msize_valid ) {
|
|
74 |
if( _degree_valid && lo_degree() ) tty->print("Trivial ");
|
|
75 |
}
|
|
76 |
|
|
77 |
tty->cr();
|
|
78 |
}
|
|
79 |
#endif
|
|
80 |
|
|
81 |
//------------------------------score------------------------------------------
|
|
82 |
// Compute score from cost and area. Low score is best to spill.
|
|
83 |
static double raw_score( double cost, double area ) {
|
|
84 |
return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
|
|
85 |
}
|
|
86 |
|
|
87 |
double LRG::score() const {
|
|
88 |
// Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
|
|
89 |
// Bigger area lowers score, encourages spilling this live range.
|
|
90 |
// Bigger cost raise score, prevents spilling this live range.
|
|
91 |
// (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
|
|
92 |
// to turn a divide by a constant into a multiply by the reciprical).
|
|
93 |
double score = raw_score( _cost, _area);
|
|
94 |
|
|
95 |
// Account for area. Basically, LRGs covering large areas are better
|
|
96 |
// to spill because more other LRGs get freed up.
|
|
97 |
if( _area == 0.0 ) // No area? Then no progress to spill
|
|
98 |
return 1e35;
|
|
99 |
|
|
100 |
if( _was_spilled2 ) // If spilled once before, we are unlikely
|
|
101 |
return score + 1e30; // to make progress again.
|
|
102 |
|
|
103 |
if( _cost >= _area*3.0 ) // Tiny area relative to cost
|
|
104 |
return score + 1e17; // Probably no progress to spill
|
|
105 |
|
|
106 |
if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
|
|
107 |
return score + 1e10; // Likely no progress to spill
|
|
108 |
|
|
109 |
return score;
|
|
110 |
}
|
|
111 |
|
|
112 |
//------------------------------LRG_List---------------------------------------
|
|
113 |
LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
|
|
114 |
memset( _lidxs, 0, sizeof(uint)*max );
|
|
115 |
}
|
|
116 |
|
|
117 |
void LRG_List::extend( uint nidx, uint lidx ) {
|
|
118 |
_nesting.check();
|
|
119 |
if( nidx >= _max ) {
|
|
120 |
uint size = 16;
|
|
121 |
while( size <= nidx ) size <<=1;
|
|
122 |
_lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );
|
|
123 |
_max = size;
|
|
124 |
}
|
|
125 |
while( _cnt <= nidx )
|
|
126 |
_lidxs[_cnt++] = 0;
|
|
127 |
_lidxs[nidx] = lidx;
|
|
128 |
}
|
|
129 |
|
|
130 |
#define NUMBUCKS 3
|
|
131 |
|
|
132 |
//------------------------------Chaitin----------------------------------------
|
|
133 |
PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
|
|
134 |
: PhaseRegAlloc(unique, cfg, matcher,
|
|
135 |
#ifndef PRODUCT
|
|
136 |
print_chaitin_statistics
|
|
137 |
#else
|
|
138 |
NULL
|
|
139 |
#endif
|
|
140 |
),
|
|
141 |
_names(unique), _uf_map(unique),
|
|
142 |
_maxlrg(0), _live(0),
|
|
143 |
_spilled_once(Thread::current()->resource_area()),
|
|
144 |
_spilled_twice(Thread::current()->resource_area()),
|
|
145 |
_lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0),
|
|
146 |
_oldphi(unique)
|
|
147 |
#ifndef PRODUCT
|
|
148 |
, _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
|
|
149 |
#endif
|
|
150 |
{
|
|
151 |
NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
|
|
152 |
uint i,j;
|
|
153 |
// Build a list of basic blocks, sorted by frequency
|
|
154 |
_blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
|
|
155 |
// Experiment with sorting strategies to speed compilation
|
|
156 |
double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
|
|
157 |
Block **buckets[NUMBUCKS]; // Array of buckets
|
|
158 |
uint buckcnt[NUMBUCKS]; // Array of bucket counters
|
|
159 |
double buckval[NUMBUCKS]; // Array of bucket value cutoffs
|
|
160 |
for( i = 0; i < NUMBUCKS; i++ ) {
|
|
161 |
buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
|
|
162 |
buckcnt[i] = 0;
|
|
163 |
// Bump by three orders of magnitude each time
|
|
164 |
cutoff *= 0.001;
|
|
165 |
buckval[i] = cutoff;
|
|
166 |
for( j = 0; j < _cfg._num_blocks; j++ ) {
|
|
167 |
buckets[i][j] = NULL;
|
|
168 |
}
|
|
169 |
}
|
|
170 |
// Sort blocks into buckets
|
|
171 |
for( i = 0; i < _cfg._num_blocks; i++ ) {
|
|
172 |
for( j = 0; j < NUMBUCKS; j++ ) {
|
|
173 |
if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) {
|
|
174 |
// Assign block to end of list for appropriate bucket
|
|
175 |
buckets[j][buckcnt[j]++] = _cfg._blocks[i];
|
|
176 |
break; // kick out of inner loop
|
|
177 |
}
|
|
178 |
}
|
|
179 |
}
|
|
180 |
// Dump buckets into final block array
|
|
181 |
uint blkcnt = 0;
|
|
182 |
for( i = 0; i < NUMBUCKS; i++ ) {
|
|
183 |
for( j = 0; j < buckcnt[i]; j++ ) {
|
|
184 |
_blks[blkcnt++] = buckets[i][j];
|
|
185 |
}
|
|
186 |
}
|
|
187 |
|
|
188 |
assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
|
|
189 |
}
|
|
190 |
|
|
191 |
void PhaseChaitin::Register_Allocate() {
|
|
192 |
|
|
193 |
// Above the OLD FP (and in registers) are the incoming arguments. Stack
|
|
194 |
// slots in this area are called "arg_slots". Above the NEW FP (and in
|
|
195 |
// registers) is the outgoing argument area; above that is the spill/temp
|
|
196 |
// area. These are all "frame_slots". Arg_slots start at the zero
|
|
197 |
// stack_slots and count up to the known arg_size. Frame_slots start at
|
|
198 |
// the stack_slot #arg_size and go up. After allocation I map stack
|
|
199 |
// slots to actual offsets. Stack-slots in the arg_slot area are biased
|
|
200 |
// by the frame_size; stack-slots in the frame_slot area are biased by 0.
|
|
201 |
|
|
202 |
_trip_cnt = 0;
|
|
203 |
_alternate = 0;
|
|
204 |
_matcher._allocation_started = true;
|
|
205 |
|
|
206 |
ResourceArea live_arena; // Arena for liveness & IFG info
|
|
207 |
ResourceMark rm(&live_arena);
|
|
208 |
|
|
209 |
// Need live-ness for the IFG; need the IFG for coalescing. If the
|
|
210 |
// liveness is JUST for coalescing, then I can get some mileage by renaming
|
|
211 |
// all copy-related live ranges low and then using the max copy-related
|
|
212 |
// live range as a cut-off for LIVE and the IFG. In other words, I can
|
|
213 |
// build a subset of LIVE and IFG just for copies.
|
|
214 |
PhaseLive live(_cfg,_names,&live_arena);
|
|
215 |
|
|
216 |
// Need IFG for coalescing and coloring
|
|
217 |
PhaseIFG ifg( &live_arena );
|
|
218 |
_ifg = &ifg;
|
|
219 |
|
|
220 |
if (C->unique() > _names.Size()) _names.extend(C->unique()-1, 0);
|
|
221 |
|
|
222 |
// Come out of SSA world to the Named world. Assign (virtual) registers to
|
|
223 |
// Nodes. Use the same register for all inputs and the output of PhiNodes
|
|
224 |
// - effectively ending SSA form. This requires either coalescing live
|
|
225 |
// ranges or inserting copies. For the moment, we insert "virtual copies"
|
|
226 |
// - we pretend there is a copy prior to each Phi in predecessor blocks.
|
|
227 |
// We will attempt to coalesce such "virtual copies" before we manifest
|
|
228 |
// them for real.
|
|
229 |
de_ssa();
|
|
230 |
|
|
231 |
{
|
|
232 |
NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
|
|
233 |
_live = NULL; // Mark live as being not available
|
|
234 |
rm.reset_to_mark(); // Reclaim working storage
|
|
235 |
IndexSet::reset_memory(C, &live_arena);
|
|
236 |
ifg.init(_maxlrg); // Empty IFG
|
|
237 |
gather_lrg_masks( false ); // Collect LRG masks
|
|
238 |
live.compute( _maxlrg ); // Compute liveness
|
|
239 |
_live = &live; // Mark LIVE as being available
|
|
240 |
}
|
|
241 |
|
|
242 |
// Base pointers are currently "used" by instructions which define new
|
|
243 |
// derived pointers. This makes base pointers live up to the where the
|
|
244 |
// derived pointer is made, but not beyond. Really, they need to be live
|
|
245 |
// across any GC point where the derived value is live. So this code looks
|
|
246 |
// at all the GC points, and "stretches" the live range of any base pointer
|
|
247 |
// to the GC point.
|
|
248 |
if( stretch_base_pointer_live_ranges(&live_arena) ) {
|
|
249 |
NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); )
|
|
250 |
// Since some live range stretched, I need to recompute live
|
|
251 |
_live = NULL;
|
|
252 |
rm.reset_to_mark(); // Reclaim working storage
|
|
253 |
IndexSet::reset_memory(C, &live_arena);
|
|
254 |
ifg.init(_maxlrg);
|
|
255 |
gather_lrg_masks( false );
|
|
256 |
live.compute( _maxlrg );
|
|
257 |
_live = &live;
|
|
258 |
}
|
|
259 |
// Create the interference graph using virtual copies
|
|
260 |
build_ifg_virtual( ); // Include stack slots this time
|
|
261 |
|
|
262 |
// Aggressive (but pessimistic) copy coalescing.
|
|
263 |
// This pass works on virtual copies. Any virtual copies which are not
|
|
264 |
// coalesced get manifested as actual copies
|
|
265 |
{
|
|
266 |
// The IFG is/was triangular. I am 'squaring it up' so Union can run
|
|
267 |
// faster. Union requires a 'for all' operation which is slow on the
|
|
268 |
// triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
|
|
269 |
// meaning I can visit all the Nodes neighbors less than a Node in time
|
|
270 |
// O(# of neighbors), but I have to visit all the Nodes greater than a
|
|
271 |
// given Node and search them for an instance, i.e., time O(#MaxLRG)).
|
|
272 |
_ifg->SquareUp();
|
|
273 |
|
|
274 |
PhaseAggressiveCoalesce coalesce( *this );
|
|
275 |
coalesce.coalesce_driver( );
|
|
276 |
// Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
|
|
277 |
// not match the Phi itself, insert a copy.
|
|
278 |
coalesce.insert_copies(_matcher);
|
|
279 |
}
|
|
280 |
|
|
281 |
// After aggressive coalesce, attempt a first cut at coloring.
|
|
282 |
// To color, we need the IFG and for that we need LIVE.
|
|
283 |
{
|
|
284 |
NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
|
|
285 |
_live = NULL;
|
|
286 |
rm.reset_to_mark(); // Reclaim working storage
|
|
287 |
IndexSet::reset_memory(C, &live_arena);
|
|
288 |
ifg.init(_maxlrg);
|
|
289 |
gather_lrg_masks( true );
|
|
290 |
live.compute( _maxlrg );
|
|
291 |
_live = &live;
|
|
292 |
}
|
|
293 |
|
|
294 |
// Build physical interference graph
|
|
295 |
uint must_spill = 0;
|
|
296 |
must_spill = build_ifg_physical( &live_arena );
|
|
297 |
// If we have a guaranteed spill, might as well spill now
|
|
298 |
if( must_spill ) {
|
|
299 |
if( !_maxlrg ) return;
|
|
300 |
// Bail out if unique gets too large (ie - unique > MaxNodeLimit)
|
|
301 |
C->check_node_count(10*must_spill, "out of nodes before split");
|
|
302 |
if (C->failing()) return;
|
|
303 |
_maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
|
|
304 |
// Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
|
|
305 |
// or we failed to split
|
|
306 |
C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
|
|
307 |
if (C->failing()) return;
|
|
308 |
|
|
309 |
#ifdef ASSERT
|
|
310 |
if( VerifyOpto ) {
|
|
311 |
_cfg.verify();
|
|
312 |
verify_base_ptrs(&live_arena);
|
|
313 |
}
|
|
314 |
#endif
|
|
315 |
NOT_PRODUCT( C->verify_graph_edges(); )
|
|
316 |
|
|
317 |
compact(); // Compact LRGs; return new lower max lrg
|
|
318 |
|
|
319 |
{
|
|
320 |
NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
|
|
321 |
_live = NULL;
|
|
322 |
rm.reset_to_mark(); // Reclaim working storage
|
|
323 |
IndexSet::reset_memory(C, &live_arena);
|
|
324 |
ifg.init(_maxlrg); // Build a new interference graph
|
|
325 |
gather_lrg_masks( true ); // Collect intersect mask
|
|
326 |
live.compute( _maxlrg ); // Compute LIVE
|
|
327 |
_live = &live;
|
|
328 |
}
|
|
329 |
build_ifg_physical( &live_arena );
|
|
330 |
_ifg->SquareUp();
|
|
331 |
_ifg->Compute_Effective_Degree();
|
|
332 |
// Only do conservative coalescing if requested
|
|
333 |
if( OptoCoalesce ) {
|
|
334 |
// Conservative (and pessimistic) copy coalescing of those spills
|
|
335 |
PhaseConservativeCoalesce coalesce( *this );
|
|
336 |
// If max live ranges greater than cutoff, don't color the stack.
|
|
337 |
// This cutoff can be larger than below since it is only done once.
|
|
338 |
coalesce.coalesce_driver( );
|
|
339 |
}
|
|
340 |
compress_uf_map_for_nodes();
|
|
341 |
|
|
342 |
#ifdef ASSERT
|
|
343 |
if( VerifyOpto ) _ifg->verify(this);
|
|
344 |
#endif
|
|
345 |
} else {
|
|
346 |
ifg.SquareUp();
|
|
347 |
ifg.Compute_Effective_Degree();
|
|
348 |
#ifdef ASSERT
|
|
349 |
set_was_low();
|
|
350 |
#endif
|
|
351 |
}
|
|
352 |
|
|
353 |
// Prepare for Simplify & Select
|
|
354 |
cache_lrg_info(); // Count degree of LRGs
|
|
355 |
|
|
356 |
// Simplify the InterFerence Graph by removing LRGs of low degree.
|
|
357 |
// LRGs of low degree are trivially colorable.
|
|
358 |
Simplify();
|
|
359 |
|
|
360 |
// Select colors by re-inserting LRGs back into the IFG in reverse order.
|
|
361 |
// Return whether or not something spills.
|
|
362 |
uint spills = Select( );
|
|
363 |
|
|
364 |
// If we spill, split and recycle the entire thing
|
|
365 |
while( spills ) {
|
|
366 |
if( _trip_cnt++ > 24 ) {
|
|
367 |
DEBUG_ONLY( dump_for_spill_split_recycle(); )
|
|
368 |
if( _trip_cnt > 27 ) {
|
|
369 |
C->record_method_not_compilable("failed spill-split-recycle sanity check");
|
|
370 |
return;
|
|
371 |
}
|
|
372 |
}
|
|
373 |
|
|
374 |
if( !_maxlrg ) return;
|
|
375 |
_maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
|
|
376 |
// Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
|
|
377 |
C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split");
|
|
378 |
if (C->failing()) return;
|
|
379 |
#ifdef ASSERT
|
|
380 |
if( VerifyOpto ) {
|
|
381 |
_cfg.verify();
|
|
382 |
verify_base_ptrs(&live_arena);
|
|
383 |
}
|
|
384 |
#endif
|
|
385 |
|
|
386 |
compact(); // Compact LRGs; return new lower max lrg
|
|
387 |
|
|
388 |
// Nuke the live-ness and interference graph and LiveRanGe info
|
|
389 |
{
|
|
390 |
NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
|
|
391 |
_live = NULL;
|
|
392 |
rm.reset_to_mark(); // Reclaim working storage
|
|
393 |
IndexSet::reset_memory(C, &live_arena);
|
|
394 |
ifg.init(_maxlrg);
|
|
395 |
|
|
396 |
// Create LiveRanGe array.
|
|
397 |
// Intersect register masks for all USEs and DEFs
|
|
398 |
gather_lrg_masks( true );
|
|
399 |
live.compute( _maxlrg );
|
|
400 |
_live = &live;
|
|
401 |
}
|
|
402 |
must_spill = build_ifg_physical( &live_arena );
|
|
403 |
_ifg->SquareUp();
|
|
404 |
_ifg->Compute_Effective_Degree();
|
|
405 |
|
|
406 |
// Only do conservative coalescing if requested
|
|
407 |
if( OptoCoalesce ) {
|
|
408 |
// Conservative (and pessimistic) copy coalescing
|
|
409 |
PhaseConservativeCoalesce coalesce( *this );
|
|
410 |
// Check for few live ranges determines how aggressive coalesce is.
|
|
411 |
coalesce.coalesce_driver( );
|
|
412 |
}
|
|
413 |
compress_uf_map_for_nodes();
|
|
414 |
#ifdef ASSERT
|
|
415 |
if( VerifyOpto ) _ifg->verify(this);
|
|
416 |
#endif
|
|
417 |
cache_lrg_info(); // Count degree of LRGs
|
|
418 |
|
|
419 |
// Simplify the InterFerence Graph by removing LRGs of low degree.
|
|
420 |
// LRGs of low degree are trivially colorable.
|
|
421 |
Simplify();
|
|
422 |
|
|
423 |
// Select colors by re-inserting LRGs back into the IFG in reverse order.
|
|
424 |
// Return whether or not something spills.
|
|
425 |
spills = Select( );
|
|
426 |
}
|
|
427 |
|
|
428 |
// Count number of Simplify-Select trips per coloring success.
|
|
429 |
_allocator_attempts += _trip_cnt + 1;
|
|
430 |
_allocator_successes += 1;
|
|
431 |
|
|
432 |
// Peephole remove copies
|
|
433 |
post_allocate_copy_removal();
|
|
434 |
|
|
435 |
// max_reg is past the largest *register* used.
|
|
436 |
// Convert that to a frame_slot number.
|
|
437 |
if( _max_reg <= _matcher._new_SP )
|
|
438 |
_framesize = C->out_preserve_stack_slots();
|
|
439 |
else _framesize = _max_reg -_matcher._new_SP;
|
|
440 |
assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
|
|
441 |
|
|
442 |
// This frame must preserve the required fp alignment
|
|
443 |
const int stack_alignment_in_words = Matcher::stack_alignment_in_slots();
|
|
444 |
if (stack_alignment_in_words > 0)
|
|
445 |
_framesize = round_to(_framesize, Matcher::stack_alignment_in_bytes());
|
|
446 |
assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
|
|
447 |
#ifndef PRODUCT
|
|
448 |
_total_framesize += _framesize;
|
|
449 |
if( (int)_framesize > _max_framesize )
|
|
450 |
_max_framesize = _framesize;
|
|
451 |
#endif
|
|
452 |
|
|
453 |
// Convert CISC spills
|
|
454 |
fixup_spills();
|
|
455 |
|
|
456 |
// Log regalloc results
|
|
457 |
CompileLog* log = Compile::current()->log();
|
|
458 |
if (log != NULL) {
|
|
459 |
log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
|
|
460 |
}
|
|
461 |
|
|
462 |
if (C->failing()) return;
|
|
463 |
|
|
464 |
NOT_PRODUCT( C->verify_graph_edges(); )
|
|
465 |
|
|
466 |
// Move important info out of the live_arena to longer lasting storage.
|
|
467 |
alloc_node_regs(_names.Size());
|
|
468 |
for( uint i=0; i < _names.Size(); i++ ) {
|
|
469 |
if( _names[i] ) { // Live range associated with Node?
|
|
470 |
LRG &lrg = lrgs( _names[i] );
|
|
471 |
if( lrg.num_regs() == 1 ) {
|
|
472 |
_node_regs[i].set1( lrg.reg() );
|
|
473 |
} else { // Must be a register-pair
|
|
474 |
if( !lrg._fat_proj ) { // Must be aligned adjacent register pair
|
|
475 |
// Live ranges record the highest register in their mask.
|
|
476 |
// We want the low register for the AD file writer's convenience.
|
|
477 |
_node_regs[i].set2( OptoReg::add(lrg.reg(),-1) );
|
|
478 |
} else { // Misaligned; extract 2 bits
|
|
479 |
OptoReg::Name hi = lrg.reg(); // Get hi register
|
|
480 |
lrg.Remove(hi); // Yank from mask
|
|
481 |
int lo = lrg.mask().find_first_elem(); // Find lo
|
|
482 |
_node_regs[i].set_pair( hi, lo );
|
|
483 |
}
|
|
484 |
}
|
|
485 |
if( lrg._is_oop ) _node_oops.set(i);
|
|
486 |
} else {
|
|
487 |
_node_regs[i].set_bad();
|
|
488 |
}
|
|
489 |
}
|
|
490 |
|
|
491 |
// Done!
|
|
492 |
_live = NULL;
|
|
493 |
_ifg = NULL;
|
|
494 |
C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
|
|
495 |
}
|
|
496 |
|
|
497 |
//------------------------------de_ssa-----------------------------------------
|
|
498 |
void PhaseChaitin::de_ssa() {
|
|
499 |
// Set initial Names for all Nodes. Most Nodes get the virtual register
|
|
500 |
// number. A few get the ZERO live range number. These do not
|
|
501 |
// get allocated, but instead rely on correct scheduling to ensure that
|
|
502 |
// only one instance is simultaneously live at a time.
|
|
503 |
uint lr_counter = 1;
|
|
504 |
for( uint i = 0; i < _cfg._num_blocks; i++ ) {
|
|
505 |
Block *b = _cfg._blocks[i];
|
|
506 |
uint cnt = b->_nodes.size();
|
|
507 |
|
|
508 |
// Handle all the normal Nodes in the block
|
|
509 |
for( uint j = 0; j < cnt; j++ ) {
|
|
510 |
Node *n = b->_nodes[j];
|
|
511 |
// Pre-color to the zero live range, or pick virtual register
|
|
512 |
const RegMask &rm = n->out_RegMask();
|
|
513 |
_names.map( n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0 );
|
|
514 |
}
|
|
515 |
}
|
|
516 |
// Reset the Union-Find mapping to be identity
|
|
517 |
reset_uf_map(lr_counter);
|
|
518 |
}
|
|
519 |
|
|
520 |
|
|
521 |
//------------------------------gather_lrg_masks-------------------------------
|
|
522 |
// Gather LiveRanGe information, including register masks. Modification of
|
|
523 |
// cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
|
|
524 |
void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
|
|
525 |
|
|
526 |
// Nail down the frame pointer live range
|
|
527 |
uint fp_lrg = n2lidx(_cfg._root->in(1)->in(TypeFunc::FramePtr));
|
|
528 |
lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
|
|
529 |
|
|
530 |
// For all blocks
|
|
531 |
for( uint i = 0; i < _cfg._num_blocks; i++ ) {
|
|
532 |
Block *b = _cfg._blocks[i];
|
|
533 |
|
|
534 |
// For all instructions
|
|
535 |
for( uint j = 1; j < b->_nodes.size(); j++ ) {
|
|
536 |
Node *n = b->_nodes[j];
|
|
537 |
uint input_edge_start =1; // Skip control most nodes
|
|
538 |
if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
|
|
539 |
uint idx = n->is_Copy();
|
|
540 |
|
|
541 |
// Get virtual register number, same as LiveRanGe index
|
|
542 |
uint vreg = n2lidx(n);
|
|
543 |
LRG &lrg = lrgs(vreg);
|
|
544 |
if( vreg ) { // No vreg means un-allocable (e.g. memory)
|
|
545 |
|
|
546 |
// Collect has-copy bit
|
|
547 |
if( idx ) {
|
|
548 |
lrg._has_copy = 1;
|
|
549 |
uint clidx = n2lidx(n->in(idx));
|
|
550 |
LRG ©_src = lrgs(clidx);
|
|
551 |
copy_src._has_copy = 1;
|
|
552 |
}
|
|
553 |
|
|
554 |
// Check for float-vs-int live range (used in register-pressure
|
|
555 |
// calculations)
|
|
556 |
const Type *n_type = n->bottom_type();
|
|
557 |
if( n_type->is_floatingpoint() )
|
|
558 |
lrg._is_float = 1;
|
|
559 |
|
|
560 |
// Check for twice prior spilling. Once prior spilling might have
|
|
561 |
// spilled 'soft', 2nd prior spill should have spilled 'hard' and
|
|
562 |
// further spilling is unlikely to make progress.
|
|
563 |
if( _spilled_once.test(n->_idx) ) {
|
|
564 |
lrg._was_spilled1 = 1;
|
|
565 |
if( _spilled_twice.test(n->_idx) )
|
|
566 |
lrg._was_spilled2 = 1;
|
|
567 |
}
|
|
568 |
|
|
569 |
#ifndef PRODUCT
|
|
570 |
if (trace_spilling() && lrg._def != NULL) {
|
|
571 |
// collect defs for MultiDef printing
|
|
572 |
if (lrg._defs == NULL) {
|
|
573 |
lrg._defs = new (_ifg->_arena) GrowableArray<Node*>();
|
|
574 |
lrg._defs->append(lrg._def);
|
|
575 |
}
|
|
576 |
lrg._defs->append(n);
|
|
577 |
}
|
|
578 |
#endif
|
|
579 |
|
|
580 |
// Check for a single def LRG; these can spill nicely
|
|
581 |
// via rematerialization. Flag as NULL for no def found
|
|
582 |
// yet, or 'n' for single def or -1 for many defs.
|
|
583 |
lrg._def = lrg._def ? NodeSentinel : n;
|
|
584 |
|
|
585 |
// Limit result register mask to acceptable registers
|
|
586 |
const RegMask &rm = n->out_RegMask();
|
|
587 |
lrg.AND( rm );
|
|
588 |
// Check for bound register masks
|
|
589 |
const RegMask &lrgmask = lrg.mask();
|
|
590 |
if( lrgmask.is_bound1() || lrgmask.is_bound2() )
|
|
591 |
lrg._is_bound = 1;
|
|
592 |
|
|
593 |
// Check for maximum frequency value
|
|
594 |
if( lrg._maxfreq < b->_freq )
|
|
595 |
lrg._maxfreq = b->_freq;
|
|
596 |
|
|
597 |
int ireg = n->ideal_reg();
|
|
598 |
assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
|
|
599 |
"oops must be in Op_RegP's" );
|
|
600 |
// Check for oop-iness, or long/double
|
|
601 |
// Check for multi-kill projection
|
|
602 |
switch( ireg ) {
|
|
603 |
case MachProjNode::fat_proj:
|
|
604 |
// Fat projections have size equal to number of registers killed
|
|
605 |
lrg.set_num_regs(rm.Size());
|
|
606 |
lrg.set_reg_pressure(lrg.num_regs());
|
|
607 |
lrg._fat_proj = 1;
|
|
608 |
lrg._is_bound = 1;
|
|
609 |
break;
|
|
610 |
case Op_RegP:
|
|
611 |
#ifdef _LP64
|
|
612 |
lrg.set_num_regs(2); // Size is 2 stack words
|
|
613 |
#else
|
|
614 |
lrg.set_num_regs(1); // Size is 1 stack word
|
|
615 |
#endif
|
|
616 |
// Register pressure is tracked relative to the maximum values
|
|
617 |
// suggested for that platform, INTPRESSURE and FLOATPRESSURE,
|
|
618 |
// and relative to other types which compete for the same regs.
|
|
619 |
//
|
|
620 |
// The following table contains suggested values based on the
|
|
621 |
// architectures as defined in each .ad file.
|
|
622 |
// INTPRESSURE and FLOATPRESSURE may be tuned differently for
|
|
623 |
// compile-speed or performance.
|
|
624 |
// Note1:
|
|
625 |
// SPARC and SPARCV9 reg_pressures are at 2 instead of 1
|
|
626 |
// since .ad registers are defined as high and low halves.
|
|
627 |
// These reg_pressure values remain compatible with the code
|
|
628 |
// in is_high_pressure() which relates get_invalid_mask_size(),
|
|
629 |
// Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
|
|
630 |
// Note2:
|
|
631 |
// SPARC -d32 has 24 registers available for integral values,
|
|
632 |
// but only 10 of these are safe for 64-bit longs.
|
|
633 |
// Using set_reg_pressure(2) for both int and long means
|
|
634 |
// the allocator will believe it can fit 26 longs into
|
|
635 |
// registers. Using 2 for longs and 1 for ints means the
|
|
636 |
// allocator will attempt to put 52 integers into registers.
|
|
637 |
// The settings below limit this problem to methods with
|
|
638 |
// many long values which are being run on 32-bit SPARC.
|
|
639 |
//
|
|
640 |
// ------------------- reg_pressure --------------------
|
|
641 |
// Each entry is reg_pressure_per_value,number_of_regs
|
|
642 |
// RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
|
|
643 |
// IA32 2 1 1 1 1 6 6
|
|
644 |
// IA64 1 1 1 1 1 50 41
|
|
645 |
// SPARC 2 2 2 2 2 48 (24) 52 (26)
|
|
646 |
// SPARCV9 2 2 2 2 2 48 (24) 52 (26)
|
|
647 |
// AMD64 1 1 1 1 1 14 15
|
|
648 |
// -----------------------------------------------------
|
|
649 |
#if defined(SPARC)
|
|
650 |
lrg.set_reg_pressure(2); // use for v9 as well
|
|
651 |
#else
|
|
652 |
lrg.set_reg_pressure(1); // normally one value per register
|
|
653 |
#endif
|
|
654 |
if( n_type->isa_oop_ptr() ) {
|
|
655 |
lrg._is_oop = 1;
|
|
656 |
}
|
|
657 |
break;
|
|
658 |
case Op_RegL: // Check for long or double
|
|
659 |
case Op_RegD:
|
|
660 |
lrg.set_num_regs(2);
|
|
661 |
// Define platform specific register pressure
|
|
662 |
#ifdef SPARC
|
|
663 |
lrg.set_reg_pressure(2);
|
|
664 |
#elif defined(IA32)
|
|
665 |
if( ireg == Op_RegL ) {
|
|
666 |
lrg.set_reg_pressure(2);
|
|
667 |
} else {
|
|
668 |
lrg.set_reg_pressure(1);
|
|
669 |
}
|
|
670 |
#else
|
|
671 |
lrg.set_reg_pressure(1); // normally one value per register
|
|
672 |
#endif
|
|
673 |
// If this def of a double forces a mis-aligned double,
|
|
674 |
// flag as '_fat_proj' - really flag as allowing misalignment
|
|
675 |
// AND changes how we count interferences. A mis-aligned
|
|
676 |
// double can interfere with TWO aligned pairs, or effectively
|
|
677 |
// FOUR registers!
|
|
678 |
if( rm.is_misaligned_Pair() ) {
|
|
679 |
lrg._fat_proj = 1;
|
|
680 |
lrg._is_bound = 1;
|
|
681 |
}
|
|
682 |
break;
|
|
683 |
case Op_RegF:
|
|
684 |
case Op_RegI:
|
|
685 |
case Op_RegFlags:
|
|
686 |
case 0: // not an ideal register
|
|
687 |
lrg.set_num_regs(1);
|
|
688 |
#ifdef SPARC
|
|
689 |
lrg.set_reg_pressure(2);
|
|
690 |
#else
|
|
691 |
lrg.set_reg_pressure(1);
|
|
692 |
#endif
|
|
693 |
break;
|
|
694 |
default:
|
|
695 |
ShouldNotReachHere();
|
|
696 |
}
|
|
697 |
}
|
|
698 |
|
|
699 |
// Now do the same for inputs
|
|
700 |
uint cnt = n->req();
|
|
701 |
// Setup for CISC SPILLING
|
|
702 |
uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
|
|
703 |
if( UseCISCSpill && after_aggressive ) {
|
|
704 |
inp = n->cisc_operand();
|
|
705 |
if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
|
|
706 |
// Convert operand number to edge index number
|
|
707 |
inp = n->as_Mach()->operand_index(inp);
|
|
708 |
}
|
|
709 |
// Prepare register mask for each input
|
|
710 |
for( uint k = input_edge_start; k < cnt; k++ ) {
|
|
711 |
uint vreg = n2lidx(n->in(k));
|
|
712 |
if( !vreg ) continue;
|
|
713 |
|
|
714 |
// If this instruction is CISC Spillable, add the flags
|
|
715 |
// bit to its appropriate input
|
|
716 |
if( UseCISCSpill && after_aggressive && inp == k ) {
|
|
717 |
#ifndef PRODUCT
|
|
718 |
if( TraceCISCSpill ) {
|
|
719 |
tty->print(" use_cisc_RegMask: ");
|
|
720 |
n->dump();
|
|
721 |
}
|
|
722 |
#endif
|
|
723 |
n->as_Mach()->use_cisc_RegMask();
|
|
724 |
}
|
|
725 |
|
|
726 |
LRG &lrg = lrgs(vreg);
|
|
727 |
// // Testing for floating point code shape
|
|
728 |
// Node *test = n->in(k);
|
|
729 |
// if( test->is_Mach() ) {
|
|
730 |
// MachNode *m = test->as_Mach();
|
|
731 |
// int op = m->ideal_Opcode();
|
|
732 |
// if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
|
|
733 |
// int zzz = 1;
|
|
734 |
// }
|
|
735 |
// }
|
|
736 |
|
|
737 |
// Limit result register mask to acceptable registers.
|
|
738 |
// Do not limit registers from uncommon uses before
|
|
739 |
// AggressiveCoalesce. This effectively pre-virtual-splits
|
|
740 |
// around uncommon uses of common defs.
|
|
741 |
const RegMask &rm = n->in_RegMask(k);
|
|
742 |
if( !after_aggressive &&
|
|
743 |
_cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) {
|
|
744 |
// Since we are BEFORE aggressive coalesce, leave the register
|
|
745 |
// mask untrimmed by the call. This encourages more coalescing.
|
|
746 |
// Later, AFTER aggressive, this live range will have to spill
|
|
747 |
// but the spiller handles slow-path calls very nicely.
|
|
748 |
} else {
|
|
749 |
lrg.AND( rm );
|
|
750 |
}
|
|
751 |
// Check for bound register masks
|
|
752 |
const RegMask &lrgmask = lrg.mask();
|
|
753 |
if( lrgmask.is_bound1() || lrgmask.is_bound2() )
|
|
754 |
lrg._is_bound = 1;
|
|
755 |
// If this use of a double forces a mis-aligned double,
|
|
756 |
// flag as '_fat_proj' - really flag as allowing misalignment
|
|
757 |
// AND changes how we count interferences. A mis-aligned
|
|
758 |
// double can interfere with TWO aligned pairs, or effectively
|
|
759 |
// FOUR registers!
|
|
760 |
if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) {
|
|
761 |
lrg._fat_proj = 1;
|
|
762 |
lrg._is_bound = 1;
|
|
763 |
}
|
|
764 |
// if the LRG is an unaligned pair, we will have to spill
|
|
765 |
// so clear the LRG's register mask if it is not already spilled
|
|
766 |
if ( !n->is_SpillCopy() &&
|
|
767 |
(lrg._def == NULL || lrg._def == NodeSentinel || !lrg._def->is_SpillCopy()) &&
|
|
768 |
lrgmask.is_misaligned_Pair()) {
|
|
769 |
lrg.Clear();
|
|
770 |
}
|
|
771 |
|
|
772 |
// Check for maximum frequency value
|
|
773 |
if( lrg._maxfreq < b->_freq )
|
|
774 |
lrg._maxfreq = b->_freq;
|
|
775 |
|
|
776 |
} // End for all allocated inputs
|
|
777 |
} // end for all instructions
|
|
778 |
} // end for all blocks
|
|
779 |
|
|
780 |
// Final per-liverange setup
|
|
781 |
for( uint i2=0; i2<_maxlrg; i2++ ) {
|
|
782 |
LRG &lrg = lrgs(i2);
|
|
783 |
if( lrg.num_regs() == 2 && !lrg._fat_proj )
|
|
784 |
lrg.ClearToPairs();
|
|
785 |
lrg.compute_set_mask_size();
|
|
786 |
if( lrg.not_free() ) { // Handle case where we lose from the start
|
|
787 |
lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
|
|
788 |
lrg._direct_conflict = 1;
|
|
789 |
}
|
|
790 |
lrg.set_degree(0); // no neighbors in IFG yet
|
|
791 |
}
|
|
792 |
}
|
|
793 |
|
|
794 |
//------------------------------set_was_low------------------------------------
|
|
795 |
// Set the was-lo-degree bit. Conservative coalescing should not change the
|
|
796 |
// colorability of the graph. If any live range was of low-degree before
|
|
797 |
// coalescing, it should Simplify. This call sets the was-lo-degree bit.
|
|
798 |
// The bit is checked in Simplify.
|
|
799 |
void PhaseChaitin::set_was_low() {
|
|
800 |
#ifdef ASSERT
|
|
801 |
for( uint i = 1; i < _maxlrg; i++ ) {
|
|
802 |
int size = lrgs(i).num_regs();
|
|
803 |
uint old_was_lo = lrgs(i)._was_lo;
|
|
804 |
lrgs(i)._was_lo = 0;
|
|
805 |
if( lrgs(i).lo_degree() ) {
|
|
806 |
lrgs(i)._was_lo = 1; // Trivially of low degree
|
|
807 |
} else { // Else check the Brigg's assertion
|
|
808 |
// Brigg's observation is that the lo-degree neighbors of a
|
|
809 |
// hi-degree live range will not interfere with the color choices
|
|
810 |
// of said hi-degree live range. The Simplify reverse-stack-coloring
|
|
811 |
// order takes care of the details. Hence you do not have to count
|
|
812 |
// low-degree neighbors when determining if this guy colors.
|
|
813 |
int briggs_degree = 0;
|
|
814 |
IndexSet *s = _ifg->neighbors(i);
|
|
815 |
IndexSetIterator elements(s);
|
|
816 |
uint lidx;
|
|
817 |
while((lidx = elements.next()) != 0) {
|
|
818 |
if( !lrgs(lidx).lo_degree() )
|
|
819 |
briggs_degree += MAX2(size,lrgs(lidx).num_regs());
|
|
820 |
}
|
|
821 |
if( briggs_degree < lrgs(i).degrees_of_freedom() )
|
|
822 |
lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
|
|
823 |
}
|
|
824 |
assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
|
|
825 |
}
|
|
826 |
#endif
|
|
827 |
}
|
|
828 |
|
|
829 |
#define REGISTER_CONSTRAINED 16
|
|
830 |
|
|
831 |
//------------------------------cache_lrg_info---------------------------------
|
|
832 |
// Compute cost/area ratio, in case we spill. Build the lo-degree list.
|
|
833 |
void PhaseChaitin::cache_lrg_info( ) {
|
|
834 |
|
|
835 |
for( uint i = 1; i < _maxlrg; i++ ) {
|
|
836 |
LRG &lrg = lrgs(i);
|
|
837 |
|
|
838 |
// Check for being of low degree: means we can be trivially colored.
|
|
839 |
// Low degree, dead or must-spill guys just get to simplify right away
|
|
840 |
if( lrg.lo_degree() ||
|
|
841 |
!lrg.alive() ||
|
|
842 |
lrg._must_spill ) {
|
|
843 |
// Split low degree list into those guys that must get a
|
|
844 |
// register and those that can go to register or stack.
|
|
845 |
// The idea is LRGs that can go register or stack color first when
|
|
846 |
// they have a good chance of getting a register. The register-only
|
|
847 |
// lo-degree live ranges always get a register.
|
|
848 |
OptoReg::Name hi_reg = lrg.mask().find_last_elem();
|
|
849 |
if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
|
|
850 |
lrg._next = _lo_stk_degree;
|
|
851 |
_lo_stk_degree = i;
|
|
852 |
} else {
|
|
853 |
lrg._next = _lo_degree;
|
|
854 |
_lo_degree = i;
|
|
855 |
}
|
|
856 |
} else { // Else high degree
|
|
857 |
lrgs(_hi_degree)._prev = i;
|
|
858 |
lrg._next = _hi_degree;
|
|
859 |
lrg._prev = 0;
|
|
860 |
_hi_degree = i;
|
|
861 |
}
|
|
862 |
}
|
|
863 |
}
|
|
864 |
|
|
865 |
//------------------------------Pre-Simplify-----------------------------------
|
|
866 |
// Simplify the IFG by removing LRGs of low degree that have NO copies
|
|
867 |
void PhaseChaitin::Pre_Simplify( ) {
|
|
868 |
|
|
869 |
// Warm up the lo-degree no-copy list
|
|
870 |
int lo_no_copy = 0;
|
|
871 |
for( uint i = 1; i < _maxlrg; i++ ) {
|
|
872 |
if( (lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
|
|
873 |
!lrgs(i).alive() ||
|
|
874 |
lrgs(i)._must_spill ) {
|
|
875 |
lrgs(i)._next = lo_no_copy;
|
|
876 |
lo_no_copy = i;
|
|
877 |
}
|
|
878 |
}
|
|
879 |
|
|
880 |
while( lo_no_copy ) {
|
|
881 |
uint lo = lo_no_copy;
|
|
882 |
lo_no_copy = lrgs(lo)._next;
|
|
883 |
int size = lrgs(lo).num_regs();
|
|
884 |
|
|
885 |
// Put the simplified guy on the simplified list.
|
|
886 |
lrgs(lo)._next = _simplified;
|
|
887 |
_simplified = lo;
|
|
888 |
|
|
889 |
// Yank this guy from the IFG.
|
|
890 |
IndexSet *adj = _ifg->remove_node( lo );
|
|
891 |
|
|
892 |
// If any neighbors' degrees fall below their number of
|
|
893 |
// allowed registers, then put that neighbor on the low degree
|
|
894 |
// list. Note that 'degree' can only fall and 'numregs' is
|
|
895 |
// unchanged by this action. Thus the two are equal at most once,
|
|
896 |
// so LRGs hit the lo-degree worklists at most once.
|
|
897 |
IndexSetIterator elements(adj);
|
|
898 |
uint neighbor;
|
|
899 |
while ((neighbor = elements.next()) != 0) {
|
|
900 |
LRG *n = &lrgs(neighbor);
|
|
901 |
assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
|
|
902 |
|
|
903 |
// Check for just becoming of-low-degree
|
|
904 |
if( n->just_lo_degree() && !n->_has_copy ) {
|
|
905 |
assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
|
|
906 |
// Put on lo-degree list
|
|
907 |
n->_next = lo_no_copy;
|
|
908 |
lo_no_copy = neighbor;
|
|
909 |
}
|
|
910 |
}
|
|
911 |
} // End of while lo-degree no_copy worklist not empty
|
|
912 |
|
|
913 |
// No more lo-degree no-copy live ranges to simplify
|
|
914 |
}
|
|
915 |
|
|
916 |
//------------------------------Simplify---------------------------------------
|
|
917 |
// Simplify the IFG by removing LRGs of low degree.
|
|
918 |
void PhaseChaitin::Simplify( ) {
|
|
919 |
|
|
920 |
while( 1 ) { // Repeat till simplified it all
|
|
921 |
// May want to explore simplifying lo_degree before _lo_stk_degree.
|
|
922 |
// This might result in more spills coloring into registers during
|
|
923 |
// Select().
|
|
924 |
while( _lo_degree || _lo_stk_degree ) {
|
|
925 |
// If possible, pull from lo_stk first
|
|
926 |
uint lo;
|
|
927 |
if( _lo_degree ) {
|
|
928 |
lo = _lo_degree;
|
|
929 |
_lo_degree = lrgs(lo)._next;
|
|
930 |
} else {
|
|
931 |
lo = _lo_stk_degree;
|
|
932 |
_lo_stk_degree = lrgs(lo)._next;
|
|
933 |
}
|
|
934 |
|
|
935 |
// Put the simplified guy on the simplified list.
|
|
936 |
lrgs(lo)._next = _simplified;
|
|
937 |
_simplified = lo;
|
|
938 |
// If this guy is "at risk" then mark his current neighbors
|
|
939 |
if( lrgs(lo)._at_risk ) {
|
|
940 |
IndexSetIterator elements(_ifg->neighbors(lo));
|
|
941 |
uint datum;
|
|
942 |
while ((datum = elements.next()) != 0) {
|
|
943 |
lrgs(datum)._risk_bias = lo;
|
|
944 |
}
|
|
945 |
}
|
|
946 |
|
|
947 |
// Yank this guy from the IFG.
|
|
948 |
IndexSet *adj = _ifg->remove_node( lo );
|
|
949 |
|
|
950 |
// If any neighbors' degrees fall below their number of
|
|
951 |
// allowed registers, then put that neighbor on the low degree
|
|
952 |
// list. Note that 'degree' can only fall and 'numregs' is
|
|
953 |
// unchanged by this action. Thus the two are equal at most once,
|
|
954 |
// so LRGs hit the lo-degree worklist at most once.
|
|
955 |
IndexSetIterator elements(adj);
|
|
956 |
uint neighbor;
|
|
957 |
while ((neighbor = elements.next()) != 0) {
|
|
958 |
LRG *n = &lrgs(neighbor);
|
|
959 |
#ifdef ASSERT
|
|
960 |
if( VerifyOpto ) {
|
|
961 |
assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
|
|
962 |
}
|
|
963 |
#endif
|
|
964 |
|
|
965 |
// Check for just becoming of-low-degree just counting registers.
|
|
966 |
// _must_spill live ranges are already on the low degree list.
|
|
967 |
if( n->just_lo_degree() && !n->_must_spill ) {
|
|
968 |
assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
|
|
969 |
// Pull from hi-degree list
|
|
970 |
uint prev = n->_prev;
|
|
971 |
uint next = n->_next;
|
|
972 |
if( prev ) lrgs(prev)._next = next;
|
|
973 |
else _hi_degree = next;
|
|
974 |
lrgs(next)._prev = prev;
|
|
975 |
n->_next = _lo_degree;
|
|
976 |
_lo_degree = neighbor;
|
|
977 |
}
|
|
978 |
}
|
|
979 |
} // End of while lo-degree/lo_stk_degree worklist not empty
|
|
980 |
|
|
981 |
// Check for got everything: is hi-degree list empty?
|
|
982 |
if( !_hi_degree ) break;
|
|
983 |
|
|
984 |
// Time to pick a potential spill guy
|
|
985 |
uint lo_score = _hi_degree;
|
|
986 |
double score = lrgs(lo_score).score();
|
|
987 |
double area = lrgs(lo_score)._area;
|
|
988 |
|
|
989 |
// Find cheapest guy
|
|
990 |
debug_only( int lo_no_simplify=0; );
|
|
991 |
for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
|
|
992 |
assert( !(*_ifg->_yanked)[i], "" );
|
|
993 |
// It's just vaguely possible to move hi-degree to lo-degree without
|
|
994 |
// going through a just-lo-degree stage: If you remove a double from
|
|
995 |
// a float live range it's degree will drop by 2 and you can skip the
|
|
996 |
// just-lo-degree stage. It's very rare (shows up after 5000+ methods
|
|
997 |
// in -Xcomp of Java2Demo). So just choose this guy to simplify next.
|
|
998 |
if( lrgs(i).lo_degree() ) {
|
|
999 |
lo_score = i;
|
|
1000 |
break;
|
|
1001 |
}
|
|
1002 |
debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
|
|
1003 |
double iscore = lrgs(i).score();
|
|
1004 |
double iarea = lrgs(i)._area;
|
|
1005 |
|
|
1006 |
// Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
|
|
1007 |
// wins. Ties happen because all live ranges in question have spilled
|
|
1008 |
// a few times before and the spill-score adds a huge number which
|
|
1009 |
// washes out the low order bits. We are choosing the lesser of 2
|
|
1010 |
// evils; in this case pick largest area to spill.
|
|
1011 |
if( iscore < score ||
|
|
1012 |
(iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ) {
|
|
1013 |
lo_score = i;
|
|
1014 |
score = iscore;
|
|
1015 |
area = iarea;
|
|
1016 |
}
|
|
1017 |
}
|
|
1018 |
LRG *lo_lrg = &lrgs(lo_score);
|
|
1019 |
// The live range we choose for spilling is either hi-degree, or very
|
|
1020 |
// rarely it can be low-degree. If we choose a hi-degree live range
|
|
1021 |
// there better not be any lo-degree choices.
|
|
1022 |
assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
|
|
1023 |
|
|
1024 |
// Pull from hi-degree list
|
|
1025 |
uint prev = lo_lrg->_prev;
|
|
1026 |
uint next = lo_lrg->_next;
|
|
1027 |
if( prev ) lrgs(prev)._next = next;
|
|
1028 |
else _hi_degree = next;
|
|
1029 |
lrgs(next)._prev = prev;
|
|
1030 |
// Jam him on the lo-degree list, despite his high degree.
|
|
1031 |
// Maybe he'll get a color, and maybe he'll spill.
|
|
1032 |
// Only Select() will know.
|
|
1033 |
lrgs(lo_score)._at_risk = true;
|
|
1034 |
_lo_degree = lo_score;
|
|
1035 |
lo_lrg->_next = 0;
|
|
1036 |
|
|
1037 |
} // End of while not simplified everything
|
|
1038 |
|
|
1039 |
}
|
|
1040 |
|
|
1041 |
//------------------------------bias_color-------------------------------------
|
|
1042 |
// Choose a color using the biasing heuristic
|
|
1043 |
OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
|
|
1044 |
|
|
1045 |
// Check for "at_risk" LRG's
|
|
1046 |
uint risk_lrg = Find(lrg._risk_bias);
|
|
1047 |
if( risk_lrg != 0 ) {
|
|
1048 |
// Walk the colored neighbors of the "at_risk" candidate
|
|
1049 |
// Choose a color which is both legal and already taken by a neighbor
|
|
1050 |
// of the "at_risk" candidate in order to improve the chances of the
|
|
1051 |
// "at_risk" candidate of coloring
|
|
1052 |
IndexSetIterator elements(_ifg->neighbors(risk_lrg));
|
|
1053 |
uint datum;
|
|
1054 |
while ((datum = elements.next()) != 0) {
|
|
1055 |
OptoReg::Name reg = lrgs(datum).reg();
|
|
1056 |
// If this LRG's register is legal for us, choose it
|
|
1057 |
if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
|
|
1058 |
lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
|
|
1059 |
(lrg.num_regs()==1 || // either size 1
|
|
1060 |
(reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
|
|
1061 |
return reg;
|
|
1062 |
}
|
|
1063 |
}
|
|
1064 |
|
|
1065 |
uint copy_lrg = Find(lrg._copy_bias);
|
|
1066 |
if( copy_lrg != 0 ) {
|
|
1067 |
// If he has a color,
|
|
1068 |
if( !(*(_ifg->_yanked))[copy_lrg] ) {
|
|
1069 |
OptoReg::Name reg = lrgs(copy_lrg).reg();
|
|
1070 |
// And it is legal for you,
|
|
1071 |
if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
|
|
1072 |
lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
|
|
1073 |
(lrg.num_regs()==1 || // either size 1
|
|
1074 |
(reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
|
|
1075 |
return reg;
|
|
1076 |
} else if( chunk == 0 ) {
|
|
1077 |
// Choose a color which is legal for him
|
|
1078 |
RegMask tempmask = lrg.mask();
|
|
1079 |
tempmask.AND(lrgs(copy_lrg).mask());
|
|
1080 |
OptoReg::Name reg;
|
|
1081 |
if( lrg.num_regs() == 1 ) {
|
|
1082 |
reg = tempmask.find_first_elem();
|
|
1083 |
} else {
|
|
1084 |
tempmask.ClearToPairs();
|
|
1085 |
reg = tempmask.find_first_pair();
|
|
1086 |
}
|
|
1087 |
if( OptoReg::is_valid(reg) )
|
|
1088 |
return reg;
|
|
1089 |
}
|
|
1090 |
}
|
|
1091 |
|
|
1092 |
// If no bias info exists, just go with the register selection ordering
|
|
1093 |
if( lrg.num_regs() == 2 ) {
|
|
1094 |
// Find an aligned pair
|
|
1095 |
return OptoReg::add(lrg.mask().find_first_pair(),chunk);
|
|
1096 |
}
|
|
1097 |
|
|
1098 |
// CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
|
|
1099 |
// copy removal to remove many more copies, by preventing a just-assigned
|
|
1100 |
// register from being repeatedly assigned.
|
|
1101 |
OptoReg::Name reg = lrg.mask().find_first_elem();
|
|
1102 |
if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
|
|
1103 |
// This 'Remove; find; Insert' idiom is an expensive way to find the
|
|
1104 |
// SECOND element in the mask.
|
|
1105 |
lrg.Remove(reg);
|
|
1106 |
OptoReg::Name reg2 = lrg.mask().find_first_elem();
|
|
1107 |
lrg.Insert(reg);
|
|
1108 |
if( OptoReg::is_reg(reg2))
|
|
1109 |
reg = reg2;
|
|
1110 |
}
|
|
1111 |
return OptoReg::add( reg, chunk );
|
|
1112 |
}
|
|
1113 |
|
|
1114 |
//------------------------------choose_color-----------------------------------
|
|
1115 |
// Choose a color in the current chunk
|
|
1116 |
OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
|
|
1117 |
assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
|
|
1118 |
assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
|
|
1119 |
|
|
1120 |
if( lrg.num_regs() == 1 || // Common Case
|
|
1121 |
!lrg._fat_proj ) // Aligned+adjacent pairs ok
|
|
1122 |
// Use a heuristic to "bias" the color choice
|
|
1123 |
return bias_color(lrg, chunk);
|
|
1124 |
|
|
1125 |
assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
|
|
1126 |
|
|
1127 |
// Fat-proj case or misaligned double argument.
|
|
1128 |
assert(lrg.compute_mask_size() == lrg.num_regs() ||
|
|
1129 |
lrg.num_regs() == 2,"fat projs exactly color" );
|
|
1130 |
assert( !chunk, "always color in 1st chunk" );
|
|
1131 |
// Return the highest element in the set.
|
|
1132 |
return lrg.mask().find_last_elem();
|
|
1133 |
}
|
|
1134 |
|
|
1135 |
//------------------------------Select-----------------------------------------
|
|
1136 |
// Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
|
|
1137 |
// in reverse order of removal. As long as nothing of hi-degree was yanked,
|
|
1138 |
// everything going back is guaranteed a color. Select that color. If some
|
|
1139 |
// hi-degree LRG cannot get a color then we record that we must spill.
|
|
1140 |
uint PhaseChaitin::Select( ) {
|
|
1141 |
uint spill_reg = LRG::SPILL_REG;
|
|
1142 |
_max_reg = OptoReg::Name(0); // Past max register used
|
|
1143 |
while( _simplified ) {
|
|
1144 |
// Pull next LRG from the simplified list - in reverse order of removal
|
|
1145 |
uint lidx = _simplified;
|
|
1146 |
LRG *lrg = &lrgs(lidx);
|
|
1147 |
_simplified = lrg->_next;
|
|
1148 |
|
|
1149 |
|
|
1150 |
#ifndef PRODUCT
|
|
1151 |
if (trace_spilling()) {
|
|
1152 |
ttyLocker ttyl;
|
|
1153 |
tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
|
|
1154 |
lrg->degrees_of_freedom());
|
|
1155 |
lrg->dump();
|
|
1156 |
}
|
|
1157 |
#endif
|
|
1158 |
|
|
1159 |
// Re-insert into the IFG
|
|
1160 |
_ifg->re_insert(lidx);
|
|
1161 |
if( !lrg->alive() ) continue;
|
|
1162 |
// capture allstackedness flag before mask is hacked
|
|
1163 |
const int is_allstack = lrg->mask().is_AllStack();
|
|
1164 |
|
|
1165 |
// Yeah, yeah, yeah, I know, I know. I can refactor this
|
|
1166 |
// to avoid the GOTO, although the refactored code will not
|
|
1167 |
// be much clearer. We arrive here IFF we have a stack-based
|
|
1168 |
// live range that cannot color in the current chunk, and it
|
|
1169 |
// has to move into the next free stack chunk.
|
|
1170 |
int chunk = 0; // Current chunk is first chunk
|
|
1171 |
retry_next_chunk:
|
|
1172 |
|
|
1173 |
// Remove neighbor colors
|
|
1174 |
IndexSet *s = _ifg->neighbors(lidx);
|
|
1175 |
|
|
1176 |
debug_only(RegMask orig_mask = lrg->mask();)
|
|
1177 |
IndexSetIterator elements(s);
|
|
1178 |
uint neighbor;
|
|
1179 |
while ((neighbor = elements.next()) != 0) {
|
|
1180 |
// Note that neighbor might be a spill_reg. In this case, exclusion
|
|
1181 |
// of its color will be a no-op, since the spill_reg chunk is in outer
|
|
1182 |
// space. Also, if neighbor is in a different chunk, this exclusion
|
|
1183 |
// will be a no-op. (Later on, if lrg runs out of possible colors in
|
|
1184 |
// its chunk, a new chunk of color may be tried, in which case
|
|
1185 |
// examination of neighbors is started again, at retry_next_chunk.)
|
|
1186 |
LRG &nlrg = lrgs(neighbor);
|
|
1187 |
OptoReg::Name nreg = nlrg.reg();
|
|
1188 |
// Only subtract masks in the same chunk
|
|
1189 |
if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
|
|
1190 |
#ifndef PRODUCT
|
|
1191 |
uint size = lrg->mask().Size();
|
|
1192 |
RegMask rm = lrg->mask();
|
|
1193 |
#endif
|
|
1194 |
lrg->SUBTRACT(nlrg.mask());
|
|
1195 |
#ifndef PRODUCT
|
|
1196 |
if (trace_spilling() && lrg->mask().Size() != size) {
|
|
1197 |
ttyLocker ttyl;
|
|
1198 |
tty->print("L%d ", lidx);
|
|
1199 |
rm.dump();
|
|
1200 |
tty->print(" intersected L%d ", neighbor);
|
|
1201 |
nlrg.mask().dump();
|
|
1202 |
tty->print(" removed ");
|
|
1203 |
rm.SUBTRACT(lrg->mask());
|
|
1204 |
rm.dump();
|
|
1205 |
tty->print(" leaving ");
|
|
1206 |
lrg->mask().dump();
|
|
1207 |
tty->cr();
|
|
1208 |
}
|
|
1209 |
#endif
|
|
1210 |
}
|
|
1211 |
}
|
|
1212 |
//assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
|
|
1213 |
// Aligned pairs need aligned masks
|
|
1214 |
if( lrg->num_regs() == 2 && !lrg->_fat_proj )
|
|
1215 |
lrg->ClearToPairs();
|
|
1216 |
|
|
1217 |
// Check if a color is available and if so pick the color
|
|
1218 |
OptoReg::Name reg = choose_color( *lrg, chunk );
|
|
1219 |
#ifdef SPARC
|
|
1220 |
debug_only(lrg->compute_set_mask_size());
|
|
1221 |
assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
|
|
1222 |
#endif
|
|
1223 |
|
|
1224 |
//---------------
|
|
1225 |
// If we fail to color and the AllStack flag is set, trigger
|
|
1226 |
// a chunk-rollover event
|
|
1227 |
if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
|
|
1228 |
// Bump register mask up to next stack chunk
|
|
1229 |
chunk += RegMask::CHUNK_SIZE;
|
|
1230 |
lrg->Set_All();
|
|
1231 |
|
|
1232 |
goto retry_next_chunk;
|
|
1233 |
}
|
|
1234 |
|
|
1235 |
//---------------
|
|
1236 |
// Did we get a color?
|
|
1237 |
else if( OptoReg::is_valid(reg)) {
|
|
1238 |
#ifndef PRODUCT
|
|
1239 |
RegMask avail_rm = lrg->mask();
|
|
1240 |
#endif
|
|
1241 |
|
|
1242 |
// Record selected register
|
|
1243 |
lrg->set_reg(reg);
|
|
1244 |
|
|
1245 |
if( reg >= _max_reg ) // Compute max register limit
|
|
1246 |
_max_reg = OptoReg::add(reg,1);
|
|
1247 |
// Fold reg back into normal space
|
|
1248 |
reg = OptoReg::add(reg,-chunk);
|
|
1249 |
|
|
1250 |
// If the live range is not bound, then we actually had some choices
|
|
1251 |
// to make. In this case, the mask has more bits in it than the colors
|
|
1252 |
// choosen. Restrict the mask to just what was picked.
|
|
1253 |
if( lrg->num_regs() == 1 ) { // Size 1 live range
|
|
1254 |
lrg->Clear(); // Clear the mask
|
|
1255 |
lrg->Insert(reg); // Set regmask to match selected reg
|
|
1256 |
lrg->set_mask_size(1);
|
|
1257 |
} else if( !lrg->_fat_proj ) {
|
|
1258 |
// For pairs, also insert the low bit of the pair
|
|
1259 |
assert( lrg->num_regs() == 2, "unbound fatproj???" );
|
|
1260 |
lrg->Clear(); // Clear the mask
|
|
1261 |
lrg->Insert(reg); // Set regmask to match selected reg
|
|
1262 |
lrg->Insert(OptoReg::add(reg,-1));
|
|
1263 |
lrg->set_mask_size(2);
|
|
1264 |
} else { // Else fatproj
|
|
1265 |
// mask must be equal to fatproj bits, by definition
|
|
1266 |
}
|
|
1267 |
#ifndef PRODUCT
|
|
1268 |
if (trace_spilling()) {
|
|
1269 |
ttyLocker ttyl;
|
|
1270 |
tty->print("L%d selected ", lidx);
|
|
1271 |
lrg->mask().dump();
|
|
1272 |
tty->print(" from ");
|
|
1273 |
avail_rm.dump();
|
|
1274 |
tty->cr();
|
|
1275 |
}
|
|
1276 |
#endif
|
|
1277 |
// Note that reg is the highest-numbered register in the newly-bound mask.
|
|
1278 |
} // end color available case
|
|
1279 |
|
|
1280 |
//---------------
|
|
1281 |
// Live range is live and no colors available
|
|
1282 |
else {
|
|
1283 |
assert( lrg->alive(), "" );
|
|
1284 |
assert( !lrg->_fat_proj || lrg->_def == NodeSentinel ||
|
|
1285 |
lrg->_def->outcnt() > 0, "fat_proj cannot spill");
|
|
1286 |
assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
|
|
1287 |
|
|
1288 |
// Assign the special spillreg register
|
|
1289 |
lrg->set_reg(OptoReg::Name(spill_reg++));
|
|
1290 |
// Do not empty the regmask; leave mask_size lying around
|
|
1291 |
// for use during Spilling
|
|
1292 |
#ifndef PRODUCT
|
|
1293 |
if( trace_spilling() ) {
|
|
1294 |
ttyLocker ttyl;
|
|
1295 |
tty->print("L%d spilling with neighbors: ", lidx);
|
|
1296 |
s->dump();
|
|
1297 |
debug_only(tty->print(" original mask: "));
|
|
1298 |
debug_only(orig_mask.dump());
|
|
1299 |
dump_lrg(lidx);
|
|
1300 |
}
|
|
1301 |
#endif
|
|
1302 |
} // end spill case
|
|
1303 |
|
|
1304 |
}
|
|
1305 |
|
|
1306 |
return spill_reg-LRG::SPILL_REG; // Return number of spills
|
|
1307 |
}
|
|
1308 |
|
|
1309 |
|
|
1310 |
//------------------------------copy_was_spilled-------------------------------
|
|
1311 |
// Copy 'was_spilled'-edness from the source Node to the dst Node.
|
|
1312 |
void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
|
|
1313 |
if( _spilled_once.test(src->_idx) ) {
|
|
1314 |
_spilled_once.set(dst->_idx);
|
|
1315 |
lrgs(Find(dst))._was_spilled1 = 1;
|
|
1316 |
if( _spilled_twice.test(src->_idx) ) {
|
|
1317 |
_spilled_twice.set(dst->_idx);
|
|
1318 |
lrgs(Find(dst))._was_spilled2 = 1;
|
|
1319 |
}
|
|
1320 |
}
|
|
1321 |
}
|
|
1322 |
|
|
1323 |
//------------------------------set_was_spilled--------------------------------
|
|
1324 |
// Set the 'spilled_once' or 'spilled_twice' flag on a node.
|
|
1325 |
void PhaseChaitin::set_was_spilled( Node *n ) {
|
|
1326 |
if( _spilled_once.test_set(n->_idx) )
|
|
1327 |
_spilled_twice.set(n->_idx);
|
|
1328 |
}
|
|
1329 |
|
|
1330 |
//------------------------------fixup_spills-----------------------------------
|
|
1331 |
// Convert Ideal spill instructions into proper FramePtr + offset Loads and
|
|
1332 |
// Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
|
|
1333 |
void PhaseChaitin::fixup_spills() {
|
|
1334 |
// This function does only cisc spill work.
|
|
1335 |
if( !UseCISCSpill ) return;
|
|
1336 |
|
|
1337 |
NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
|
|
1338 |
|
|
1339 |
// Grab the Frame Pointer
|
|
1340 |
Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
|
|
1341 |
|
|
1342 |
// For all blocks
|
|
1343 |
for( uint i = 0; i < _cfg._num_blocks; i++ ) {
|
|
1344 |
Block *b = _cfg._blocks[i];
|
|
1345 |
|
|
1346 |
// For all instructions in block
|
|
1347 |
uint last_inst = b->end_idx();
|
|
1348 |
for( uint j = 1; j <= last_inst; j++ ) {
|
|
1349 |
Node *n = b->_nodes[j];
|
|
1350 |
|
|
1351 |
// Dead instruction???
|
|
1352 |
assert( n->outcnt() != 0 ||// Nothing dead after post alloc
|
|
1353 |
C->top() == n || // Or the random TOP node
|
|
1354 |
n->is_Proj(), // Or a fat-proj kill node
|
|
1355 |
"No dead instructions after post-alloc" );
|
|
1356 |
|
|
1357 |
int inp = n->cisc_operand();
|
|
1358 |
if( inp != AdlcVMDeps::Not_cisc_spillable ) {
|
|
1359 |
// Convert operand number to edge index number
|
|
1360 |
MachNode *mach = n->as_Mach();
|
|
1361 |
inp = mach->operand_index(inp);
|
|
1362 |
Node *src = n->in(inp); // Value to load or store
|
|
1363 |
LRG &lrg_cisc = lrgs( Find_const(src) );
|
|
1364 |
OptoReg::Name src_reg = lrg_cisc.reg();
|
|
1365 |
// Doubles record the HIGH register of an adjacent pair.
|
|
1366 |
src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
|
|
1367 |
if( OptoReg::is_stack(src_reg) ) { // If input is on stack
|
|
1368 |
// This is a CISC Spill, get stack offset and construct new node
|
|
1369 |
#ifndef PRODUCT
|
|
1370 |
if( TraceCISCSpill ) {
|
|
1371 |
tty->print(" reg-instr: ");
|
|
1372 |
n->dump();
|
|
1373 |
}
|
|
1374 |
#endif
|
|
1375 |
int stk_offset = reg2offset(src_reg);
|
|
1376 |
// Bailout if we might exceed node limit when spilling this instruction
|
|
1377 |
C->check_node_count(0, "out of nodes fixing spills");
|
|
1378 |
if (C->failing()) return;
|
|
1379 |
// Transform node
|
|
1380 |
MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
|
|
1381 |
cisc->set_req(inp,fp); // Base register is frame pointer
|
|
1382 |
if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
|
|
1383 |
assert( cisc->oper_input_base() == 2, "Only adding one edge");
|
|
1384 |
cisc->ins_req(1,src); // Requires a memory edge
|
|
1385 |
}
|
|
1386 |
b->_nodes.map(j,cisc); // Insert into basic block
|
|
1387 |
n->replace_by(cisc); // Correct graph
|
|
1388 |
//
|
|
1389 |
++_used_cisc_instructions;
|
|
1390 |
#ifndef PRODUCT
|
|
1391 |
if( TraceCISCSpill ) {
|
|
1392 |
tty->print(" cisc-instr: ");
|
|
1393 |
cisc->dump();
|
|
1394 |
}
|
|
1395 |
#endif
|
|
1396 |
} else {
|
|
1397 |
#ifndef PRODUCT
|
|
1398 |
if( TraceCISCSpill ) {
|
|
1399 |
tty->print(" using reg-instr: ");
|
|
1400 |
n->dump();
|
|
1401 |
}
|
|
1402 |
#endif
|
|
1403 |
++_unused_cisc_instructions; // input can be on stack
|
|
1404 |
}
|
|
1405 |
}
|
|
1406 |
|
|
1407 |
} // End of for all instructions
|
|
1408 |
|
|
1409 |
} // End of for all blocks
|
|
1410 |
}
|
|
1411 |
|
|
1412 |
//------------------------------find_base_for_derived--------------------------
|
|
1413 |
// Helper to stretch above; recursively discover the base Node for a
|
|
1414 |
// given derived Node. Easy for AddP-related machine nodes, but needs
|
|
1415 |
// to be recursive for derived Phis.
|
|
1416 |
Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
|
|
1417 |
// See if already computed; if so return it
|
|
1418 |
if( derived_base_map[derived->_idx] )
|
|
1419 |
return derived_base_map[derived->_idx];
|
|
1420 |
|
|
1421 |
// See if this happens to be a base.
|
|
1422 |
// NOTE: we use TypePtr instead of TypeOopPtr because we can have
|
|
1423 |
// pointers derived from NULL! These are always along paths that
|
|
1424 |
// can't happen at run-time but the optimizer cannot deduce it so
|
|
1425 |
// we have to handle it gracefully.
|
|
1426 |
const TypePtr *tj = derived->bottom_type()->isa_ptr();
|
|
1427 |
// If its an OOP with a non-zero offset, then it is derived.
|
|
1428 |
if( tj->_offset == 0 ) {
|
|
1429 |
derived_base_map[derived->_idx] = derived;
|
|
1430 |
return derived;
|
|
1431 |
}
|
|
1432 |
// Derived is NULL+offset? Base is NULL!
|
|
1433 |
if( derived->is_Con() ) {
|
|
1434 |
Node *base = new (C, 1) ConPNode( TypePtr::NULL_PTR );
|
|
1435 |
uint no_lidx = 0; // an unmatched constant in debug info has no LRG
|
|
1436 |
_names.extend(base->_idx, no_lidx);
|
|
1437 |
derived_base_map[derived->_idx] = base;
|
|
1438 |
return base;
|
|
1439 |
}
|
|
1440 |
|
|
1441 |
// Check for AddP-related opcodes
|
|
1442 |
if( !derived->is_Phi() ) {
|
|
1443 |
assert( derived->as_Mach()->ideal_Opcode() == Op_AddP, "" );
|
|
1444 |
Node *base = derived->in(AddPNode::Base);
|
|
1445 |
derived_base_map[derived->_idx] = base;
|
|
1446 |
return base;
|
|
1447 |
}
|
|
1448 |
|
|
1449 |
// Recursively find bases for Phis.
|
|
1450 |
// First check to see if we can avoid a base Phi here.
|
|
1451 |
Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
|
|
1452 |
uint i;
|
|
1453 |
for( i = 2; i < derived->req(); i++ )
|
|
1454 |
if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
|
|
1455 |
break;
|
|
1456 |
// Went to the end without finding any different bases?
|
|
1457 |
if( i == derived->req() ) { // No need for a base Phi here
|
|
1458 |
derived_base_map[derived->_idx] = base;
|
|
1459 |
return base;
|
|
1460 |
}
|
|
1461 |
|
|
1462 |
// Now we see we need a base-Phi here to merge the bases
|
|
1463 |
base = new (C, derived->req()) PhiNode( derived->in(0), base->bottom_type() );
|
|
1464 |
for( i = 1; i < derived->req(); i++ )
|
|
1465 |
base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
|
|
1466 |
|
|
1467 |
// Search the current block for an existing base-Phi
|
|
1468 |
Block *b = _cfg._bbs[derived->_idx];
|
|
1469 |
for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
|
|
1470 |
Node *phi = b->_nodes[i];
|
|
1471 |
if( !phi->is_Phi() ) { // Found end of Phis with no match?
|
|
1472 |
b->_nodes.insert( i, base ); // Must insert created Phi here as base
|
|
1473 |
_cfg._bbs.map( base->_idx, b );
|
|
1474 |
new_lrg(base,maxlrg++);
|
|
1475 |
break;
|
|
1476 |
}
|
|
1477 |
// See if Phi matches.
|
|
1478 |
uint j;
|
|
1479 |
for( j = 1; j < base->req(); j++ )
|
|
1480 |
if( phi->in(j) != base->in(j) &&
|
|
1481 |
!(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
|
|
1482 |
break;
|
|
1483 |
if( j == base->req() ) { // All inputs match?
|
|
1484 |
base = phi; // Then use existing 'phi' and drop 'base'
|
|
1485 |
break;
|
|
1486 |
}
|
|
1487 |
}
|
|
1488 |
|
|
1489 |
|
|
1490 |
// Cache info for later passes
|
|
1491 |
derived_base_map[derived->_idx] = base;
|
|
1492 |
return base;
|
|
1493 |
}
|
|
1494 |
|
|
1495 |
|
|
1496 |
//------------------------------stretch_base_pointer_live_ranges---------------
|
|
1497 |
// At each Safepoint, insert extra debug edges for each pair of derived value/
|
|
1498 |
// base pointer that is live across the Safepoint for oopmap building. The
|
|
1499 |
// edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
|
|
1500 |
// required edge set.
|
|
1501 |
bool PhaseChaitin::stretch_base_pointer_live_ranges( ResourceArea *a ) {
|
|
1502 |
int must_recompute_live = false;
|
|
1503 |
uint maxlrg = _maxlrg;
|
|
1504 |
Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
|
|
1505 |
memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
|
|
1506 |
|
|
1507 |
// For all blocks in RPO do...
|
|
1508 |
for( uint i=0; i<_cfg._num_blocks; i++ ) {
|
|
1509 |
Block *b = _cfg._blocks[i];
|
|
1510 |
// Note use of deep-copy constructor. I cannot hammer the original
|
|
1511 |
// liveout bits, because they are needed by the following coalesce pass.
|
|
1512 |
IndexSet liveout(_live->live(b));
|
|
1513 |
|
|
1514 |
for( uint j = b->end_idx() + 1; j > 1; j-- ) {
|
|
1515 |
Node *n = b->_nodes[j-1];
|
|
1516 |
|
|
1517 |
// Pre-split compares of loop-phis. Loop-phis form a cycle we would
|
|
1518 |
// like to see in the same register. Compare uses the loop-phi and so
|
|
1519 |
// extends its live range BUT cannot be part of the cycle. If this
|
|
1520 |
// extended live range overlaps with the update of the loop-phi value
|
|
1521 |
// we need both alive at the same time -- which requires at least 1
|
|
1522 |
// copy. But because Intel has only 2-address registers we end up with
|
|
1523 |
// at least 2 copies, one before the loop-phi update instruction and
|
|
1524 |
// one after. Instead we split the input to the compare just after the
|
|
1525 |
// phi.
|
|
1526 |
if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
|
|
1527 |
Node *phi = n->in(1);
|
|
1528 |
if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
|
|
1529 |
Block *phi_block = _cfg._bbs[phi->_idx];
|
|
1530 |
if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) {
|
|
1531 |
const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
|
|
1532 |
Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
|
|
1533 |
insert_proj( phi_block, 1, spill, maxlrg++ );
|
|
1534 |
n->set_req(1,spill);
|
|
1535 |
must_recompute_live = true;
|
|
1536 |
}
|
|
1537 |
}
|
|
1538 |
}
|
|
1539 |
|
|
1540 |
// Get value being defined
|
|
1541 |
uint lidx = n2lidx(n);
|
|
1542 |
if( lidx && lidx < _maxlrg /* Ignore the occasional brand-new live range */) {
|
|
1543 |
// Remove from live-out set
|
|
1544 |
liveout.remove(lidx);
|
|
1545 |
|
|
1546 |
// Copies do not define a new value and so do not interfere.
|
|
1547 |
// Remove the copies source from the liveout set before interfering.
|
|
1548 |
uint idx = n->is_Copy();
|
|
1549 |
if( idx ) liveout.remove( n2lidx(n->in(idx)) );
|
|
1550 |
}
|
|
1551 |
|
|
1552 |
// Found a safepoint?
|
|
1553 |
JVMState *jvms = n->jvms();
|
|
1554 |
if( jvms ) {
|
|
1555 |
// Now scan for a live derived pointer
|
|
1556 |
IndexSetIterator elements(&liveout);
|
|
1557 |
uint neighbor;
|
|
1558 |
while ((neighbor = elements.next()) != 0) {
|
|
1559 |
// Find reaching DEF for base and derived values
|
|
1560 |
// This works because we are still in SSA during this call.
|
|
1561 |
Node *derived = lrgs(neighbor)._def;
|
|
1562 |
const TypePtr *tj = derived->bottom_type()->isa_ptr();
|
|
1563 |
// If its an OOP with a non-zero offset, then it is derived.
|
|
1564 |
if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
|
|
1565 |
Node *base = find_base_for_derived( derived_base_map, derived, maxlrg );
|
|
1566 |
assert( base->_idx < _names.Size(), "" );
|
|
1567 |
// Add reaching DEFs of derived pointer and base pointer as a
|
|
1568 |
// pair of inputs
|
|
1569 |
n->add_req( derived );
|
|
1570 |
n->add_req( base );
|
|
1571 |
|
|
1572 |
// See if the base pointer is already live to this point.
|
|
1573 |
// Since I'm working on the SSA form, live-ness amounts to
|
|
1574 |
// reaching def's. So if I find the base's live range then
|
|
1575 |
// I know the base's def reaches here.
|
|
1576 |
if( (n2lidx(base) >= _maxlrg ||// (Brand new base (hence not live) or
|
|
1577 |
!liveout.member( n2lidx(base) ) ) && // not live) AND
|
|
1578 |
(n2lidx(base) > 0) && // not a constant
|
|
1579 |
_cfg._bbs[base->_idx] != b ) { // base not def'd in blk)
|
|
1580 |
// Base pointer is not currently live. Since I stretched
|
|
1581 |
// the base pointer to here and it crosses basic-block
|
|
1582 |
// boundaries, the global live info is now incorrect.
|
|
1583 |
// Recompute live.
|
|
1584 |
must_recompute_live = true;
|
|
1585 |
} // End of if base pointer is not live to debug info
|
|
1586 |
}
|
|
1587 |
} // End of scan all live data for derived ptrs crossing GC point
|
|
1588 |
} // End of if found a GC point
|
|
1589 |
|
|
1590 |
// Make all inputs live
|
|
1591 |
if( !n->is_Phi() ) { // Phi function uses come from prior block
|
|
1592 |
for( uint k = 1; k < n->req(); k++ ) {
|
|
1593 |
uint lidx = n2lidx(n->in(k));
|
|
1594 |
if( lidx < _maxlrg )
|
|
1595 |
liveout.insert( lidx );
|
|
1596 |
}
|
|
1597 |
}
|
|
1598 |
|
|
1599 |
} // End of forall instructions in block
|
|
1600 |
liveout.clear(); // Free the memory used by liveout.
|
|
1601 |
|
|
1602 |
} // End of forall blocks
|
|
1603 |
_maxlrg = maxlrg;
|
|
1604 |
|
|
1605 |
// If I created a new live range I need to recompute live
|
|
1606 |
if( maxlrg != _ifg->_maxlrg )
|
|
1607 |
must_recompute_live = true;
|
|
1608 |
|
|
1609 |
return must_recompute_live != 0;
|
|
1610 |
}
|
|
1611 |
|
|
1612 |
|
|
1613 |
//------------------------------add_reference----------------------------------
|
|
1614 |
// Extend the node to LRG mapping
|
|
1615 |
void PhaseChaitin::add_reference( const Node *node, const Node *old_node ) {
|
|
1616 |
_names.extend( node->_idx, n2lidx(old_node) );
|
|
1617 |
}
|
|
1618 |
|
|
1619 |
//------------------------------dump-------------------------------------------
|
|
1620 |
#ifndef PRODUCT
|
|
1621 |
void PhaseChaitin::dump( const Node *n ) const {
|
|
1622 |
uint r = (n->_idx < _names.Size() ) ? Find_const(n) : 0;
|
|
1623 |
tty->print("L%d",r);
|
|
1624 |
if( r && n->Opcode() != Op_Phi ) {
|
|
1625 |
if( _node_regs ) { // Got a post-allocation copy of allocation?
|
|
1626 |
tty->print("[");
|
|
1627 |
OptoReg::Name second = get_reg_second(n);
|
|
1628 |
if( OptoReg::is_valid(second) ) {
|
|
1629 |
if( OptoReg::is_reg(second) )
|
|
1630 |
tty->print("%s:",Matcher::regName[second]);
|
|
1631 |
else
|
|
1632 |
tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
|
|
1633 |
}
|
|
1634 |
OptoReg::Name first = get_reg_first(n);
|
|
1635 |
if( OptoReg::is_reg(first) )
|
|
1636 |
tty->print("%s]",Matcher::regName[first]);
|
|
1637 |
else
|
|
1638 |
tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
|
|
1639 |
} else
|
|
1640 |
n->out_RegMask().dump();
|
|
1641 |
}
|
|
1642 |
tty->print("/N%d\t",n->_idx);
|
|
1643 |
tty->print("%s === ", n->Name());
|
|
1644 |
uint k;
|
|
1645 |
for( k = 0; k < n->req(); k++) {
|
|
1646 |
Node *m = n->in(k);
|
|
1647 |
if( !m ) tty->print("_ ");
|
|
1648 |
else {
|
|
1649 |
uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
|
|
1650 |
tty->print("L%d",r);
|
|
1651 |
// Data MultiNode's can have projections with no real registers.
|
|
1652 |
// Don't die while dumping them.
|
|
1653 |
int op = n->Opcode();
|
|
1654 |
if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
|
|
1655 |
if( _node_regs ) {
|
|
1656 |
tty->print("[");
|
|
1657 |
OptoReg::Name second = get_reg_second(n->in(k));
|
|
1658 |
if( OptoReg::is_valid(second) ) {
|
|
1659 |
if( OptoReg::is_reg(second) )
|
|
1660 |
tty->print("%s:",Matcher::regName[second]);
|
|
1661 |
else
|
|
1662 |
tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
|
|
1663 |
reg2offset_unchecked(second));
|
|
1664 |
}
|
|
1665 |
OptoReg::Name first = get_reg_first(n->in(k));
|
|
1666 |
if( OptoReg::is_reg(first) )
|
|
1667 |
tty->print("%s]",Matcher::regName[first]);
|
|
1668 |
else
|
|
1669 |
tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
|
|
1670 |
reg2offset_unchecked(first));
|
|
1671 |
} else
|
|
1672 |
n->in_RegMask(k).dump();
|
|
1673 |
}
|
|
1674 |
tty->print("/N%d ",m->_idx);
|
|
1675 |
}
|
|
1676 |
}
|
|
1677 |
if( k < n->len() && n->in(k) ) tty->print("| ");
|
|
1678 |
for( ; k < n->len(); k++ ) {
|
|
1679 |
Node *m = n->in(k);
|
|
1680 |
if( !m ) break;
|
|
1681 |
uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
|
|
1682 |
tty->print("L%d",r);
|
|
1683 |
tty->print("/N%d ",m->_idx);
|
|
1684 |
}
|
|
1685 |
if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
|
|
1686 |
else n->dump_spec(tty);
|
|
1687 |
if( _spilled_once.test(n->_idx ) ) {
|
|
1688 |
tty->print(" Spill_1");
|
|
1689 |
if( _spilled_twice.test(n->_idx ) )
|
|
1690 |
tty->print(" Spill_2");
|
|
1691 |
}
|
|
1692 |
tty->print("\n");
|
|
1693 |
}
|
|
1694 |
|
|
1695 |
void PhaseChaitin::dump( const Block * b ) const {
|
|
1696 |
b->dump_head( &_cfg._bbs );
|
|
1697 |
|
|
1698 |
// For all instructions
|
|
1699 |
for( uint j = 0; j < b->_nodes.size(); j++ )
|
|
1700 |
dump(b->_nodes[j]);
|
|
1701 |
// Print live-out info at end of block
|
|
1702 |
if( _live ) {
|
|
1703 |
tty->print("Liveout: ");
|
|
1704 |
IndexSet *live = _live->live(b);
|
|
1705 |
IndexSetIterator elements(live);
|
|
1706 |
tty->print("{");
|
|
1707 |
uint i;
|
|
1708 |
while ((i = elements.next()) != 0) {
|
|
1709 |
tty->print("L%d ", Find_const(i));
|
|
1710 |
}
|
|
1711 |
tty->print_cr("}");
|
|
1712 |
}
|
|
1713 |
tty->print("\n");
|
|
1714 |
}
|
|
1715 |
|
|
1716 |
void PhaseChaitin::dump() const {
|
|
1717 |
tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
|
|
1718 |
_matcher._new_SP, _framesize );
|
|
1719 |
|
|
1720 |
// For all blocks
|
|
1721 |
for( uint i = 0; i < _cfg._num_blocks; i++ )
|
|
1722 |
dump(_cfg._blocks[i]);
|
|
1723 |
// End of per-block dump
|
|
1724 |
tty->print("\n");
|
|
1725 |
|
|
1726 |
if (!_ifg) {
|
|
1727 |
tty->print("(No IFG.)\n");
|
|
1728 |
return;
|
|
1729 |
}
|
|
1730 |
|
|
1731 |
// Dump LRG array
|
|
1732 |
tty->print("--- Live RanGe Array ---\n");
|
|
1733 |
for(uint i2 = 1; i2 < _maxlrg; i2++ ) {
|
|
1734 |
tty->print("L%d: ",i2);
|
|
1735 |
if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( );
|
|
1736 |
else tty->print("new LRG");
|
|
1737 |
}
|
|
1738 |
tty->print_cr("");
|
|
1739 |
|
|
1740 |
// Dump lo-degree list
|
|
1741 |
tty->print("Lo degree: ");
|
|
1742 |
for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
|
|
1743 |
tty->print("L%d ",i3);
|
|
1744 |
tty->print_cr("");
|
|
1745 |
|
|
1746 |
// Dump lo-stk-degree list
|
|
1747 |
tty->print("Lo stk degree: ");
|
|
1748 |
for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
|
|
1749 |
tty->print("L%d ",i4);
|
|
1750 |
tty->print_cr("");
|
|
1751 |
|
|
1752 |
// Dump lo-degree list
|
|
1753 |
tty->print("Hi degree: ");
|
|
1754 |
for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
|
|
1755 |
tty->print("L%d ",i5);
|
|
1756 |
tty->print_cr("");
|
|
1757 |
}
|
|
1758 |
|
|
1759 |
//------------------------------dump_degree_lists------------------------------
|
|
1760 |
void PhaseChaitin::dump_degree_lists() const {
|
|
1761 |
// Dump lo-degree list
|
|
1762 |
tty->print("Lo degree: ");
|
|
1763 |
for( uint i = _lo_degree; i; i = lrgs(i)._next )
|
|
1764 |
tty->print("L%d ",i);
|
|
1765 |
tty->print_cr("");
|
|
1766 |
|
|
1767 |
// Dump lo-stk-degree list
|
|
1768 |
tty->print("Lo stk degree: ");
|
|
1769 |
for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
|
|
1770 |
tty->print("L%d ",i2);
|
|
1771 |
tty->print_cr("");
|
|
1772 |
|
|
1773 |
// Dump lo-degree list
|
|
1774 |
tty->print("Hi degree: ");
|
|
1775 |
for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
|
|
1776 |
tty->print("L%d ",i3);
|
|
1777 |
tty->print_cr("");
|
|
1778 |
}
|
|
1779 |
|
|
1780 |
//------------------------------dump_simplified--------------------------------
|
|
1781 |
void PhaseChaitin::dump_simplified() const {
|
|
1782 |
tty->print("Simplified: ");
|
|
1783 |
for( uint i = _simplified; i; i = lrgs(i)._next )
|
|
1784 |
tty->print("L%d ",i);
|
|
1785 |
tty->print_cr("");
|
|
1786 |
}
|
|
1787 |
|
|
1788 |
static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
|
|
1789 |
if ((int)reg < 0)
|
|
1790 |
sprintf(buf, "<OptoReg::%d>", (int)reg);
|
|
1791 |
else if (OptoReg::is_reg(reg))
|
|
1792 |
strcpy(buf, Matcher::regName[reg]);
|
|
1793 |
else
|
|
1794 |
sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
|
|
1795 |
pc->reg2offset(reg));
|
|
1796 |
return buf+strlen(buf);
|
|
1797 |
}
|
|
1798 |
|
|
1799 |
//------------------------------dump_register----------------------------------
|
|
1800 |
// Dump a register name into a buffer. Be intelligent if we get called
|
|
1801 |
// before allocation is complete.
|
|
1802 |
char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
|
|
1803 |
if( !this ) { // Not got anything?
|
|
1804 |
sprintf(buf,"N%d",n->_idx); // Then use Node index
|
|
1805 |
} else if( _node_regs ) {
|
|
1806 |
// Post allocation, use direct mappings, no LRG info available
|
|
1807 |
print_reg( get_reg_first(n), this, buf );
|
|
1808 |
} else {
|
|
1809 |
uint lidx = Find_const(n); // Grab LRG number
|
|
1810 |
if( !_ifg ) {
|
|
1811 |
sprintf(buf,"L%d",lidx); // No register binding yet
|
|
1812 |
} else if( !lidx ) { // Special, not allocated value
|
|
1813 |
strcpy(buf,"Special");
|
|
1814 |
} else if( (lrgs(lidx).num_regs() == 1)
|
|
1815 |
? !lrgs(lidx).mask().is_bound1()
|
|
1816 |
: !lrgs(lidx).mask().is_bound2() ) {
|
|
1817 |
sprintf(buf,"L%d",lidx); // No register binding yet
|
|
1818 |
} else { // Hah! We have a bound machine register
|
|
1819 |
print_reg( lrgs(lidx).reg(), this, buf );
|
|
1820 |
}
|
|
1821 |
}
|
|
1822 |
return buf+strlen(buf);
|
|
1823 |
}
|
|
1824 |
|
|
1825 |
//----------------------dump_for_spill_split_recycle--------------------------
|
|
1826 |
void PhaseChaitin::dump_for_spill_split_recycle() const {
|
|
1827 |
if( WizardMode && (PrintCompilation || PrintOpto) ) {
|
|
1828 |
// Display which live ranges need to be split and the allocator's state
|
|
1829 |
tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
|
|
1830 |
for( uint bidx = 1; bidx < _maxlrg; bidx++ ) {
|
|
1831 |
if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
|
|
1832 |
tty->print("L%d: ", bidx);
|
|
1833 |
lrgs(bidx).dump();
|
|
1834 |
}
|
|
1835 |
}
|
|
1836 |
tty->cr();
|
|
1837 |
dump();
|
|
1838 |
}
|
|
1839 |
}
|
|
1840 |
|
|
1841 |
//------------------------------dump_frame------------------------------------
|
|
1842 |
void PhaseChaitin::dump_frame() const {
|
|
1843 |
const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
|
|
1844 |
const TypeTuple *domain = C->tf()->domain();
|
|
1845 |
const int argcnt = domain->cnt() - TypeFunc::Parms;
|
|
1846 |
|
|
1847 |
// Incoming arguments in registers dump
|
|
1848 |
for( int k = 0; k < argcnt; k++ ) {
|
|
1849 |
OptoReg::Name parmreg = _matcher._parm_regs[k].first();
|
|
1850 |
if( OptoReg::is_reg(parmreg)) {
|
|
1851 |
const char *reg_name = OptoReg::regname(parmreg);
|
|
1852 |
tty->print("#r%3.3d %s", parmreg, reg_name);
|
|
1853 |
parmreg = _matcher._parm_regs[k].second();
|
|
1854 |
if( OptoReg::is_reg(parmreg)) {
|
|
1855 |
tty->print(":%s", OptoReg::regname(parmreg));
|
|
1856 |
}
|
|
1857 |
tty->print(" : parm %d: ", k);
|
|
1858 |
domain->field_at(k + TypeFunc::Parms)->dump();
|
|
1859 |
tty->print_cr("");
|
|
1860 |
}
|
|
1861 |
}
|
|
1862 |
|
|
1863 |
// Check for un-owned padding above incoming args
|
|
1864 |
OptoReg::Name reg = _matcher._new_SP;
|
|
1865 |
if( reg > _matcher._in_arg_limit ) {
|
|
1866 |
reg = OptoReg::add(reg, -1);
|
|
1867 |
tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
|
|
1868 |
}
|
|
1869 |
|
|
1870 |
// Incoming argument area dump
|
|
1871 |
OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
|
|
1872 |
while( reg > begin_in_arg ) {
|
|
1873 |
reg = OptoReg::add(reg, -1);
|
|
1874 |
tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
|
|
1875 |
int j;
|
|
1876 |
for( j = 0; j < argcnt; j++) {
|
|
1877 |
if( _matcher._parm_regs[j].first() == reg ||
|
|
1878 |
_matcher._parm_regs[j].second() == reg ) {
|
|
1879 |
tty->print("parm %d: ",j);
|
|
1880 |
domain->field_at(j + TypeFunc::Parms)->dump();
|
|
1881 |
tty->print_cr("");
|
|
1882 |
break;
|
|
1883 |
}
|
|
1884 |
}
|
|
1885 |
if( j >= argcnt )
|
|
1886 |
tty->print_cr("HOLE, owned by SELF");
|
|
1887 |
}
|
|
1888 |
|
|
1889 |
// Old outgoing preserve area
|
|
1890 |
while( reg > _matcher._old_SP ) {
|
|
1891 |
reg = OptoReg::add(reg, -1);
|
|
1892 |
tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
|
|
1893 |
}
|
|
1894 |
|
|
1895 |
// Old SP
|
|
1896 |
tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
|
|
1897 |
reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
|
|
1898 |
|
|
1899 |
// Preserve area dump
|
|
1900 |
reg = OptoReg::add(reg, -1);
|
|
1901 |
while( OptoReg::is_stack(reg)) {
|
|
1902 |
tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
|
|
1903 |
if( _matcher.return_addr() == reg )
|
|
1904 |
tty->print_cr("return address");
|
|
1905 |
else if( _matcher.return_addr() == OptoReg::add(reg,1) &&
|
|
1906 |
VerifyStackAtCalls )
|
|
1907 |
tty->print_cr("0xBADB100D +VerifyStackAtCalls");
|
|
1908 |
else if ((int)OptoReg::reg2stack(reg) < C->fixed_slots())
|
|
1909 |
tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
|
|
1910 |
else
|
|
1911 |
tty->print_cr("pad2, in_preserve");
|
|
1912 |
reg = OptoReg::add(reg, -1);
|
|
1913 |
}
|
|
1914 |
|
|
1915 |
// Spill area dump
|
|
1916 |
reg = OptoReg::add(_matcher._new_SP, _framesize );
|
|
1917 |
while( reg > _matcher._out_arg_limit ) {
|
|
1918 |
reg = OptoReg::add(reg, -1);
|
|
1919 |
tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
|
|
1920 |
}
|
|
1921 |
|
|
1922 |
// Outgoing argument area dump
|
|
1923 |
while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
|
|
1924 |
reg = OptoReg::add(reg, -1);
|
|
1925 |
tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
|
|
1926 |
}
|
|
1927 |
|
|
1928 |
// Outgoing new preserve area
|
|
1929 |
while( reg > _matcher._new_SP ) {
|
|
1930 |
reg = OptoReg::add(reg, -1);
|
|
1931 |
tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
|
|
1932 |
}
|
|
1933 |
tty->print_cr("#");
|
|
1934 |
}
|
|
1935 |
|
|
1936 |
//------------------------------dump_bb----------------------------------------
|
|
1937 |
void PhaseChaitin::dump_bb( uint pre_order ) const {
|
|
1938 |
tty->print_cr("---dump of B%d---",pre_order);
|
|
1939 |
for( uint i = 0; i < _cfg._num_blocks; i++ ) {
|
|
1940 |
Block *b = _cfg._blocks[i];
|
|
1941 |
if( b->_pre_order == pre_order )
|
|
1942 |
dump(b);
|
|
1943 |
}
|
|
1944 |
}
|
|
1945 |
|
|
1946 |
//------------------------------dump_lrg---------------------------------------
|
|
1947 |
void PhaseChaitin::dump_lrg( uint lidx ) const {
|
|
1948 |
tty->print_cr("---dump of L%d---",lidx);
|
|
1949 |
|
|
1950 |
if( _ifg ) {
|
|
1951 |
if( lidx >= _maxlrg ) {
|
|
1952 |
tty->print("Attempt to print live range index beyond max live range.\n");
|
|
1953 |
return;
|
|
1954 |
}
|
|
1955 |
tty->print("L%d: ",lidx);
|
|
1956 |
lrgs(lidx).dump( );
|
|
1957 |
}
|
|
1958 |
if( _ifg ) { tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
|
|
1959 |
_ifg->neighbors(lidx)->dump();
|
|
1960 |
tty->cr();
|
|
1961 |
}
|
|
1962 |
// For all blocks
|
|
1963 |
for( uint i = 0; i < _cfg._num_blocks; i++ ) {
|
|
1964 |
Block *b = _cfg._blocks[i];
|
|
1965 |
int dump_once = 0;
|
|
1966 |
|
|
1967 |
// For all instructions
|
|
1968 |
for( uint j = 0; j < b->_nodes.size(); j++ ) {
|
|
1969 |
Node *n = b->_nodes[j];
|
|
1970 |
if( Find_const(n) == lidx ) {
|
|
1971 |
if( !dump_once++ ) {
|
|
1972 |
tty->cr();
|
|
1973 |
b->dump_head( &_cfg._bbs );
|
|
1974 |
}
|
|
1975 |
dump(n);
|
|
1976 |
continue;
|
|
1977 |
}
|
|
1978 |
uint cnt = n->req();
|
|
1979 |
for( uint k = 1; k < cnt; k++ ) {
|
|
1980 |
Node *m = n->in(k);
|
|
1981 |
if (!m) continue; // be robust in the dumper
|
|
1982 |
if( Find_const(m) == lidx ) {
|
|
1983 |
if( !dump_once++ ) {
|
|
1984 |
tty->cr();
|
|
1985 |
b->dump_head( &_cfg._bbs );
|
|
1986 |
}
|
|
1987 |
dump(n);
|
|
1988 |
}
|
|
1989 |
}
|
|
1990 |
}
|
|
1991 |
} // End of per-block dump
|
|
1992 |
tty->cr();
|
|
1993 |
}
|
|
1994 |
#endif // not PRODUCT
|
|
1995 |
|
|
1996 |
//------------------------------print_chaitin_statistics-------------------------------
|
|
1997 |
int PhaseChaitin::_final_loads = 0;
|
|
1998 |
int PhaseChaitin::_final_stores = 0;
|
|
1999 |
int PhaseChaitin::_final_memoves= 0;
|
|
2000 |
int PhaseChaitin::_final_copies = 0;
|
|
2001 |
double PhaseChaitin::_final_load_cost = 0;
|
|
2002 |
double PhaseChaitin::_final_store_cost = 0;
|
|
2003 |
double PhaseChaitin::_final_memove_cost= 0;
|
|
2004 |
double PhaseChaitin::_final_copy_cost = 0;
|
|
2005 |
int PhaseChaitin::_conserv_coalesce = 0;
|
|
2006 |
int PhaseChaitin::_conserv_coalesce_pair = 0;
|
|
2007 |
int PhaseChaitin::_conserv_coalesce_trie = 0;
|
|
2008 |
int PhaseChaitin::_conserv_coalesce_quad = 0;
|
|
2009 |
int PhaseChaitin::_post_alloc = 0;
|
|
2010 |
int PhaseChaitin::_lost_opp_pp_coalesce = 0;
|
|
2011 |
int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
|
|
2012 |
int PhaseChaitin::_used_cisc_instructions = 0;
|
|
2013 |
int PhaseChaitin::_unused_cisc_instructions = 0;
|
|
2014 |
int PhaseChaitin::_allocator_attempts = 0;
|
|
2015 |
int PhaseChaitin::_allocator_successes = 0;
|
|
2016 |
|
|
2017 |
#ifndef PRODUCT
|
|
2018 |
uint PhaseChaitin::_high_pressure = 0;
|
|
2019 |
uint PhaseChaitin::_low_pressure = 0;
|
|
2020 |
|
|
2021 |
void PhaseChaitin::print_chaitin_statistics() {
|
|
2022 |
tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
|
|
2023 |
tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
|
|
2024 |
tty->print_cr("Adjusted spill cost = %7.0f.",
|
|
2025 |
_final_load_cost*4.0 + _final_store_cost * 2.0 +
|
|
2026 |
_final_copy_cost*1.0 + _final_memove_cost*12.0);
|
|
2027 |
tty->print("Conservatively coalesced %d copies, %d pairs",
|
|
2028 |
_conserv_coalesce, _conserv_coalesce_pair);
|
|
2029 |
if( _conserv_coalesce_trie || _conserv_coalesce_quad )
|
|
2030 |
tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
|
|
2031 |
tty->print_cr(", %d post alloc.", _post_alloc);
|
|
2032 |
if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
|
|
2033 |
tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
|
|
2034 |
_lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
|
|
2035 |
if( _used_cisc_instructions || _unused_cisc_instructions )
|
|
2036 |
tty->print_cr("Used cisc instruction %d, remained in register %d",
|
|
2037 |
_used_cisc_instructions, _unused_cisc_instructions);
|
|
2038 |
if( _allocator_successes != 0 )
|
|
2039 |
tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
|
|
2040 |
tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
|
|
2041 |
}
|
|
2042 |
#endif // not PRODUCT
|