/*

 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "c1/c1_InstructionPrinter.hpp"

#include "c1/c1_LIR.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciInstance.hpp"

#include "runtime/sharedRuntime.hpp"

Register LIR_OprDesc::as_register() const {

  return FrameMap::cpu_rnr2reg(cpu_regnr());

}

Register LIR_OprDesc::as_register_lo() const {

  return FrameMap::cpu_rnr2reg(cpu_regnrLo());

}

Register LIR_OprDesc::as_register_hi() const {

  return FrameMap::cpu_rnr2reg(cpu_regnrHi());

}

#if defined(X86)

XMMRegister LIR_OprDesc::as_xmm_float_reg() const {

  return FrameMap::nr2xmmreg(xmm_regnr());

}

XMMRegister LIR_OprDesc::as_xmm_double_reg() const {

  assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");

  return FrameMap::nr2xmmreg(xmm_regnrLo());

}

#endif // X86

#if defined(SPARC) || defined(PPC)

FloatRegister LIR_OprDesc::as_float_reg() const {

  return FrameMap::nr2floatreg(fpu_regnr());

}

FloatRegister LIR_OprDesc::as_double_reg() const {

  return FrameMap::nr2floatreg(fpu_regnrHi());

}

#endif

#ifdef ARM

FloatRegister LIR_OprDesc::as_float_reg() const {

  return as_FloatRegister(fpu_regnr());

}

FloatRegister LIR_OprDesc::as_double_reg() const {

  return as_FloatRegister(fpu_regnrLo());

}

#endif

LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();

LIR_Opr LIR_OprFact::value_type(ValueType* type) {

  ValueTag tag = type->tag();

  switch (tag) {

  case metaDataTag : {

    ClassConstant* c = type->as_ClassConstant();

    if (c != NULL && !c->value()->is_loaded()) {

      return LIR_OprFact::metadataConst(NULL);

    } else if (c != NULL) {

      return LIR_OprFact::metadataConst(c->value()->constant_encoding());

    } else {

      MethodConstant* m = type->as_MethodConstant();

      assert (m != NULL, "not a class or a method?");

      return LIR_OprFact::metadataConst(m->value()->constant_encoding());

    }

  }

  case objectTag : {

      return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());

    }

  case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());

  case intTag    : return LIR_OprFact::intConst(type->as_IntConstant()->value());

  case floatTag  : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());

  case longTag   : return LIR_OprFact::longConst(type->as_LongConstant()->value());

  case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());

  default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);

  }

}

LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {

  switch (type->tag()) {

    case objectTag: return LIR_OprFact::oopConst(NULL);

    case addressTag:return LIR_OprFact::addressConst(0);

    case intTag:    return LIR_OprFact::intConst(0);

    case floatTag:  return LIR_OprFact::floatConst(0.0);

    case longTag:   return LIR_OprFact::longConst(0);

    case doubleTag: return LIR_OprFact::doubleConst(0.0);

    default:        ShouldNotReachHere(); return LIR_OprFact::intConst(-1);

  }

  return illegalOpr;

}

//---------------------------------------------------

LIR_Address::Scale LIR_Address::scale(BasicType type) {

  int elem_size = type2aelembytes(type);

  switch (elem_size) {

  case 1: return LIR_Address::times_1;

  case 2: return LIR_Address::times_2;

  case 4: return LIR_Address::times_4;

  case 8: return LIR_Address::times_8;

  }

  ShouldNotReachHere();

  return LIR_Address::times_1;

}

#ifndef PRODUCT

void LIR_Address::verify() const {

#if defined(SPARC) || defined(PPC)

  assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");

  assert(disp() == 0 || index()->is_illegal(), "can't have both");

#endif

#ifdef ARM

  assert(disp() == 0 || index()->is_illegal(), "can't have both");

  // Note: offsets higher than 4096 must not be rejected here. They can

  // be handled by the back-end or will be rejected if not.

#endif

#ifdef _LP64

  assert(base()->is_cpu_register(), "wrong base operand");

  assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");

  assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,

         "wrong type for addresses");

#else

  assert(base()->is_single_cpu(), "wrong base operand");

  assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");

  assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,

         "wrong type for addresses");

#endif

}

#endif

//---------------------------------------------------

char LIR_OprDesc::type_char(BasicType t) {

  switch (t) {

    case T_ARRAY:

      t = T_OBJECT;

    case T_BOOLEAN:

    case T_CHAR:

    case T_FLOAT:

    case T_DOUBLE:

    case T_BYTE:

    case T_SHORT:

    case T_INT:

    case T_LONG:

    case T_OBJECT:

    case T_ADDRESS:

    case T_METADATA:

    case T_VOID:

      return ::type2char(t);

    case T_ILLEGAL:

      return '?';

    default:

      ShouldNotReachHere();

      return '?';

  }

}

#ifndef PRODUCT

void LIR_OprDesc::validate_type() const {

#ifdef ASSERT

  if (!is_pointer() && !is_illegal()) {

    switch (as_BasicType(type_field())) {

    case T_LONG:

      assert((kind_field() == cpu_register || kind_field() == stack_value) &&

             size_field() == double_size, "must match");

      break;

    case T_FLOAT:

      // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)

      assert((kind_field() == fpu_register || kind_field() == stack_value

             ARM_ONLY(|| kind_field() == cpu_register)

             PPC_ONLY(|| kind_field() == cpu_register) ) &&

             size_field() == single_size, "must match");

      break;

    case T_DOUBLE:

      // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)

      assert((kind_field() == fpu_register || kind_field() == stack_value

             ARM_ONLY(|| kind_field() == cpu_register)

             PPC_ONLY(|| kind_field() == cpu_register) ) &&

             size_field() == double_size, "must match");

      break;

    case T_BOOLEAN:

    case T_CHAR:

    case T_BYTE:

    case T_SHORT:

    case T_INT:

    case T_ADDRESS:

    case T_OBJECT:

    case T_METADATA:

    case T_ARRAY:

      assert((kind_field() == cpu_register || kind_field() == stack_value) &&

             size_field() == single_size, "must match");

      break;

    case T_ILLEGAL:

      // XXX TKR also means unknown right now

      // assert(is_illegal(), "must match");

      break;

    default:

      ShouldNotReachHere();

    }

  }

#endif

}

#endif // PRODUCT

bool LIR_OprDesc::is_oop() const {

  if (is_pointer()) {

    return pointer()->is_oop_pointer();

  } else {

    OprType t= type_field();

    assert(t != unknown_type, "not set");

    return t == object_type;

  }

}

void LIR_Op2::verify() const {

#ifdef ASSERT

  switch (code()) {

    case lir_cmove:

    case lir_xchg:

      break;

    default:

      assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),

             "can't produce oops from arith");

  }

  if (TwoOperandLIRForm) {

    switch (code()) {

    case lir_add:

    case lir_sub:

    case lir_mul:

    case lir_mul_strictfp:

    case lir_div:

    case lir_div_strictfp:

    case lir_rem:

    case lir_logic_and:

    case lir_logic_or:

    case lir_logic_xor:

    case lir_shl:

    case lir_shr:

      assert(in_opr1() == result_opr(), "opr1 and result must match");

      assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");

      break;

    // special handling for lir_ushr because of write barriers

    case lir_ushr:

      assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");

      assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");

      break;

    }

  }

#endif

}

LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)

  : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)

  , _cond(cond)

  , _type(type)

  , _label(block->label())

  , _block(block)

  , _ublock(NULL)

  , _stub(NULL) {

}

LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :

  LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)

  , _cond(cond)

  , _type(type)

  , _label(stub->entry())

  , _block(NULL)

  , _ublock(NULL)

  , _stub(stub) {

}

LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)

  : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)

  , _cond(cond)

  , _type(type)

  , _label(block->label())

  , _block(block)

  , _ublock(ublock)

  , _stub(NULL)

{

}

void LIR_OpBranch::change_block(BlockBegin* b) {

  assert(_block != NULL, "must have old block");

  assert(_block->label() == label(), "must be equal");

  _block = b;

  _label = b->label();

}

void LIR_OpBranch::change_ublock(BlockBegin* b) {

  assert(_ublock != NULL, "must have old block");

  _ublock = b;

}

void LIR_OpBranch::negate_cond() {

  switch (_cond) {

    case lir_cond_equal:        _cond = lir_cond_notEqual;     break;

    case lir_cond_notEqual:     _cond = lir_cond_equal;        break;

    case lir_cond_less:         _cond = lir_cond_greaterEqual; break;

    case lir_cond_lessEqual:    _cond = lir_cond_greater;      break;

    case lir_cond_greaterEqual: _cond = lir_cond_less;         break;

    case lir_cond_greater:      _cond = lir_cond_lessEqual;    break;

    default: ShouldNotReachHere();

  }

}

LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,

                                 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,

                                 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,

                                 CodeStub* stub)

  : LIR_Op(code, result, NULL)

  , _object(object)

  , _array(LIR_OprFact::illegalOpr)

  , _klass(klass)

  , _tmp1(tmp1)

  , _tmp2(tmp2)

  , _tmp3(tmp3)

  , _fast_check(fast_check)

  , _stub(stub)

  , _info_for_patch(info_for_patch)

  , _info_for_exception(info_for_exception)

  , _profiled_method(NULL)

  , _profiled_bci(-1)

  , _should_profile(false)

{

  if (code == lir_checkcast) {

    assert(info_for_exception != NULL, "checkcast throws exceptions");

  } else if (code == lir_instanceof) {

    assert(info_for_exception == NULL, "instanceof throws no exceptions");

  } else {

    ShouldNotReachHere();

  }

}

LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)

  : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)

  , _object(object)

  , _array(array)

  , _klass(NULL)

  , _tmp1(tmp1)

  , _tmp2(tmp2)

  , _tmp3(tmp3)

  , _fast_check(false)

  , _stub(NULL)

  , _info_for_patch(NULL)

  , _info_for_exception(info_for_exception)

  , _profiled_method(NULL)

  , _profiled_bci(-1)

  , _should_profile(false)

{

  if (code == lir_store_check) {

    _stub = new ArrayStoreExceptionStub(object, info_for_exception);

    assert(info_for_exception != NULL, "store_check throws exceptions");

  } else {

    ShouldNotReachHere();

  }

}

LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,

                                 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)

  : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)

  , _tmp(tmp)

  , _src(src)

  , _src_pos(src_pos)

  , _dst(dst)

  , _dst_pos(dst_pos)

  , _flags(flags)

  , _expected_type(expected_type)

  , _length(length) {

  _stub = new ArrayCopyStub(this);

}

//-------------------verify--------------------------

void LIR_Op1::verify() const {

  switch(code()) {

  case lir_move:

    assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");

    break;

  case lir_null_check:

    assert(in_opr()->is_register(), "must be");

    break;

  case lir_return:

    assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");

    break;

  }

}

void LIR_OpRTCall::verify() const {

  assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");

}

//-------------------visits--------------------------

// complete rework of LIR instruction visitor.

// The virtual calls for each instruction type is replaced by a big

// switch that adds the operands for each instruction

void LIR_OpVisitState::visit(LIR_Op* op) {

  // copy information from the LIR_Op

  reset();

  set_op(op);

  switch (op->code()) {

// LIR_Op0

    case lir_word_align:               // result and info always invalid

    case lir_backwardbranch_target:    // result and info always invalid

    case lir_build_frame:              // result and info always invalid

    case lir_fpop_raw:                 // result and info always invalid

    case lir_24bit_FPU:                // result and info always invalid

    case lir_reset_FPU:                // result and info always invalid

    case lir_breakpoint:               // result and info always invalid

    case lir_membar:                   // result and info always invalid

    case lir_membar_acquire:           // result and info always invalid

    case lir_membar_release:           // result and info always invalid

    case lir_membar_loadload:          // result and info always invalid

    case lir_membar_storestore:        // result and info always invalid

    case lir_membar_loadstore:         // result and info always invalid

    case lir_membar_storeload:         // result and info always invalid

    {

      assert(op->as_Op0() != NULL, "must be");

      assert(op->_info == NULL, "info not used by this instruction");

      assert(op->_result->is_illegal(), "not used");

      break;

    }

    case lir_nop:                      // may have info, result always invalid

    case lir_std_entry:                // may have result, info always invalid

    case lir_osr_entry:                // may have result, info always invalid

    case lir_get_thread:               // may have result, info always invalid

    {

      assert(op->as_Op0() != NULL, "must be");

      if (op->_info != NULL)           do_info(op->_info);

      if (op->_result->is_valid())     do_output(op->_result);

      break;

    }

// LIR_OpLabel

    case lir_label:                    // result and info always invalid

    {

      assert(op->as_OpLabel() != NULL, "must be");

      assert(op->_info == NULL, "info not used by this instruction");

      assert(op->_result->is_illegal(), "not used");

      break;

    }

// LIR_Op1

    case lir_fxch:           // input always valid, result and info always invalid

    case lir_fld:            // input always valid, result and info always invalid

    case lir_ffree:          // input always valid, result and info always invalid

    case lir_push:           // input always valid, result and info always invalid

    case lir_pop:            // input always valid, result and info always invalid

    case lir_return:         // input always valid, result and info always invalid

    case lir_leal:           // input and result always valid, info always invalid

    case lir_neg:            // input and result always valid, info always invalid