author | kvn |
Wed, 14 Jul 2010 14:29:14 -0700 | |
changeset 5927 | 1e309b7d96b0 |
parent 5902 | ba0c3b725081 |
child 6459 | 3d75ed40a975 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2010, Oracle and/or its affiliates. All Rights Reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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class VM_Version : public Abstract_VM_Version { |
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public: |
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// cpuid result register layouts. These are all unions of a uint32_t |
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// (in case anyone wants access to the register as a whole) and a bitfield. |
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||
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union StdCpuid1Eax { |
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uint32_t value; |
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struct { |
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uint32_t stepping : 4, |
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model : 4, |
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family : 4, |
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proc_type : 2, |
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: 2, |
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ext_model : 4, |
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ext_family : 8, |
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: 4; |
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} bits; |
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}; |
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||
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union StdCpuid1Ebx { // example, unused |
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uint32_t value; |
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struct { |
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uint32_t brand_id : 8, |
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clflush_size : 8, |
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threads_per_cpu : 8, |
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apic_id : 8; |
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} bits; |
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}; |
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||
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union StdCpuid1Ecx { |
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uint32_t value; |
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struct { |
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uint32_t sse3 : 1, |
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: 2, |
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monitor : 1, |
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: 1, |
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vmx : 1, |
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: 1, |
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est : 1, |
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: 1, |
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ssse3 : 1, |
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cid : 1, |
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: 2, |
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cmpxchg16: 1, |
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: 4, |
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dca : 1, |
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sse4_1 : 1, |
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sse4_2 : 1, |
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: 2, |
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popcnt : 1, |
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: 8; |
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} bits; |
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}; |
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||
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union StdCpuid1Edx { |
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uint32_t value; |
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struct { |
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uint32_t : 4, |
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tsc : 1, |
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: 3, |
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cmpxchg8 : 1, |
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: 6, |
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cmov : 1, |
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: 7, |
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mmx : 1, |
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fxsr : 1, |
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sse : 1, |
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sse2 : 1, |
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: 1, |
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ht : 1, |
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: 3; |
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} bits; |
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}; |
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||
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union DcpCpuid4Eax { |
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uint32_t value; |
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struct { |
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uint32_t cache_type : 5, |
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: 21, |
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cores_per_cpu : 6; |
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} bits; |
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}; |
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||
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union DcpCpuid4Ebx { |
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uint32_t value; |
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struct { |
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uint32_t L1_line_size : 12, |
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partitions : 10, |
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associativity : 10; |
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} bits; |
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}; |
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union TplCpuidBEbx { |
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uint32_t value; |
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struct { |
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uint32_t logical_cpus : 16, |
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: 16; |
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} bits; |
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}; |
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||
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union ExtCpuid1Ecx { |
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uint32_t value; |
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struct { |
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uint32_t LahfSahf : 1, |
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CmpLegacy : 1, |
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: 4, |
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lzcnt : 1, |
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sse4a : 1, |
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misalignsse : 1, |
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prefetchw : 1, |
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: 22; |
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} bits; |
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}; |
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||
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union ExtCpuid1Edx { |
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uint32_t value; |
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struct { |
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uint32_t : 22, |
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mmx_amd : 1, |
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mmx : 1, |
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fxsr : 1, |
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: 4, |
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long_mode : 1, |
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tdnow2 : 1, |
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tdnow : 1; |
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} bits; |
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}; |
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||
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union ExtCpuid5Ex { |
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uint32_t value; |
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struct { |
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uint32_t L1_line_size : 8, |
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L1_tag_lines : 8, |
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L1_assoc : 8, |
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L1_size : 8; |
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} bits; |
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}; |
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||
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union ExtCpuid8Ecx { |
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uint32_t value; |
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struct { |
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uint32_t cores_per_cpu : 8, |
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: 24; |
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} bits; |
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}; |
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||
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protected: |
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static int _cpu; |
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static int _model; |
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static int _stepping; |
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static int _cpuFeatures; // features returned by the "cpuid" instruction |
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// 0 if this instruction is not available |
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static const char* _features_str; |
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||
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enum { |
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CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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CPU_CMOV = (1 << 1), |
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CPU_FXSR = (1 << 2), |
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CPU_HT = (1 << 3), |
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CPU_MMX = (1 << 4), |
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CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX) |
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CPU_SSE = (1 << 6), |
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CPU_SSE2 = (1 << 7), |
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CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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CPU_SSSE3 = (1 << 9), |
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CPU_SSE4A = (1 << 10), |
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CPU_SSE4_1 = (1 << 11), |
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CPU_SSE4_2 = (1 << 12), |
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CPU_POPCNT = (1 << 13), |
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CPU_LZCNT = (1 << 14) |
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} cpuFeatureFlags; |
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||
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// cpuid information block. All info derived from executing cpuid with |
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// various function numbers is stored here. Intel and AMD info is |
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// merged in this block: accessor methods disentangle it. |
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// |
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// The info block is laid out in subblocks of 4 dwords corresponding to |
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// eax, ebx, ecx and edx, whether or not they contain anything useful. |
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struct CpuidInfo { |
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// cpuid function 0 |
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uint32_t std_max_function; |
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uint32_t std_vendor_name_0; |
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uint32_t std_vendor_name_1; |
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uint32_t std_vendor_name_2; |
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||
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// cpuid function 1 |
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StdCpuid1Eax std_cpuid1_eax; |
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StdCpuid1Ebx std_cpuid1_ebx; |
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StdCpuid1Ecx std_cpuid1_ecx; |
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StdCpuid1Edx std_cpuid1_edx; |
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// cpuid function 4 (deterministic cache parameters) |
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DcpCpuid4Eax dcp_cpuid4_eax; |
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DcpCpuid4Ebx dcp_cpuid4_ebx; |
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uint32_t dcp_cpuid4_ecx; // unused currently |
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uint32_t dcp_cpuid4_edx; // unused currently |
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||
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// cpuid function 0xB (processor topology) |
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// ecx = 0 |
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uint32_t tpl_cpuidB0_eax; |
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TplCpuidBEbx tpl_cpuidB0_ebx; |
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uint32_t tpl_cpuidB0_ecx; // unused currently |
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uint32_t tpl_cpuidB0_edx; // unused currently |
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// ecx = 1 |
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uint32_t tpl_cpuidB1_eax; |
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TplCpuidBEbx tpl_cpuidB1_ebx; |
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uint32_t tpl_cpuidB1_ecx; // unused currently |
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uint32_t tpl_cpuidB1_edx; // unused currently |
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// ecx = 2 |
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uint32_t tpl_cpuidB2_eax; |
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TplCpuidBEbx tpl_cpuidB2_ebx; |
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uint32_t tpl_cpuidB2_ecx; // unused currently |
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uint32_t tpl_cpuidB2_edx; // unused currently |
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// cpuid function 0x80000000 // example, unused |
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uint32_t ext_max_function; |
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uint32_t ext_vendor_name_0; |
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uint32_t ext_vendor_name_1; |
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uint32_t ext_vendor_name_2; |
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// cpuid function 0x80000001 |
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uint32_t ext_cpuid1_eax; // reserved |
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uint32_t ext_cpuid1_ebx; // reserved |
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ExtCpuid1Ecx ext_cpuid1_ecx; |
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ExtCpuid1Edx ext_cpuid1_edx; |
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// cpuid functions 0x80000002 thru 0x80000004: example, unused |
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uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; |
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uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; |
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uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; |
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// cpuid function 0x80000005 //AMD L1, Intel reserved |
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uint32_t ext_cpuid5_eax; // unused currently |
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uint32_t ext_cpuid5_ebx; // reserved |
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ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) |
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ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) |
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||
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// cpuid function 0x80000008 |
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uint32_t ext_cpuid8_eax; // unused currently |
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uint32_t ext_cpuid8_ebx; // reserved |
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ExtCpuid8Ecx ext_cpuid8_ecx; |
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uint32_t ext_cpuid8_edx; // reserved |
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}; |
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||
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// The actual cpuid info block |
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static CpuidInfo _cpuid_info; |
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// Extractors and predicates |
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static uint32_t extended_cpu_family() { |
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uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; |
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result += _cpuid_info.std_cpuid1_eax.bits.ext_family; |
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return result; |
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} |
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static uint32_t extended_cpu_model() { |
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uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; |
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result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; |
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return result; |
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} |
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static uint32_t cpu_stepping() { |
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uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; |
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return result; |
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} |
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static uint logical_processor_count() { |
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uint result = threads_per_core(); |
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return result; |
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} |
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static uint32_t feature_flags() { |
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uint32_t result = 0; |
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if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) |
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result |= CPU_CX8; |
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297 |
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) |
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298 |
result |= CPU_CMOV; |
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299 |
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || is_amd() && |
|
300 |
_cpuid_info.ext_cpuid1_edx.bits.fxsr != 0) |
|
301 |
result |= CPU_FXSR; |
|
302 |
// HT flag is set for multi-core processors also. |
|
303 |
if (threads_per_core() > 1) |
|
304 |
result |= CPU_HT; |
|
305 |
if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || is_amd() && |
|
306 |
_cpuid_info.ext_cpuid1_edx.bits.mmx != 0) |
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307 |
result |= CPU_MMX; |
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308 |
if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) |
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309 |
result |= CPU_SSE; |
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310 |
if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) |
|
311 |
result |= CPU_SSE2; |
|
312 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) |
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313 |
result |= CPU_SSE3; |
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314 |
if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) |
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315 |
result |= CPU_SSSE3; |
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316 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) |
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317 |
result |= CPU_SSE4_1; |
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318 |
if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) |
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result |= CPU_SSE4_2; |
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if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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result |= CPU_POPCNT; |
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|
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// AMD features. |
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if (is_amd()) { |
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if (_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) |
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result |= CPU_3DNOW; |
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if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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result |= CPU_LZCNT; |
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if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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result |= CPU_SSE4A; |
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331 |
} |
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332 |
|
2111 | 333 |
return result; |
334 |
} |
|
335 |
||
336 |
static void get_processor_features(); |
|
337 |
||
338 |
public: |
|
339 |
// Offsets for cpuid asm stub |
|
340 |
static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } |
|
341 |
static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } |
|
342 |
static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } |
|
343 |
static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
|
344 |
static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } |
|
345 |
static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
|
5902 | 346 |
static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
347 |
static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } |
|
348 |
static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } |
|
2111 | 349 |
|
350 |
// Initialization |
|
351 |
static void initialize(); |
|
352 |
||
353 |
// Asserts |
|
354 |
static void assert_is_initialized() { |
|
355 |
assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); |
|
356 |
} |
|
357 |
||
358 |
// |
|
359 |
// Processor family: |
|
360 |
// 3 - 386 |
|
361 |
// 4 - 486 |
|
362 |
// 5 - Pentium |
|
363 |
// 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, |
|
364 |
// Pentium M, Core Solo, Core Duo, Core2 Duo |
|
365 |
// family 6 model: 9, 13, 14, 15 |
|
366 |
// 0x0f - Pentium 4, Opteron |
|
367 |
// |
|
368 |
// Note: The cpu family should be used to select between |
|
369 |
// instruction sequences which are valid on all Intel |
|
370 |
// processors. Use the feature test functions below to |
|
371 |
// determine whether a particular instruction is supported. |
|
372 |
// |
|
373 |
static int cpu_family() { return _cpu;} |
|
374 |
static bool is_P6() { return cpu_family() >= 6; } |
|
375 |
||
376 |
static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' |
|
377 |
static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' |
|
378 |
||
5927 | 379 |
static bool supports_processor_topology() { |
380 |
return (_cpuid_info.std_max_function >= 0xB) && |
|
381 |
// eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. |
|
382 |
// Some cpus have max cpuid >= 0xB but do not support processor topology. |
|
383 |
((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
|
384 |
} |
|
385 |
||
2111 | 386 |
static uint cores_per_cpu() { |
387 |
uint result = 1; |
|
388 |
if (is_intel()) { |
|
5927 | 389 |
if (supports_processor_topology()) { |
5902 | 390 |
result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
391 |
_cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
|
392 |
} else { |
|
393 |
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); |
|
394 |
} |
|
2111 | 395 |
} else if (is_amd()) { |
396 |
result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); |
|
397 |
} |
|
398 |
return result; |
|
399 |
} |
|
400 |
||
401 |
static uint threads_per_core() { |
|
402 |
uint result = 1; |
|
5927 | 403 |
if (is_intel() && supports_processor_topology()) { |
5902 | 404 |
result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
405 |
} else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { |
|
2111 | 406 |
result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
407 |
cores_per_cpu(); |
|
408 |
} |
|
409 |
return result; |
|
410 |
} |
|
411 |
||
412 |
static intx L1_data_cache_line_size() { |
|
413 |
intx result = 0; |
|
414 |
if (is_intel()) { |
|
415 |
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); |
|
416 |
} else if (is_amd()) { |
|
417 |
result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; |
|
418 |
} |
|
419 |
if (result < 32) // not defined ? |
|
420 |
result = 32; // 32 bytes by default on x86 and other x64 |
|
421 |
return result; |
|
422 |
} |
|
423 |
||
424 |
// |
|
425 |
// Feature identification |
|
426 |
// |
|
427 |
static bool supports_cpuid() { return _cpuFeatures != 0; } |
|
428 |
static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } |
|
429 |
static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } |
|
430 |
static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } |
|
431 |
static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } |
|
432 |
static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } |
|
433 |
static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } |
|
434 |
static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } |
|
435 |
static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } |
|
436 |
static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } |
|
437 |
static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } |
|
438 |
static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
439 |
static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
2111 | 440 |
// |
441 |
// AMD features |
|
442 |
// |
|
443 |
static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; } |
|
444 |
static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
|
445 |
static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; } |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2255
diff
changeset
|
446 |
static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
2111 | 447 |
static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
448 |
||
449 |
static bool supports_compare_and_exchange() { return true; } |
|
450 |
||
451 |
static const char* cpu_features() { return _features_str; } |
|
452 |
||
453 |
static intx allocate_prefetch_distance() { |
|
454 |
// This method should be called before allocate_prefetch_style(). |
|
455 |
// |
|
456 |
// Hardware prefetching (distance/size in bytes): |
|
457 |
// Pentium 3 - 64 / 32 |
|
458 |
// Pentium 4 - 256 / 128 |
|
459 |
// Athlon - 64 / 32 ???? |
|
460 |
// Opteron - 128 / 64 only when 2 sequential cache lines accessed |
|
461 |
// Core - 128 / 64 |
|
462 |
// |
|
463 |
// Software prefetching (distance in bytes / instruction with best score): |
|
464 |
// Pentium 3 - 128 / prefetchnta |
|
465 |
// Pentium 4 - 512 / prefetchnta |
|
466 |
// Athlon - 128 / prefetchnta |
|
467 |
// Opteron - 256 / prefetchnta |
|
468 |
// Core - 256 / prefetchnta |
|
469 |
// It will be used only when AllocatePrefetchStyle > 0 |
|
470 |
||
471 |
intx count = AllocatePrefetchDistance; |
|
472 |
if (count < 0) { // default ? |
|
473 |
if (is_amd()) { // AMD |
|
474 |
if (supports_sse2()) |
|
475 |
count = 256; // Opteron |
|
476 |
else |
|
477 |
count = 128; // Athlon |
|
478 |
} else { // Intel |
|
479 |
if (supports_sse2()) |
|
480 |
if (cpu_family() == 6) { |
|
481 |
count = 256; // Pentium M, Core, Core2 |
|
482 |
} else { |
|
483 |
count = 512; // Pentium 4 |
|
484 |
} |
|
485 |
else |
|
486 |
count = 128; // Pentium 3 (and all other old CPUs) |
|
487 |
} |
|
488 |
} |
|
489 |
return count; |
|
490 |
} |
|
491 |
static intx allocate_prefetch_style() { |
|
492 |
assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); |
|
493 |
// Return 0 if AllocatePrefetchDistance was not defined. |
|
494 |
return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; |
|
495 |
} |
|
496 |
||
497 |
// Prefetch interval for gc copy/scan == 9 dcache lines. Derived from |
|
498 |
// 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. |
|
499 |
// Tested intervals from 128 to 2048 in increments of 64 == one cache line. |
|
500 |
// 256 bytes (4 dcache lines) was the nearest runner-up to 576. |
|
501 |
||
502 |
// gc copy/scan is disabled if prefetchw isn't supported, because |
|
503 |
// Prefetch::write emits an inlined prefetchw on Linux. |
|
504 |
// Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. |
|
505 |
// The used prefetcht0 instruction works for both amd64 and em64t. |
|
506 |
static intx prefetch_copy_interval_in_bytes() { |
|
507 |
intx interval = PrefetchCopyIntervalInBytes; |
|
508 |
return interval >= 0 ? interval : 576; |
|
509 |
} |
|
510 |
static intx prefetch_scan_interval_in_bytes() { |
|
511 |
intx interval = PrefetchScanIntervalInBytes; |
|
512 |
return interval >= 0 ? interval : 576; |
|
513 |
} |
|
514 |
static intx prefetch_fields_ahead() { |
|
515 |
intx count = PrefetchFieldsAhead; |
|
516 |
return count >= 0 ? count : 1; |
|
517 |
} |
|
518 |
}; |