/*

 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

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 */

#ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP

#define CPU_X86_VM_MACROASSEMBLER_X86_HPP

#include "asm/assembler.hpp"

#include "utilities/macros.hpp"

#include "runtime/rtmLocking.hpp"

// MacroAssembler extends Assembler by frequently used macros.

//

// Instructions for which a 'better' code sequence exists depending

// on arguments should also go in here.

class MacroAssembler: public Assembler {

  friend class LIR_Assembler;

  friend class Runtime1;      // as_Address()

 protected:

  Address as_Address(AddressLiteral adr);

  Address as_Address(ArrayAddress adr);

  // Support for VM calls

  //

  // This is the base routine called by the different versions of call_VM_leaf. The interpreter

  // may customize this version by overriding it for its purposes (e.g., to save/restore

  // additional registers when doing a VM call).

#ifdef CC_INTERP

  // c++ interpreter never wants to use interp_masm version of call_VM

  #define VIRTUAL

#else

  #define VIRTUAL virtual

#endif

  VIRTUAL void call_VM_leaf_base(

    address entry_point,               // the entry point

    int     number_of_arguments        // the number of arguments to pop after the call

  );

  // This is the base routine called by the different versions of call_VM. The interpreter

  // may customize this version by overriding it for its purposes (e.g., to save/restore

  // additional registers when doing a VM call).

  //

  // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base

  // returns the register which contains the thread upon return. If a thread register has been

  // specified, the return value will correspond to that register. If no last_java_sp is specified

  // (noreg) than rsp will be used instead.

  VIRTUAL void call_VM_base(           // returns the register containing the thread upon return

    Register oop_result,               // where an oop-result ends up if any; use noreg otherwise

    Register java_thread,              // the thread if computed before     ; use noreg otherwise

    Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise

    address  entry_point,              // the entry point

    int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call

    bool     check_exceptions          // whether to check for pending exceptions after return

  );

  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.

  // The implementation is only non-empty for the InterpreterMacroAssembler,

  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.

  virtual void check_and_handle_popframe(Register java_thread);

  virtual void check_and_handle_earlyret(Register java_thread);

  void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);

  // helpers for FPU flag access

  // tmp is a temporary register, if none is available use noreg

  void save_rax   (Register tmp);

  void restore_rax(Register tmp);

 public:

  MacroAssembler(CodeBuffer* code) : Assembler(code) {}

  // Support for NULL-checks

  //

  // Generates code that causes a NULL OS exception if the content of reg is NULL.

  // If the accessed location is M[reg + offset] and the offset is known, provide the

  // offset. No explicit code generation is needed if the offset is within a certain

  // range (0 <= offset <= page_size).

  void null_check(Register reg, int offset = -1);

  static bool needs_explicit_null_check(intptr_t offset);

  // Required platform-specific helpers for Label::patch_instructions.

  // They _shadow_ the declarations in AbstractAssembler, which are undefined.

  void pd_patch_instruction(address branch, address target) {

    unsigned char op = branch[0];

    assert(op == 0xE8 /* call */ ||

        op == 0xE9 /* jmp */ ||

        op == 0xEB /* short jmp */ ||

        (op & 0xF0) == 0x70 /* short jcc */ ||

        op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||

        op == 0xC7 && branch[1] == 0xF8 /* xbegin */,

        "Invalid opcode at patch point");

    if (op == 0xEB || (op & 0xF0) == 0x70) {

      // short offset operators (jmp and jcc)

      char* disp = (char*) &branch[1];

      int imm8 = target - (address) &disp[1];

      guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");

      *disp = imm8;

    } else {

      int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];

      int imm32 = target - (address) &disp[1];

      *disp = imm32;

    }

  }

  // The following 4 methods return the offset of the appropriate move instruction

  // Support for fast byte/short loading with zero extension (depending on particular CPU)

  int load_unsigned_byte(Register dst, Address src);

  int load_unsigned_short(Register dst, Address src);

  // Support for fast byte/short loading with sign extension (depending on particular CPU)

  int load_signed_byte(Register dst, Address src);

  int load_signed_short(Register dst, Address src);

  // Support for sign-extension (hi:lo = extend_sign(lo))

  void extend_sign(Register hi, Register lo);

  // Load and store values by size and signed-ness

  void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);

  void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);

  // Support for inc/dec with optimal instruction selection depending on value

  void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }

  void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }

  void decrementl(Address dst, int value = 1);

  void decrementl(Register reg, int value = 1);

  void decrementq(Register reg, int value = 1);

  void decrementq(Address dst, int value = 1);

  void incrementl(Address dst, int value = 1);

  void incrementl(Register reg, int value = 1);

  void incrementq(Register reg, int value = 1);

  void incrementq(Address dst, int value = 1);

  // Support optimal SSE move instructions.

  void movflt(XMMRegister dst, XMMRegister src) {

    if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }

    else                       { movss (dst, src); return; }

  }

  void movflt(XMMRegister dst, Address src) { movss(dst, src); }

  void movflt(XMMRegister dst, AddressLiteral src);

  void movflt(Address dst, XMMRegister src) { movss(dst, src); }

  void movdbl(XMMRegister dst, XMMRegister src) {

    if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }

    else                       { movsd (dst, src); return; }

  }

  void movdbl(XMMRegister dst, AddressLiteral src);

  void movdbl(XMMRegister dst, Address src) {

    if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }

    else                         { movlpd(dst, src); return; }

  }

  void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }

  void incrementl(AddressLiteral dst);

  void incrementl(ArrayAddress dst);

  void incrementq(AddressLiteral dst);

  // Alignment

  void align(int modulus);

  // A 5 byte nop that is safe for patching (see patch_verified_entry)

  void fat_nop();

  // Stack frame creation/removal

  void enter();

  void leave();

  // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)

  // The pointer will be loaded into the thread register.

  void get_thread(Register thread);

  // Support for VM calls

  //

  // It is imperative that all calls into the VM are handled via the call_VM macros.

  // They make sure that the stack linkage is setup correctly. call_VM's correspond

  // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.

  void call_VM(Register oop_result,

               address entry_point,

               bool check_exceptions = true);

  void call_VM(Register oop_result,

               address entry_point,

               Register arg_1,

               bool check_exceptions = true);

  void call_VM(Register oop_result,

               address entry_point,

               Register arg_1, Register arg_2,

               bool check_exceptions = true);

  void call_VM(Register oop_result,

               address entry_point,

               Register arg_1, Register arg_2, Register arg_3,

               bool check_exceptions = true);

  // Overloadings with last_Java_sp

  void call_VM(Register oop_result,

               Register last_java_sp,

               address entry_point,

               int number_of_arguments = 0,

               bool check_exceptions = true);

  void call_VM(Register oop_result,

               Register last_java_sp,

               address entry_point,

               Register arg_1, bool

               check_exceptions = true);

  void call_VM(Register oop_result,

               Register last_java_sp,

               address entry_point,

               Register arg_1, Register arg_2,

               bool check_exceptions = true);

  void call_VM(Register oop_result,

               Register last_java_sp,

               address entry_point,

               Register arg_1, Register arg_2, Register arg_3,

               bool check_exceptions = true);

  void get_vm_result  (Register oop_result, Register thread);

  void get_vm_result_2(Register metadata_result, Register thread);

  // These always tightly bind to MacroAssembler::call_VM_base

  // bypassing the virtual implementation

  void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);

  void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);

  void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);

  void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);

  void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);

  void call_VM_leaf(address entry_point,

                    int number_of_arguments = 0);

  void call_VM_leaf(address entry_point,

                    Register arg_1);

  void call_VM_leaf(address entry_point,

                    Register arg_1, Register arg_2);

  void call_VM_leaf(address entry_point,

                    Register arg_1, Register arg_2, Register arg_3);

  // These always tightly bind to MacroAssembler::call_VM_leaf_base

  // bypassing the virtual implementation

  void super_call_VM_leaf(address entry_point);

  void super_call_VM_leaf(address entry_point, Register arg_1);

  void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);

  void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);

  void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);

  // last Java Frame (fills frame anchor)

  void set_last_Java_frame(Register thread,

                           Register last_java_sp,

                           Register last_java_fp,

                           address last_java_pc);

  // thread in the default location (r15_thread on 64bit)

  void set_last_Java_frame(Register last_java_sp,

                           Register last_java_fp,

                           address last_java_pc);

  void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);

  // thread in the default location (r15_thread on 64bit)

  void reset_last_Java_frame(bool clear_fp, bool clear_pc);

  // Stores

  void store_check(Register obj);                // store check for obj - register is destroyed afterwards

  void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)

#if INCLUDE_ALL_GCS

  void g1_write_barrier_pre(Register obj,

                            Register pre_val,

                            Register thread,

                            Register tmp,

                            bool tosca_live,

                            bool expand_call);

  void g1_write_barrier_post(Register store_addr,

                             Register new_val,

                             Register thread,

                             Register tmp,

                             Register tmp2);

#endif // INCLUDE_ALL_GCS

  // split store_check(Register obj) to enhance instruction interleaving

  void store_check_part_1(Register obj);

  void store_check_part_2(Register obj);

  // C 'boolean' to Java boolean: x == 0 ? 0 : 1

  void c2bool(Register x);

  // C++ bool manipulation

  void movbool(Register dst, Address src);

  void movbool(Address dst, bool boolconst);

  void movbool(Address dst, Register src);

  void testbool(Register dst);

  // oop manipulations

  void load_klass(Register dst, Register src);

  void store_klass(Register dst, Register src);

  void load_heap_oop(Register dst, Address src);

  void load_heap_oop_not_null(Register dst, Address src);

  void store_heap_oop(Address dst, Register src);

  void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);

  // Used for storing NULL. All other oop constants should be

  // stored using routines that take a jobject.

  void store_heap_oop_null(Address dst);

  void load_prototype_header(Register dst, Register src);

#ifdef _LP64

  void store_klass_gap(Register dst, Register src);

  // This dummy is to prevent a call to store_heap_oop from

  // converting a zero (like NULL) into a Register by giving

  // the compiler two choices it can't resolve

  void store_heap_oop(Address dst, void* dummy);

  void encode_heap_oop(Register r);

  void decode_heap_oop(Register r);

  void encode_heap_oop_not_null(Register r);

  void decode_heap_oop_not_null(Register r);

  void encode_heap_oop_not_null(Register dst, Register src);

  void decode_heap_oop_not_null(Register dst, Register src);

  void set_narrow_oop(Register dst, jobject obj);

  void set_narrow_oop(Address dst, jobject obj);

  void cmp_narrow_oop(Register dst, jobject obj);

  void cmp_narrow_oop(Address dst, jobject obj);

  void encode_klass_not_null(Register r);

  void decode_klass_not_null(Register r);

  void encode_klass_not_null(Register dst, Register src);

  void decode_klass_not_null(Register dst, Register src);

  void set_narrow_klass(Register dst, Klass* k);

  void set_narrow_klass(Address dst, Klass* k);

  void cmp_narrow_klass(Register dst, Klass* k);

  void cmp_narrow_klass(Address dst, Klass* k);

  // Returns the byte size of the instructions generated by decode_klass_not_null()

  // when compressed klass pointers are being used.

  static int instr_size_for_decode_klass_not_null();

  // if heap base register is used - reinit it with the correct value

  void reinit_heapbase();

  DEBUG_ONLY(void verify_heapbase(const char* msg);)

#endif // _LP64

  // Int division/remainder for Java

  // (as idivl, but checks for special case as described in JVM spec.)

  // returns idivl instruction offset for implicit exception handling

  int corrected_idivl(Register reg);

  // Long division/remainder for Java

  // (as idivq, but checks for special case as described in JVM spec.)

  // returns idivq instruction offset for implicit exception handling

  int corrected_idivq(Register reg);

  void int3();

  // Long operation macros for a 32bit cpu

  // Long negation for Java

  void lneg(Register hi, Register lo);

  // Long multiplication for Java

  // (destroys contents of eax, ebx, ecx and edx)

  void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y

  // Long shifts for Java

  // (semantics as described in JVM spec.)

  void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)

  void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)

  // Long compare for Java

  // (semantics as described in JVM spec.)

  void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)

  // misc

  // Sign extension

  void sign_extend_short(Register reg);

  void sign_extend_byte(Register reg);

  // Division by power of 2, rounding towards 0

  void division_with_shift(Register reg, int shift_value);

  // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:

  //

  // CF (corresponds to C0) if x < y

  // PF (corresponds to C2) if unordered

  // ZF (corresponds to C3) if x = y

  //

  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).

  // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)

  void fcmp(Register tmp);

  // Variant of the above which allows y to be further down the stack

  // and which only pops x and y if specified. If pop_right is

  // specified then pop_left must also be specified.

  void fcmp(Register tmp, int index, bool pop_left, bool pop_right);

  // Floating-point comparison for Java

  // Compares the top-most stack entries on the FPU stack and stores the result in dst.

  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).

  // (semantics as described in JVM spec.)

  void fcmp2int(Register dst, bool unordered_is_less);

  // Variant of the above which allows y to be further down the stack

  // and which only pops x and y if specified. If pop_right is

  // specified then pop_left must also be specified.

  void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);

  // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)

  // tmp is a temporary register, if none is available use noreg

  void fremr(Register tmp);

  // same as fcmp2int, but using SSE2

  void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);

  void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);

  // Inlined sin/cos generator for Java; must not use CPU instruction

  // directly on Intel as it does not have high enough precision

  // outside of the range [-pi/4, pi/4]. Extra argument indicate the

  // number of FPU stack slots in use; all but the topmost will

  // require saving if a slow case is necessary. Assumes argument is

  // on FP TOS; result is on FP TOS.  No cpu registers are changed by

  // this code.

  void trigfunc(char trig, int num_fpu_regs_in_use = 1);

  // branch to L if FPU flag C2 is set/not set

  // tmp is a temporary register, if none is available use noreg

  void jC2 (Register tmp, Label& L);

  void jnC2(Register tmp, Label& L);

  // Pop ST (ffree & fincstp combined)

  void fpop();

  // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack

  void push_fTOS();

  // pops double TOS element from CPU stack and pushes on FPU stack

  void pop_fTOS();

  void empty_FPU_stack();

  void push_IU_state();

  void pop_IU_state();

  void push_FPU_state();

  void pop_FPU_state();

  void push_CPU_state();

  void pop_CPU_state();

  // Round up to a power of two

  void round_to(Register reg, int modulus);

  // Callee saved registers handling

  void push_callee_saved_registers();

  void pop_callee_saved_registers();

  // allocation

  void eden_allocate(

    Register obj,                      // result: pointer to object after successful allocation

    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise

    int      con_size_in_bytes,        // object size in bytes if   known at compile time

    Register t1,                       // temp register

    Label&   slow_case                 // continuation point if fast allocation fails

  );

  void tlab_allocate(

    Register obj,                      // result: pointer to object after successful allocation

    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise

    int      con_size_in_bytes,        // object size in bytes if   known at compile time

    Register t1,                       // temp register

    Register t2,                       // temp register

    Label&   slow_case                 // continuation point if fast allocation fails

  );

  Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address

  void incr_allocated_bytes(Register thread,

                            Register var_size_in_bytes, int con_size_in_bytes,

                            Register t1 = noreg);

  // interface method calling

  void lookup_interface_method(Register recv_klass,

                               Register intf_klass,

                               RegisterOrConstant itable_index,

                               Register method_result,